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1da177e4 LT |
1 | /* |
2 | * drivers/i2c/busses/i2c-mv64xxx.c | |
3 | * | |
4 | * Driver for the i2c controller on the Marvell line of host bridges for MIPS | |
5 | * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0). | |
6 | * | |
7 | * Author: Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * 2005 (c) MontaVista, Software, Inc. This file is licensed under | |
10 | * the terms of the GNU General Public License version 2. This program | |
11 | * is licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | */ | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/mv643xx.h> | |
20 | #include <asm/io.h> | |
21 | ||
22 | /* Register defines */ | |
23 | #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 | |
24 | #define MV64XXX_I2C_REG_DATA 0x04 | |
25 | #define MV64XXX_I2C_REG_CONTROL 0x08 | |
26 | #define MV64XXX_I2C_REG_STATUS 0x0c | |
27 | #define MV64XXX_I2C_REG_BAUD 0x0c | |
28 | #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 | |
29 | #define MV64XXX_I2C_REG_SOFT_RESET 0x1c | |
30 | ||
31 | #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 | |
32 | #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 | |
33 | #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 | |
34 | #define MV64XXX_I2C_REG_CONTROL_START 0x00000020 | |
35 | #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 | |
36 | #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 | |
37 | ||
38 | /* Ctlr status values */ | |
39 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 | |
40 | #define MV64XXX_I2C_STATUS_MAST_START 0x08 | |
41 | #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 | |
42 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 | |
43 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 | |
44 | #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 | |
45 | #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 | |
46 | #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 | |
47 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 | |
48 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 | |
49 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 | |
50 | #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 | |
51 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 | |
52 | #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 | |
53 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 | |
54 | #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 | |
55 | #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 | |
56 | ||
57 | /* Driver states */ | |
58 | enum { | |
59 | MV64XXX_I2C_STATE_INVALID, | |
60 | MV64XXX_I2C_STATE_IDLE, | |
61 | MV64XXX_I2C_STATE_WAITING_FOR_START_COND, | |
62 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, | |
63 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, | |
64 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, | |
65 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, | |
66 | MV64XXX_I2C_STATE_ABORTING, | |
67 | }; | |
68 | ||
69 | /* Driver actions */ | |
70 | enum { | |
71 | MV64XXX_I2C_ACTION_INVALID, | |
72 | MV64XXX_I2C_ACTION_CONTINUE, | |
73 | MV64XXX_I2C_ACTION_SEND_START, | |
74 | MV64XXX_I2C_ACTION_SEND_ADDR_1, | |
75 | MV64XXX_I2C_ACTION_SEND_ADDR_2, | |
76 | MV64XXX_I2C_ACTION_SEND_DATA, | |
77 | MV64XXX_I2C_ACTION_RCV_DATA, | |
78 | MV64XXX_I2C_ACTION_RCV_DATA_STOP, | |
79 | MV64XXX_I2C_ACTION_SEND_STOP, | |
80 | }; | |
81 | ||
82 | struct mv64xxx_i2c_data { | |
83 | int irq; | |
84 | u32 state; | |
85 | u32 action; | |
86 | u32 cntl_bits; | |
87 | void __iomem *reg_base; | |
88 | u32 reg_base_p; | |
89 | u32 addr1; | |
90 | u32 addr2; | |
91 | u32 bytes_left; | |
92 | u32 byte_posn; | |
93 | u32 block; | |
94 | int rc; | |
95 | u32 freq_m; | |
96 | u32 freq_n; | |
97 | wait_queue_head_t waitq; | |
98 | spinlock_t lock; | |
99 | struct i2c_msg *msg; | |
100 | struct i2c_adapter adapter; | |
101 | }; | |
102 | ||
103 | /* | |
104 | ***************************************************************************** | |
105 | * | |
106 | * Finite State Machine & Interrupt Routines | |
107 | * | |
108 | ***************************************************************************** | |
109 | */ | |
110 | static void | |
111 | mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) | |
112 | { | |
113 | /* | |
114 | * If state is idle, then this is likely the remnants of an old | |
115 | * operation that driver has given up on or the user has killed. | |
116 | * If so, issue the stop condition and go to idle. | |
117 | */ | |
118 | if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { | |
119 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
120 | return; | |
121 | } | |
122 | ||
123 | if (drv_data->state == MV64XXX_I2C_STATE_ABORTING) { | |
124 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
125 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
126 | return; | |
127 | } | |
128 | ||
129 | /* The status from the ctlr [mostly] tells us what to do next */ | |
130 | switch (status) { | |
131 | /* Start condition interrupt */ | |
132 | case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ | |
133 | case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ | |
134 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; | |
135 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; | |
136 | break; | |
137 | ||
138 | /* Performing a write */ | |
139 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ | |
140 | if (drv_data->msg->flags & I2C_M_TEN) { | |
141 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
142 | drv_data->state = | |
143 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
144 | break; | |
145 | } | |
146 | /* FALLTHRU */ | |
147 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ | |
148 | case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ | |
149 | if (drv_data->bytes_left > 0) { | |
150 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; | |
151 | drv_data->state = | |
152 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
153 | drv_data->bytes_left--; | |
154 | } else { | |
155 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
156 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
157 | } | |
158 | break; | |
159 | ||
160 | /* Performing a read */ | |
161 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ | |
162 | if (drv_data->msg->flags & I2C_M_TEN) { | |
163 | drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; | |
164 | drv_data->state = | |
165 | MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; | |
166 | break; | |
167 | } | |
168 | /* FALLTHRU */ | |
169 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ | |
170 | if (drv_data->bytes_left == 0) { | |
171 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
172 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
173 | break; | |
174 | } | |
175 | /* FALLTHRU */ | |
176 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ | |
177 | if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) | |
178 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
179 | else { | |
180 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; | |
181 | drv_data->bytes_left--; | |
182 | } | |
183 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
184 | ||
185 | if (drv_data->bytes_left == 1) | |
186 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; | |
187 | break; | |
188 | ||
189 | case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ | |
190 | drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; | |
191 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
192 | break; | |
193 | ||
194 | case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ | |
195 | case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ | |
196 | case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ | |
197 | /* Doesn't seem to be a device at other end */ | |
198 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
199 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
200 | drv_data->rc = -ENODEV; | |
201 | break; | |
202 | ||
203 | default: | |
204 | dev_err(&drv_data->adapter.dev, | |
205 | "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " | |
206 | "status: 0x%x, addr: 0x%x, flags: 0x%x\n", | |
207 | drv_data->state, status, drv_data->msg->addr, | |
208 | drv_data->msg->flags); | |
209 | drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; | |
210 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
211 | drv_data->rc = -EIO; | |
212 | } | |
213 | } | |
214 | ||
215 | static void | |
216 | mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) | |
217 | { | |
218 | switch(drv_data->action) { | |
219 | case MV64XXX_I2C_ACTION_CONTINUE: | |
220 | writel(drv_data->cntl_bits, | |
221 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
222 | break; | |
223 | ||
224 | case MV64XXX_I2C_ACTION_SEND_START: | |
225 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, | |
226 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
227 | break; | |
228 | ||
229 | case MV64XXX_I2C_ACTION_SEND_ADDR_1: | |
230 | writel(drv_data->addr1, | |
231 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
232 | writel(drv_data->cntl_bits, | |
233 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
234 | break; | |
235 | ||
236 | case MV64XXX_I2C_ACTION_SEND_ADDR_2: | |
237 | writel(drv_data->addr2, | |
238 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
239 | writel(drv_data->cntl_bits, | |
240 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
241 | break; | |
242 | ||
243 | case MV64XXX_I2C_ACTION_SEND_DATA: | |
244 | writel(drv_data->msg->buf[drv_data->byte_posn++], | |
245 | drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
246 | writel(drv_data->cntl_bits, | |
247 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
248 | break; | |
249 | ||
250 | case MV64XXX_I2C_ACTION_RCV_DATA: | |
251 | drv_data->msg->buf[drv_data->byte_posn++] = | |
252 | readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
253 | writel(drv_data->cntl_bits, | |
254 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
255 | break; | |
256 | ||
257 | case MV64XXX_I2C_ACTION_RCV_DATA_STOP: | |
258 | drv_data->msg->buf[drv_data->byte_posn++] = | |
259 | readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); | |
260 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
261 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
262 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
263 | drv_data->block = 0; | |
264 | wake_up_interruptible(&drv_data->waitq); | |
265 | break; | |
266 | ||
267 | case MV64XXX_I2C_ACTION_INVALID: | |
268 | default: | |
269 | dev_err(&drv_data->adapter.dev, | |
270 | "mv64xxx_i2c_do_action: Invalid action: %d\n", | |
271 | drv_data->action); | |
272 | drv_data->rc = -EIO; | |
273 | /* FALLTHRU */ | |
274 | case MV64XXX_I2C_ACTION_SEND_STOP: | |
275 | drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; | |
276 | writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, | |
277 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
278 | drv_data->block = 0; | |
279 | wake_up_interruptible(&drv_data->waitq); | |
280 | break; | |
281 | } | |
282 | } | |
283 | ||
284 | static int | |
285 | mv64xxx_i2c_intr(int irq, void *dev_id, struct pt_regs *regs) | |
286 | { | |
287 | struct mv64xxx_i2c_data *drv_data = dev_id; | |
288 | unsigned long flags; | |
289 | u32 status; | |
290 | int rc = IRQ_NONE; | |
291 | ||
292 | spin_lock_irqsave(&drv_data->lock, flags); | |
293 | while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & | |
294 | MV64XXX_I2C_REG_CONTROL_IFLG) { | |
295 | status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); | |
296 | mv64xxx_i2c_fsm(drv_data, status); | |
297 | mv64xxx_i2c_do_action(drv_data); | |
298 | rc = IRQ_HANDLED; | |
299 | } | |
300 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
301 | ||
302 | return rc; | |
303 | } | |
304 | ||
305 | /* | |
306 | ***************************************************************************** | |
307 | * | |
308 | * I2C Msg Execution Routines | |
309 | * | |
310 | ***************************************************************************** | |
311 | */ | |
312 | static void | |
313 | mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, | |
314 | struct i2c_msg *msg) | |
315 | { | |
316 | u32 dir = 0; | |
317 | ||
318 | drv_data->msg = msg; | |
319 | drv_data->byte_posn = 0; | |
320 | drv_data->bytes_left = msg->len; | |
321 | drv_data->rc = 0; | |
322 | drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | | |
323 | MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; | |
324 | ||
325 | if (msg->flags & I2C_M_RD) | |
326 | dir = 1; | |
327 | ||
328 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
329 | dir ^= 1; | |
330 | ||
331 | if (msg->flags & I2C_M_TEN) { | |
332 | drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; | |
333 | drv_data->addr2 = (u32)msg->addr & 0xff; | |
334 | } else { | |
335 | drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; | |
336 | drv_data->addr2 = 0; | |
337 | } | |
338 | } | |
339 | ||
340 | static void | |
341 | mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) | |
342 | { | |
343 | long time_left; | |
344 | unsigned long flags; | |
345 | char abort = 0; | |
346 | ||
347 | time_left = wait_event_interruptible_timeout(drv_data->waitq, | |
348 | !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout)); | |
349 | ||
350 | spin_lock_irqsave(&drv_data->lock, flags); | |
351 | if (!time_left) { /* Timed out */ | |
352 | drv_data->rc = -ETIMEDOUT; | |
353 | abort = 1; | |
354 | } else if (time_left < 0) { /* Interrupted/Error */ | |
355 | drv_data->rc = time_left; /* errno value */ | |
356 | abort = 1; | |
357 | } | |
358 | ||
359 | if (abort && drv_data->block) { | |
360 | drv_data->state = MV64XXX_I2C_STATE_ABORTING; | |
361 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
362 | ||
363 | time_left = wait_event_timeout(drv_data->waitq, | |
364 | !drv_data->block, | |
365 | msecs_to_jiffies(drv_data->adapter.timeout)); | |
366 | ||
367 | if (time_left <= 0) { | |
368 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
369 | dev_err(&drv_data->adapter.dev, | |
370 | "mv64xxx: I2C bus locked\n"); | |
371 | } | |
372 | } else | |
373 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
374 | } | |
375 | ||
376 | static int | |
377 | mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg) | |
378 | { | |
379 | unsigned long flags; | |
380 | ||
381 | spin_lock_irqsave(&drv_data->lock, flags); | |
382 | mv64xxx_i2c_prepare_for_io(drv_data, msg); | |
383 | ||
384 | if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ | |
385 | if (drv_data->msg->flags & I2C_M_RD) { | |
386 | /* No action to do, wait for slave to send a byte */ | |
387 | drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; | |
388 | drv_data->state = | |
389 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; | |
390 | } else { | |
391 | drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; | |
392 | drv_data->state = | |
393 | MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; | |
394 | drv_data->bytes_left--; | |
395 | } | |
396 | } else { | |
397 | drv_data->action = MV64XXX_I2C_ACTION_SEND_START; | |
398 | drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; | |
399 | } | |
400 | ||
401 | drv_data->block = 1; | |
402 | mv64xxx_i2c_do_action(drv_data); | |
403 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
404 | ||
405 | mv64xxx_i2c_wait_for_completion(drv_data); | |
406 | return drv_data->rc; | |
407 | } | |
408 | ||
409 | /* | |
410 | ***************************************************************************** | |
411 | * | |
412 | * I2C Core Support Routines (Interface to higher level I2C code) | |
413 | * | |
414 | ***************************************************************************** | |
415 | */ | |
416 | static u32 | |
417 | mv64xxx_i2c_functionality(struct i2c_adapter *adap) | |
418 | { | |
419 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; | |
420 | } | |
421 | ||
422 | static int | |
423 | mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
424 | { | |
425 | struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); | |
d1b2f0a9 | 426 | int i, rc; |
1da177e4 LT |
427 | |
428 | for (i=0; i<num; i++) | |
d1b2f0a9 JD |
429 | if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0) |
430 | return rc; | |
1da177e4 | 431 | |
d1b2f0a9 | 432 | return num; |
1da177e4 LT |
433 | } |
434 | ||
435 | static struct i2c_algorithm mv64xxx_i2c_algo = { | |
1da177e4 LT |
436 | .master_xfer = mv64xxx_i2c_xfer, |
437 | .functionality = mv64xxx_i2c_functionality, | |
438 | }; | |
439 | ||
440 | /* | |
441 | ***************************************************************************** | |
442 | * | |
443 | * Driver Interface & Early Init Routines | |
444 | * | |
445 | ***************************************************************************** | |
446 | */ | |
447 | static void __devinit | |
448 | mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) | |
449 | { | |
450 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); | |
451 | writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), | |
452 | drv_data->reg_base + MV64XXX_I2C_REG_BAUD); | |
453 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); | |
454 | writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); | |
455 | writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, | |
456 | drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); | |
457 | drv_data->state = MV64XXX_I2C_STATE_IDLE; | |
458 | } | |
459 | ||
460 | static int __devinit | |
461 | mv64xxx_i2c_map_regs(struct platform_device *pd, | |
462 | struct mv64xxx_i2c_data *drv_data) | |
463 | { | |
464 | struct resource *r; | |
465 | ||
466 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) && | |
467 | request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE, | |
468 | drv_data->adapter.name)) { | |
469 | ||
470 | drv_data->reg_base = ioremap(r->start, | |
471 | MV64XXX_I2C_REG_BLOCK_SIZE); | |
472 | drv_data->reg_base_p = r->start; | |
473 | } else | |
474 | return -ENOMEM; | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static void __devexit | |
480 | mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) | |
481 | { | |
482 | if (drv_data->reg_base) { | |
483 | iounmap(drv_data->reg_base); | |
484 | release_mem_region(drv_data->reg_base_p, | |
485 | MV64XXX_I2C_REG_BLOCK_SIZE); | |
486 | } | |
487 | ||
488 | drv_data->reg_base = NULL; | |
489 | drv_data->reg_base_p = 0; | |
490 | } | |
491 | ||
492 | static int __devinit | |
493 | mv64xxx_i2c_probe(struct device *dev) | |
494 | { | |
495 | struct platform_device *pd = to_platform_device(dev); | |
496 | struct mv64xxx_i2c_data *drv_data; | |
497 | struct mv64xxx_i2c_pdata *pdata = dev->platform_data; | |
498 | int rc; | |
499 | ||
500 | if ((pd->id != 0) || !pdata) | |
501 | return -ENODEV; | |
502 | ||
503 | drv_data = kmalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); | |
504 | ||
505 | if (!drv_data) | |
506 | return -ENOMEM; | |
507 | ||
508 | memset(drv_data, 0, sizeof(struct mv64xxx_i2c_data)); | |
509 | ||
510 | if (mv64xxx_i2c_map_regs(pd, drv_data)) { | |
511 | rc = -ENODEV; | |
512 | goto exit_kfree; | |
513 | } | |
514 | ||
515 | strncpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", | |
516 | I2C_NAME_SIZE); | |
517 | ||
518 | init_waitqueue_head(&drv_data->waitq); | |
519 | spin_lock_init(&drv_data->lock); | |
520 | ||
521 | drv_data->freq_m = pdata->freq_m; | |
522 | drv_data->freq_n = pdata->freq_n; | |
523 | drv_data->irq = platform_get_irq(pd, 0); | |
c7a46533 | 524 | drv_data->adapter.id = I2C_HW_MV64XXX; |
1da177e4 LT |
525 | drv_data->adapter.algo = &mv64xxx_i2c_algo; |
526 | drv_data->adapter.owner = THIS_MODULE; | |
527 | drv_data->adapter.class = I2C_CLASS_HWMON; | |
528 | drv_data->adapter.timeout = pdata->timeout; | |
529 | drv_data->adapter.retries = pdata->retries; | |
530 | dev_set_drvdata(dev, drv_data); | |
531 | i2c_set_adapdata(&drv_data->adapter, drv_data); | |
532 | ||
533 | if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, | |
534 | MV64XXX_I2C_CTLR_NAME, drv_data)) { | |
535 | ||
536 | dev_err(dev, "mv64xxx: Can't register intr handler " | |
537 | "irq: %d\n", drv_data->irq); | |
538 | rc = -EINVAL; | |
539 | goto exit_unmap_regs; | |
540 | } else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) { | |
541 | dev_err(dev, "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); | |
542 | goto exit_free_irq; | |
543 | } | |
544 | ||
545 | mv64xxx_i2c_hw_init(drv_data); | |
546 | ||
547 | return 0; | |
548 | ||
549 | exit_free_irq: | |
550 | free_irq(drv_data->irq, drv_data); | |
551 | exit_unmap_regs: | |
552 | mv64xxx_i2c_unmap_regs(drv_data); | |
553 | exit_kfree: | |
554 | kfree(drv_data); | |
555 | return rc; | |
556 | } | |
557 | ||
558 | static int __devexit | |
559 | mv64xxx_i2c_remove(struct device *dev) | |
560 | { | |
561 | struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev); | |
562 | int rc; | |
563 | ||
564 | rc = i2c_del_adapter(&drv_data->adapter); | |
565 | free_irq(drv_data->irq, drv_data); | |
566 | mv64xxx_i2c_unmap_regs(drv_data); | |
567 | kfree(drv_data); | |
568 | ||
569 | return rc; | |
570 | } | |
571 | ||
572 | static struct device_driver mv64xxx_i2c_driver = { | |
0cf36281 | 573 | .owner = THIS_MODULE, |
1da177e4 LT |
574 | .name = MV64XXX_I2C_CTLR_NAME, |
575 | .bus = &platform_bus_type, | |
576 | .probe = mv64xxx_i2c_probe, | |
577 | .remove = mv64xxx_i2c_remove, | |
578 | }; | |
579 | ||
580 | static int __init | |
581 | mv64xxx_i2c_init(void) | |
582 | { | |
583 | return driver_register(&mv64xxx_i2c_driver); | |
584 | } | |
585 | ||
586 | static void __exit | |
587 | mv64xxx_i2c_exit(void) | |
588 | { | |
589 | driver_unregister(&mv64xxx_i2c_driver); | |
590 | } | |
591 | ||
592 | module_init(mv64xxx_i2c_init); | |
593 | module_exit(mv64xxx_i2c_exit); | |
594 | ||
595 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); | |
596 | MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); | |
597 | MODULE_LICENSE("GPL"); |