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a8da7fec WS |
1 | /* |
2 | * Freescale MXS I2C bus driver | |
3 | * | |
4 | * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. | |
5 | * | |
6 | * based on a (non-working) driver which was: | |
7 | * | |
8 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
9 | * | |
10 | * TODO: add dma-support if platform-support for it is available | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/slab.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/i2c.h> | |
23 | #include <linux/err.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/completion.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/jiffies.h> | |
28 | #include <linux/io.h> | |
d98d033c | 29 | #include <linux/pinctrl/consumer.h> |
a8da7fec WS |
30 | |
31 | #include <mach/common.h> | |
32 | ||
33 | #define DRIVER_NAME "mxs-i2c" | |
34 | ||
35 | #define MXS_I2C_CTRL0 (0x00) | |
36 | #define MXS_I2C_CTRL0_SET (0x04) | |
37 | ||
38 | #define MXS_I2C_CTRL0_SFTRST 0x80000000 | |
39 | #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 | |
40 | #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 | |
41 | #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 | |
42 | #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 | |
43 | #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000 | |
44 | #define MXS_I2C_CTRL0_DIRECTION 0x00010000 | |
45 | #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) | |
46 | ||
47 | #define MXS_I2C_CTRL1 (0x40) | |
48 | #define MXS_I2C_CTRL1_SET (0x44) | |
49 | #define MXS_I2C_CTRL1_CLR (0x48) | |
50 | ||
51 | #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80 | |
52 | #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | |
53 | #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | |
54 | #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | |
55 | #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08 | |
56 | #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04 | |
57 | #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02 | |
58 | #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 | |
59 | ||
60 | #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \ | |
61 | MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \ | |
62 | MXS_I2C_CTRL1_EARLY_TERM_IRQ | \ | |
63 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \ | |
64 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ | |
65 | MXS_I2C_CTRL1_SLAVE_IRQ) | |
66 | ||
67 | #define MXS_I2C_QUEUECTRL (0x60) | |
68 | #define MXS_I2C_QUEUECTRL_SET (0x64) | |
69 | #define MXS_I2C_QUEUECTRL_CLR (0x68) | |
70 | ||
71 | #define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20 | |
72 | #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04 | |
73 | ||
74 | #define MXS_I2C_QUEUESTAT (0x70) | |
75 | #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 | |
844990da | 76 | #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F |
a8da7fec WS |
77 | |
78 | #define MXS_I2C_QUEUECMD (0x80) | |
79 | ||
80 | #define MXS_I2C_QUEUEDATA (0x90) | |
81 | ||
82 | #define MXS_I2C_DATA (0xa0) | |
83 | ||
84 | ||
85 | #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ | |
86 | MXS_I2C_CTRL0_PRE_SEND_START | \ | |
87 | MXS_I2C_CTRL0_MASTER_MODE | \ | |
88 | MXS_I2C_CTRL0_DIRECTION | \ | |
89 | MXS_I2C_CTRL0_XFER_COUNT(1)) | |
90 | ||
91 | #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \ | |
92 | MXS_I2C_CTRL0_MASTER_MODE | \ | |
93 | MXS_I2C_CTRL0_DIRECTION) | |
94 | ||
95 | #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ | |
96 | MXS_I2C_CTRL0_MASTER_MODE) | |
97 | ||
98 | /** | |
99 | * struct mxs_i2c_dev - per device, private MXS-I2C data | |
100 | * | |
101 | * @dev: driver model device node | |
102 | * @regs: IO registers pointer | |
103 | * @cmd_complete: completion object for transaction wait | |
104 | * @cmd_err: error code for last transaction | |
105 | * @adapter: i2c subsystem adapter node | |
106 | */ | |
107 | struct mxs_i2c_dev { | |
108 | struct device *dev; | |
109 | void __iomem *regs; | |
110 | struct completion cmd_complete; | |
111 | u32 cmd_err; | |
112 | struct i2c_adapter adapter; | |
113 | }; | |
114 | ||
115 | /* | |
116 | * TODO: check if calls to here are really needed. If not, we could get rid of | |
117 | * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably. | |
118 | */ | |
119 | static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) | |
120 | { | |
121 | mxs_reset_block(i2c->regs); | |
122 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); | |
6b7d815c SH |
123 | writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, |
124 | i2c->regs + MXS_I2C_QUEUECTRL_SET); | |
a8da7fec WS |
125 | } |
126 | ||
127 | static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len, | |
128 | int flags) | |
129 | { | |
130 | u32 data; | |
131 | ||
132 | writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD); | |
133 | ||
134 | data = (addr << 1) | I2C_SMBUS_READ; | |
135 | writel(data, i2c->regs + MXS_I2C_DATA); | |
136 | ||
137 | data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags; | |
138 | writel(data, i2c->regs + MXS_I2C_QUEUECMD); | |
139 | } | |
140 | ||
141 | static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c, | |
142 | u8 addr, u8 *buf, int len, int flags) | |
143 | { | |
144 | u32 data; | |
145 | int i, shifts_left; | |
146 | ||
147 | data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags; | |
148 | writel(data, i2c->regs + MXS_I2C_QUEUECMD); | |
149 | ||
150 | /* | |
151 | * We have to copy the slave address (u8) and buffer (arbitrary number | |
152 | * of u8) into the data register (u32). To achieve that, the u8 are put | |
153 | * into the MSBs of 'data' which is then shifted for the next u8. When | |
25985edc | 154 | * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32 |
a8da7fec WS |
155 | * looks like this: |
156 | * | |
157 | * 3 2 1 0 | |
158 | * 10987654|32109876|54321098|76543210 | |
159 | * --------+--------+--------+-------- | |
160 | * buffer+2|buffer+1|buffer+0|slave_addr | |
161 | */ | |
162 | ||
163 | data = ((addr << 1) | I2C_SMBUS_WRITE) << 24; | |
164 | ||
165 | for (i = 0; i < len; i++) { | |
166 | data >>= 8; | |
167 | data |= buf[i] << 24; | |
168 | if ((i & 3) == 2) | |
169 | writel(data, i2c->regs + MXS_I2C_DATA); | |
170 | } | |
171 | ||
172 | /* Write out the remaining bytes if any */ | |
173 | shifts_left = 24 - (i & 3) * 8; | |
174 | if (shifts_left) | |
175 | writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA); | |
176 | } | |
177 | ||
178 | /* | |
179 | * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the | |
180 | * rd_threshold to 1). Couldn't get this to work, though. | |
181 | */ | |
182 | static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c) | |
183 | { | |
184 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | |
185 | ||
186 | while (readl(i2c->regs + MXS_I2C_QUEUESTAT) | |
187 | & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) { | |
188 | if (time_after(jiffies, timeout)) | |
189 | return -ETIMEDOUT; | |
190 | cond_resched(); | |
191 | } | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len) | |
197 | { | |
198 | u32 data; | |
199 | int i; | |
200 | ||
201 | for (i = 0; i < len; i++) { | |
202 | if ((i & 3) == 0) { | |
203 | if (mxs_i2c_wait_for_data(i2c)) | |
204 | return -ETIMEDOUT; | |
205 | data = readl(i2c->regs + MXS_I2C_QUEUEDATA); | |
206 | } | |
207 | buf[i] = data & 0xff; | |
208 | data >>= 8; | |
209 | } | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | /* | |
215 | * Low level master read/write transaction. | |
216 | */ | |
217 | static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, | |
218 | int stop) | |
219 | { | |
220 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
221 | int ret; | |
222 | int flags; | |
223 | ||
a8da7fec WS |
224 | dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", |
225 | msg->addr, msg->len, msg->flags, stop); | |
226 | ||
227 | if (msg->len == 0) | |
228 | return -EINVAL; | |
229 | ||
844990da | 230 | init_completion(&i2c->cmd_complete); |
c95eeae9 | 231 | i2c->cmd_err = 0; |
844990da | 232 | |
a8da7fec WS |
233 | flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; |
234 | ||
235 | if (msg->flags & I2C_M_RD) | |
236 | mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags); | |
237 | else | |
238 | mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len, | |
239 | flags); | |
240 | ||
241 | writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, | |
242 | i2c->regs + MXS_I2C_QUEUECTRL_SET); | |
243 | ||
244 | ret = wait_for_completion_timeout(&i2c->cmd_complete, | |
245 | msecs_to_jiffies(1000)); | |
246 | if (ret == 0) | |
247 | goto timeout; | |
248 | ||
249 | if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) { | |
250 | ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len); | |
251 | if (ret) | |
252 | goto timeout; | |
253 | } | |
254 | ||
255 | if (i2c->cmd_err == -ENXIO) | |
256 | mxs_i2c_reset(i2c); | |
1e4f0b82 WS |
257 | else |
258 | writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, | |
259 | i2c->regs + MXS_I2C_QUEUECTRL_CLR); | |
a8da7fec WS |
260 | |
261 | dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err); | |
262 | ||
263 | return i2c->cmd_err; | |
264 | ||
265 | timeout: | |
266 | dev_dbg(i2c->dev, "Timeout!\n"); | |
267 | mxs_i2c_reset(i2c); | |
268 | return -ETIMEDOUT; | |
269 | } | |
270 | ||
271 | static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |
272 | int num) | |
273 | { | |
274 | int i; | |
275 | int err; | |
276 | ||
277 | for (i = 0; i < num; i++) { | |
278 | err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1)); | |
279 | if (err) | |
280 | return err; | |
281 | } | |
282 | ||
283 | return num; | |
284 | } | |
285 | ||
286 | static u32 mxs_i2c_func(struct i2c_adapter *adap) | |
287 | { | |
288 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
289 | } | |
290 | ||
291 | static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) | |
292 | { | |
293 | struct mxs_i2c_dev *i2c = dev_id; | |
294 | u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; | |
844990da | 295 | bool is_last_cmd; |
a8da7fec WS |
296 | |
297 | if (!stat) | |
298 | return IRQ_NONE; | |
299 | ||
300 | if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) | |
301 | i2c->cmd_err = -ENXIO; | |
302 | else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | | |
303 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | | |
304 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ)) | |
305 | /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ | |
306 | i2c->cmd_err = -EIO; | |
a8da7fec | 307 | |
844990da WS |
308 | is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & |
309 | MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; | |
310 | ||
311 | if (is_last_cmd || i2c->cmd_err) | |
312 | complete(&i2c->cmd_complete); | |
a8da7fec WS |
313 | |
314 | writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); | |
844990da | 315 | |
a8da7fec WS |
316 | return IRQ_HANDLED; |
317 | } | |
318 | ||
319 | static const struct i2c_algorithm mxs_i2c_algo = { | |
320 | .master_xfer = mxs_i2c_xfer, | |
321 | .functionality = mxs_i2c_func, | |
322 | }; | |
323 | ||
324 | static int __devinit mxs_i2c_probe(struct platform_device *pdev) | |
325 | { | |
326 | struct device *dev = &pdev->dev; | |
327 | struct mxs_i2c_dev *i2c; | |
328 | struct i2c_adapter *adap; | |
d98d033c | 329 | struct pinctrl *pinctrl; |
a8da7fec WS |
330 | struct resource *res; |
331 | resource_size_t res_size; | |
332 | int err, irq; | |
333 | ||
d98d033c SG |
334 | pinctrl = devm_pinctrl_get_select_default(dev); |
335 | if (IS_ERR(pinctrl)) | |
336 | return PTR_ERR(pinctrl); | |
337 | ||
a8da7fec WS |
338 | i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); |
339 | if (!i2c) | |
340 | return -ENOMEM; | |
341 | ||
342 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
343 | if (!res) | |
344 | return -ENOENT; | |
345 | ||
346 | res_size = resource_size(res); | |
347 | if (!devm_request_mem_region(dev, res->start, res_size, res->name)) | |
348 | return -EBUSY; | |
349 | ||
350 | i2c->regs = devm_ioremap_nocache(dev, res->start, res_size); | |
351 | if (!i2c->regs) | |
352 | return -EBUSY; | |
353 | ||
354 | irq = platform_get_irq(pdev, 0); | |
355 | if (irq < 0) | |
356 | return irq; | |
357 | ||
358 | err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c); | |
359 | if (err) | |
360 | return err; | |
361 | ||
362 | i2c->dev = dev; | |
363 | platform_set_drvdata(pdev, i2c); | |
364 | ||
365 | /* Do reset to enforce correct startup after pinmuxing */ | |
366 | mxs_i2c_reset(i2c); | |
a8da7fec WS |
367 | |
368 | adap = &i2c->adapter; | |
369 | strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); | |
370 | adap->owner = THIS_MODULE; | |
371 | adap->algo = &mxs_i2c_algo; | |
372 | adap->dev.parent = dev; | |
373 | adap->nr = pdev->id; | |
374 | i2c_set_adapdata(adap, i2c); | |
375 | err = i2c_add_numbered_adapter(adap); | |
376 | if (err) { | |
377 | dev_err(dev, "Failed to add adapter (%d)\n", err); | |
378 | writel(MXS_I2C_CTRL0_SFTRST, | |
379 | i2c->regs + MXS_I2C_CTRL0_SET); | |
380 | return err; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static int __devexit mxs_i2c_remove(struct platform_device *pdev) | |
387 | { | |
388 | struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev); | |
389 | int ret; | |
390 | ||
391 | ret = i2c_del_adapter(&i2c->adapter); | |
392 | if (ret) | |
393 | return -EBUSY; | |
394 | ||
a8da7fec WS |
395 | writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET); |
396 | ||
397 | platform_set_drvdata(pdev, NULL); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static struct platform_driver mxs_i2c_driver = { | |
403 | .driver = { | |
404 | .name = DRIVER_NAME, | |
405 | .owner = THIS_MODULE, | |
406 | }, | |
407 | .remove = __devexit_p(mxs_i2c_remove), | |
408 | }; | |
409 | ||
410 | static int __init mxs_i2c_init(void) | |
411 | { | |
412 | return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe); | |
413 | } | |
414 | subsys_initcall(mxs_i2c_init); | |
415 | ||
416 | static void __exit mxs_i2c_exit(void) | |
417 | { | |
418 | platform_driver_unregister(&mxs_i2c_driver); | |
419 | } | |
420 | module_exit(mxs_i2c_exit); | |
421 | ||
422 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); | |
423 | MODULE_DESCRIPTION("MXS I2C Bus Driver"); | |
424 | MODULE_LICENSE("GPL"); | |
425 | MODULE_ALIAS("platform:" DRIVER_NAME); |