[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-nforce2.c

/*
    SMBus driver for nVidia nForce2 MCP

    Added nForce3 Pro 150  Thomas Leibold <thomas@plx.com>,
	Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
    Copyright (c) 2003  Hans-Frieder Vogt <hfvogt@arcor.de>,
    Based on
    SMBus 2.0 driver for AMD-8111 IO-Hub
    Copyright (c) 2002 Vojtech Pavlik

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
*/

/*
    SUPPORTED DEVICES		PCI ID
    nForce2 MCP			0064
    nForce2 Ultra 400 MCP	0084
    nForce3 Pro150 MCP		00D4
    nForce3 250Gb MCP		00E4
    nForce4 MCP			0052
    nForce4 MCP-04		0034
    nForce MCP51		0264
    nForce MCP55		0368
    nForce MCP61		03EB
    nForce MCP65		0446
    nForce MCP67		0542
    nForce MCP73		07D8
    nForce MCP78S		0752
    nForce MCP79		0AA2

    This driver supports the 2 SMBuses that are included in the MCP of the
    nForce2/3/4/5xx chipsets.
*/

/* Note: we assume there can only be one nForce2, with two SMBus interfaces */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/slab.h>
#include <linux/io.h>

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");


struct nforce2_smbus {
	struct i2c_adapter adapter;
	int base;
	int size;
	int blockops;
	int can_abort;
};


/*
 * nVidia nForce2 SMBus control register definitions
 * (Newer incarnations use standard BARs 4 and 5 instead)
 */
#define NFORCE_PCI_SMB1	0x50
#define NFORCE_PCI_SMB2	0x54


/*
 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
 */
#define NVIDIA_SMB_PRTCL	(smbus->base + 0x00)	/* protocol, PEC */
#define NVIDIA_SMB_STS		(smbus->base + 0x01)	/* status */
#define NVIDIA_SMB_ADDR		(smbus->base + 0x02)	/* address */
#define NVIDIA_SMB_CMD		(smbus->base + 0x03)	/* command */
#define NVIDIA_SMB_DATA		(smbus->base + 0x04)	/* 32 data registers */
#define NVIDIA_SMB_BCNT		(smbus->base + 0x24)	/* number of data
							   bytes */
#define NVIDIA_SMB_STATUS_ABRT	(smbus->base + 0x3c)	/* register used to
							   check the status of
							   the abort command */
#define NVIDIA_SMB_CTRL		(smbus->base + 0x3e)	/* control register */

#define NVIDIA_SMB_STATUS_ABRT_STS	0x01		/* Bit to notify that
							   abort succeeded */
#define NVIDIA_SMB_CTRL_ABORT	0x20
#define NVIDIA_SMB_STS_DONE	0x80
#define NVIDIA_SMB_STS_ALRM	0x40
#define NVIDIA_SMB_STS_RES	0x20
#define NVIDIA_SMB_STS_STATUS	0x1f

#define NVIDIA_SMB_PRTCL_WRITE			0x00
#define NVIDIA_SMB_PRTCL_READ			0x01
#define NVIDIA_SMB_PRTCL_QUICK			0x02
#define NVIDIA_SMB_PRTCL_BYTE			0x04
#define NVIDIA_SMB_PRTCL_BYTE_DATA		0x06
#define NVIDIA_SMB_PRTCL_WORD_DATA		0x08
#define NVIDIA_SMB_PRTCL_BLOCK_DATA		0x0a
#define NVIDIA_SMB_PRTCL_PEC			0x80

/* Misc definitions */
#define MAX_TIMEOUT	100

/* We disable the second SMBus channel on these boards */
static const struct dmi_system_id nforce2_dmi_blacklist2[] = {
	{
		.ident = "DFI Lanparty NF4 Expert",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"),
			DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"),
		},
	},
	{ }
};

static struct pci_driver nforce2_driver;

/* For multiplexing support, we need a global reference to the 1st
   SMBus channel */
#if IS_ENABLED(CONFIG_I2C_NFORCE2_S4985)
struct i2c_adapter *nforce2_smbus;
EXPORT_SYMBOL_GPL(nforce2_smbus);

static void nforce2_set_reference(struct i2c_adapter *adap)
{
	nforce2_smbus = adap;
}
#else
static inline void nforce2_set_reference(struct i2c_adapter *adap) { }
#endif

static void nforce2_abort(struct i2c_adapter *adap)
{
	struct nforce2_smbus *smbus = adap->algo_data;
	int timeout = 0;
	unsigned char temp;

	dev_dbg(&adap->dev, "Aborting current transaction\n");

	outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
	do {
		msleep(1);
		temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
	} while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
			(timeout++ < MAX_TIMEOUT));
	if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
		dev_err(&adap->dev, "Can't reset the smbus\n");
	outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
}

static int nforce2_check_status(struct i2c_adapter *adap)
{
	struct nforce2_smbus *smbus = adap->algo_data;
	int timeout = 0;
	unsigned char temp;

	do {
		msleep(1);
		temp = inb_p(NVIDIA_SMB_STS);
	} while ((!temp) && (timeout++ < MAX_TIMEOUT));

	if (timeout > MAX_TIMEOUT) {
		dev_dbg(&adap->dev, "SMBus Timeout!\n");
		if (smbus->can_abort)
			nforce2_abort(adap);
		return -ETIMEDOUT;
	}
	if (!(temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) {
		dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
		return -EIO;
	}
	return 0;
}

/* Return negative errno on error */
static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
		unsigned short flags, char read_write,
		u8 command, int size, union i2c_smbus_data *data)
{
	struct nforce2_smbus *smbus = adap->algo_data;
	unsigned char protocol, pec;
	u8 len;
	int i, status;

	protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
		NVIDIA_SMB_PRTCL_WRITE;
	pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;

	switch (size) {
	case I2C_SMBUS_QUICK:
		protocol |= NVIDIA_SMB_PRTCL_QUICK;
		read_write = I2C_SMBUS_WRITE;
		break;

	case I2C_SMBUS_BYTE:
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, NVIDIA_SMB_CMD);
		protocol |= NVIDIA_SMB_PRTCL_BYTE;
		break;

	case I2C_SMBUS_BYTE_DATA:
		outb_p(command, NVIDIA_SMB_CMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, NVIDIA_SMB_DATA);
		protocol |= NVIDIA_SMB_PRTCL_BYTE_DATA;
		break;

	case I2C_SMBUS_WORD_DATA:
		outb_p(command, NVIDIA_SMB_CMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word, NVIDIA_SMB_DATA);
			outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
		}
		protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec;
		break;

	case I2C_SMBUS_BLOCK_DATA:
		outb_p(command, NVIDIA_SMB_CMD);
		if (read_write == I2C_SMBUS_WRITE) {
			len = data->block[0];
			if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
				dev_err(&adap->dev,
					"Transaction failed (requested block size: %d)\n",
					len);
				return -EINVAL;
			}
			outb_p(len, NVIDIA_SMB_BCNT);
			for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
				outb_p(data->block[i + 1],
				       NVIDIA_SMB_DATA + i);
		}
		protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec;
		break;

	default:
		dev_err(&adap->dev, "Unsupported transaction %d\n", size);
		return -EOPNOTSUPP;
	}

	outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
	outb_p(protocol, NVIDIA_SMB_PRTCL);

	status = nforce2_check_status(adap);
	if (status)
		return status;

	if (read_write == I2C_SMBUS_WRITE)
		return 0;

	switch (size) {
	case I2C_SMBUS_BYTE:
	case I2C_SMBUS_BYTE_DATA:
		data->byte = inb_p(NVIDIA_SMB_DATA);
		break;

	case I2C_SMBUS_WORD_DATA:
		data->word = inb_p(NVIDIA_SMB_DATA) |
			     (inb_p(NVIDIA_SMB_DATA + 1) << 8);
		break;

	case I2C_SMBUS_BLOCK_DATA:
		len = inb_p(NVIDIA_SMB_BCNT);
		if ((len <= 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
			dev_err(&adap->dev,
				"Transaction failed (received block size: 0x%02x)\n",
				len);
			return -EPROTO;
		}
		for (i = 0; i < len; i++)
			data->block[i + 1] = inb_p(NVIDIA_SMB_DATA + i);
		data->block[0] = len;
		break;
	}

	return 0;
}


static u32 nforce2_func(struct i2c_adapter *adapter)
{
	/* other functionality might be possible, but is not tested */
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	       I2C_FUNC_SMBUS_PEC |
	       (((struct nforce2_smbus *)adapter->algo_data)->blockops ?
		I2C_FUNC_SMBUS_BLOCK_DATA : 0);
}

static struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= nforce2_access,
	.functionality	= nforce2_func,
};


static const struct pci_device_id nforce2_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) },
	{ 0 }
};

MODULE_DEVICE_TABLE(pci, nforce2_ids);


static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,
			     struct nforce2_smbus *smbus, const char *name)
{
	int error;

	smbus->base = pci_resource_start(dev, bar);
	if (smbus->base) {
		smbus->size = pci_resource_len(dev, bar);
	} else {
		/* Older incarnations of the device used non-standard BARs */
		u16 iobase;

		if (pci_read_config_word(dev, alt_reg, &iobase)
		    != PCIBIOS_SUCCESSFUL) {
			dev_err(&dev->dev, "Error reading PCI config for %s\n",
				name);
			return -EIO;
		}

		smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
		smbus->size = 64;
	}

	error = acpi_check_region(smbus->base, smbus->size,
				  nforce2_driver.name);
	if (error)
		return error;

	if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
		dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
			smbus->base, smbus->base+smbus->size-1, name);
		return -EBUSY;
	}
	smbus->adapter.owner = THIS_MODULE;
	smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
	smbus->adapter.algo = &smbus_algorithm;
	smbus->adapter.algo_data = smbus;
	smbus->adapter.dev.parent = &dev->dev;
	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
		"SMBus nForce2 adapter at %04x", smbus->base);

	error = i2c_add_adapter(&smbus->adapter);
	if (error) {
		release_region(smbus->base, smbus->size);
		return error;
	}
	dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n",
		smbus->base);
	return 0;
}


static int nforce2_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct nforce2_smbus *smbuses;
	int res1, res2;

	/* we support 2 SMBus adapters */
	smbuses = kzalloc(2 * sizeof(struct nforce2_smbus), GFP_KERNEL);
	if (!smbuses)
		return -ENOMEM;
	pci_set_drvdata(dev, smbuses);

	switch (dev->device) {
	case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS:
	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
		smbuses[0].blockops = 1;
		smbuses[1].blockops = 1;
		smbuses[0].can_abort = 1;
		smbuses[1].can_abort = 1;
	}

	/* SMBus adapter 1 */
	res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
	if (res1 < 0)
		smbuses[0].base = 0;	/* to have a check value */

	/* SMBus adapter 2 */
	if (dmi_check_system(nforce2_dmi_blacklist2)) {
		dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n");
		res2 = -EPERM;
		smbuses[1].base = 0;
	} else {
		res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1],
					 "SMB2");
		if (res2 < 0)
			smbuses[1].base = 0;	/* to have a check value */
	}

	if ((res1 < 0) && (res2 < 0)) {
		/* we did not find even one of the SMBuses, so we give up */
		kfree(smbuses);
		return -ENODEV;
	}

	nforce2_set_reference(&smbuses[0].adapter);
	return 0;
}


static void nforce2_remove(struct pci_dev *dev)
{
	struct nforce2_smbus *smbuses = pci_get_drvdata(dev);

	nforce2_set_reference(NULL);
	if (smbuses[0].base) {
		i2c_del_adapter(&smbuses[0].adapter);
		release_region(smbuses[0].base, smbuses[0].size);
	}
	if (smbuses[1].base) {
		i2c_del_adapter(&smbuses[1].adapter);
		release_region(smbuses[1].base, smbuses[1].size);
	}
	kfree(smbuses);
}

static struct pci_driver nforce2_driver = {
	.name		= "nForce2_smbus",
	.id_table	= nforce2_ids,
	.probe		= nforce2_probe,
	.remove		= nforce2_remove,
};

module_pci_driver(nforce2_driver);
Commit	Line	Data
1da177e4 LT	1	/*
	2	SMBus driver for nVidia nForce2 MCP
	3
	4	Added nForce3 Pro 150 Thomas Leibold <thomas@plx.com>,
	5	Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
	6	Copyright (c) 2003 Hans-Frieder Vogt <hfvogt@arcor.de>,
	7	Based on
	8	SMBus 2.0 driver for AMD-8111 IO-Hub
	9	Copyright (c) 2002 Vojtech Pavlik
	10
	11	This program is free software; you can redistribute it and/or modify
	12	it under the terms of the GNU General Public License as published by
	13	the Free Software Foundation; either version 2 of the License, or
	14	(at your option) any later version.
	15
	16	This program is distributed in the hope that it will be useful,
	17	but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	GNU General Public License for more details.
1da177e4 LT	20	*/
	21
	22	/*
	23	SUPPORTED DEVICES PCI ID
	24	nForce2 MCP 0064
	25	nForce2 Ultra 400 MCP 0084
	26	nForce3 Pro150 MCP 00D4
	27	nForce3 250Gb MCP 00E4
	28	nForce4 MCP 0052
7c72ccf0	29	nForce4 MCP-04 0034
d2dd14ac JD	30	nForce MCP51 0264
d2dd14ac JD	31	nForce MCP55 0368
f75803de JD	32	nForce MCP61 03EB
f75803de JD	33	nForce MCP65 0446
d2dd14ac JD	34	nForce MCP67 0542
	35	nForce MCP73 07D8
	36	nForce MCP78S 0752
	37	nForce MCP79 0AA2
1da177e4 LT	38
1da177e4 LT	39	This driver supports the 2 SMBuses that are included in the MCP of the
ad04d5c3	40	nForce2/3/4/5xx chipsets.
1da177e4 LT	41	*/
	42
	43	/* Note: we assume there can only be one nForce2, with two SMBus interfaces */
	44
1da177e4 LT	45	#include <linux/module.h>
	46	#include <linux/pci.h>
	47	#include <linux/kernel.h>
	48	#include <linux/stddef.h>
1da177e4	49	#include <linux/ioport.h>
1da177e4 LT	50	#include <linux/i2c.h>
1da177e4 LT	51	#include <linux/delay.h>
08851d6e	52	#include <linux/dmi.h>
54fb4a05	53	#include <linux/acpi.h>
5a0e3ad6	54	#include <linux/slab.h>
21782180	55	#include <linux/io.h>
1da177e4 LT	56
1da177e4 LT	57	MODULE_LICENSE("GPL");
5c38dc89	58	MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
ad04d5c3	59	MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
1da177e4 LT	60
	61
	62	struct nforce2_smbus {
1da177e4 LT	63	struct i2c_adapter adapter;
	64	int base;
	65	int size;
b53c8221	66	int blockops;
d49584c4	67	int can_abort;
1da177e4 LT	68	};
	69
	70
	71	/*
	72	* nVidia nForce2 SMBus control register definitions
5c7ae658	73	* (Newer incarnations use standard BARs 4 and 5 instead)
1da177e4 LT	74	*/
	75	#define NFORCE_PCI_SMB1 0x50
	76	#define NFORCE_PCI_SMB2 0x54
	77
	78
	79	/*
	80	* ACPI 2.0 chapter 13 SMBus 2.0 EC register model
	81	*/
	82	#define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
	83	#define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
	84	#define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
	85	#define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
	86	#define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
b53c8221 OR	87	#define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
b53c8221 OR	88	bytes */
d49584c4 OR	89	#define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
	90	check the status of
	91	the abort command */
	92	#define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
	93
	94	#define NVIDIA_SMB_STATUS_ABRT_STS 0x01 /* Bit to notify that
	95	abort succeeded */
	96	#define NVIDIA_SMB_CTRL_ABORT 0x20
1da177e4 LT	97	#define NVIDIA_SMB_STS_DONE 0x80
	98	#define NVIDIA_SMB_STS_ALRM 0x40
	99	#define NVIDIA_SMB_STS_RES 0x20
	100	#define NVIDIA_SMB_STS_STATUS 0x1f
	101
	102	#define NVIDIA_SMB_PRTCL_WRITE 0x00
	103	#define NVIDIA_SMB_PRTCL_READ 0x01
	104	#define NVIDIA_SMB_PRTCL_QUICK 0x02
	105	#define NVIDIA_SMB_PRTCL_BYTE 0x04
	106	#define NVIDIA_SMB_PRTCL_BYTE_DATA 0x06
	107	#define NVIDIA_SMB_PRTCL_WORD_DATA 0x08
b53c8221	108	#define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a
1da177e4 LT	109	#define NVIDIA_SMB_PRTCL_PEC 0x80
1da177e4 LT	110
41535497 OR	111	/* Misc definitions */
	112	#define MAX_TIMEOUT 100
	113
08851d6e	114	/* We disable the second SMBus channel on these boards */
0b255e92	115	static const struct dmi_system_id nforce2_dmi_blacklist2[] = {
08851d6e JD	116	{
	117	.ident = "DFI Lanparty NF4 Expert",
	118	.matches = {
	119	DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"),
	120	DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"),
	121	},
	122	},
	123	{ }
	124	};
	125
d6072f84	126	static struct pci_driver nforce2_driver;
1da177e4	127
279e9024 JD	128	/* For multiplexing support, we need a global reference to the 1st
279e9024 JD	129	SMBus channel */
dd485951	130	#if IS_ENABLED(CONFIG_I2C_NFORCE2_S4985)
279e9024 JD	131	struct i2c_adapter *nforce2_smbus;
	132	EXPORT_SYMBOL_GPL(nforce2_smbus);
	133
	134	static void nforce2_set_reference(struct i2c_adapter *adap)
	135	{
	136	nforce2_smbus = adap;
	137	}
	138	#else
	139	static inline void nforce2_set_reference(struct i2c_adapter *adap) { }
	140	#endif
	141
d49584c4 OR	142	static void nforce2_abort(struct i2c_adapter *adap)
	143	{
	144	struct nforce2_smbus *smbus = adap->algo_data;
	145	int timeout = 0;
	146	unsigned char temp;
	147
	148	dev_dbg(&adap->dev, "Aborting current transaction\n");
	149
	150	outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
	151	do {
	152	msleep(1);
	153	temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
	154	} while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
	155	(timeout++ < MAX_TIMEOUT));
	156	if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
	157	dev_err(&adap->dev, "Can't reset the smbus\n");
	158	outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
	159	}
	160
41535497 OR	161	static int nforce2_check_status(struct i2c_adapter *adap)
	162	{
	163	struct nforce2_smbus *smbus = adap->algo_data;
	164	int timeout = 0;
	165	unsigned char temp;
	166
	167	do {
	168	msleep(1);
	169	temp = inb_p(NVIDIA_SMB_STS);
	170	} while ((!temp) && (timeout++ < MAX_TIMEOUT));
	171
4ccc28f7	172	if (timeout > MAX_TIMEOUT) {
41535497	173	dev_dbg(&adap->dev, "SMBus Timeout!\n");
d49584c4 OR	174	if (smbus->can_abort)
d49584c4 OR	175	nforce2_abort(adap);
97140342	176	return -ETIMEDOUT;
41535497 OR	177	}
	178	if (!(temp & NVIDIA_SMB_STS_DONE) \|\| (temp & NVIDIA_SMB_STS_STATUS)) {
	179	dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
97140342	180	return -EIO;
41535497 OR	181	}
	182	return 0;
	183	}
	184
97140342	185	/* Return negative errno on error */
5c38dc89	186	static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
1da177e4	187	unsigned short flags, char read_write,
5c38dc89	188	u8 command, int size, union i2c_smbus_data *data)
1da177e4 LT	189	{
1da177e4 LT	190	struct nforce2_smbus *smbus = adap->algo_data;
41535497	191	unsigned char protocol, pec;
b53c8221	192	u8 len;
97140342	193	int i, status;
1da177e4 LT	194
	195	protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
	196	NVIDIA_SMB_PRTCL_WRITE;
	197	pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;
	198
	199	switch (size) {
5c38dc89 LN	200	case I2C_SMBUS_QUICK:
	201	protocol \|= NVIDIA_SMB_PRTCL_QUICK;
	202	read_write = I2C_SMBUS_WRITE;
	203	break;
1da177e4	204
5c38dc89 LN	205	case I2C_SMBUS_BYTE:
5c38dc89 LN	206	if (read_write == I2C_SMBUS_WRITE)
1da177e4	207	outb_p(command, NVIDIA_SMB_CMD);
5c38dc89 LN	208	protocol \|= NVIDIA_SMB_PRTCL_BYTE;
	209	break;
	210
	211	case I2C_SMBUS_BYTE_DATA:
	212	outb_p(command, NVIDIA_SMB_CMD);
	213	if (read_write == I2C_SMBUS_WRITE)
	214	outb_p(data->byte, NVIDIA_SMB_DATA);
	215	protocol \|= NVIDIA_SMB_PRTCL_BYTE_DATA;
	216	break;
	217
	218	case I2C_SMBUS_WORD_DATA:
	219	outb_p(command, NVIDIA_SMB_CMD);
	220	if (read_write == I2C_SMBUS_WRITE) {
	221	outb_p(data->word, NVIDIA_SMB_DATA);
	222	outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
	223	}
	224	protocol \|= NVIDIA_SMB_PRTCL_WORD_DATA \| pec;
	225	break;
	226
	227	case I2C_SMBUS_BLOCK_DATA:
	228	outb_p(command, NVIDIA_SMB_CMD);
	229	if (read_write == I2C_SMBUS_WRITE) {
	230	len = data->block[0];
	231	if ((len == 0) \|\| (len > I2C_SMBUS_BLOCK_MAX)) {
	232	dev_err(&adap->dev,
	233	"Transaction failed (requested block size: %d)\n",
	234	len);
	235	return -EINVAL;
b53c8221	236	}
5c38dc89 LN	237	outb_p(len, NVIDIA_SMB_BCNT);
	238	for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
	239	outb_p(data->block[i + 1],
	240	NVIDIA_SMB_DATA + i);
	241	}
	242	protocol \|= NVIDIA_SMB_PRTCL_BLOCK_DATA \| pec;
	243	break;
b53c8221	244
5c38dc89 LN	245	default:
	246	dev_err(&adap->dev, "Unsupported transaction %d\n", size);
	247	return -EOPNOTSUPP;
1da177e4 LT	248	}
	249
	250	outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
	251	outb_p(protocol, NVIDIA_SMB_PRTCL);
	252
97140342 DB	253	status = nforce2_check_status(adap);
	254	if (status)
	255	return status;
1da177e4 LT	256
	257	if (read_write == I2C_SMBUS_WRITE)
	258	return 0;
	259
	260	switch (size) {
5c38dc89 LN	261	case I2C_SMBUS_BYTE:
	262	case I2C_SMBUS_BYTE_DATA:
	263	data->byte = inb_p(NVIDIA_SMB_DATA);
	264	break;
	265
	266	case I2C_SMBUS_WORD_DATA:
	267	data->word = inb_p(NVIDIA_SMB_DATA) \|
	268	(inb_p(NVIDIA_SMB_DATA + 1) << 8);
	269	break;
	270
	271	case I2C_SMBUS_BLOCK_DATA:
	272	len = inb_p(NVIDIA_SMB_BCNT);
	273	if ((len <= 0) \|\| (len > I2C_SMBUS_BLOCK_MAX)) {
	274	dev_err(&adap->dev,
	275	"Transaction failed (received block size: 0x%02x)\n",
	276	len);
	277	return -EPROTO;
	278	}
	279	for (i = 0; i < len; i++)
	280	data->block[i + 1] = inb_p(NVIDIA_SMB_DATA + i);
	281	data->block[0] = len;
	282	break;
1da177e4 LT	283	}
	284
	285	return 0;
	286	}
	287
	288
	289	static u32 nforce2_func(struct i2c_adapter *adapter)
	290	{
	291	/* other functionality might be possible, but is not tested */
	292	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
b53c8221	293	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
ac3f5753	294	I2C_FUNC_SMBUS_PEC \|
5c38dc89	295	(((struct nforce2_smbus *)adapter->algo_data)->blockops ?
b53c8221	296	I2C_FUNC_SMBUS_BLOCK_DATA : 0);
1da177e4 LT	297	}
1da177e4 LT	298
ad04d5c3 HFV	299	static struct i2c_algorithm smbus_algorithm = {
	300	.smbus_xfer = nforce2_access,
	301	.functionality = nforce2_func,
	302	};
	303
1da177e4	304
392debf1	305	static const struct pci_device_id nforce2_ids[] = {
1da177e4 LT	306	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
	307	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
	308	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
	309	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
	310	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
7c72ccf0	311	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) },
5c7ae658 JD	312	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) },
5c7ae658 JD	313	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) },
f75803de JD	314	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) },
f75803de JD	315	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) },
d2dd14ac JD	316	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) },
	317	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) },
	318	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) },
	319	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) },
1da177e4 LT	320	{ 0 }
	321	};
	322
5c38dc89	323	MODULE_DEVICE_TABLE(pci, nforce2_ids);
1da177e4 LT	324
1da177e4 LT	325
0b255e92 BP	326	static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,
0b255e92 BP	327	struct nforce2_smbus smbus, const char name)
1da177e4	328	{
1da177e4 LT	329	int error;
1da177e4 LT	330
5c7ae658 JD	331	smbus->base = pci_resource_start(dev, bar);
	332	if (smbus->base) {
	333	smbus->size = pci_resource_len(dev, bar);
	334	} else {
	335	/* Older incarnations of the device used non-standard BARs */
	336	u16 iobase;
	337
	338	if (pci_read_config_word(dev, alt_reg, &iobase)
	339	!= PCIBIOS_SUCCESSFUL) {
	340	dev_err(&dev->dev, "Error reading PCI config for %s\n",
	341	name);
97140342	342	return -EIO;
5c7ae658 JD	343	}
	344
	345	smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
ad04d5c3	346	smbus->size = 64;
1da177e4	347	}
1da177e4	348
54fb4a05 JD	349	error = acpi_check_region(smbus->base, smbus->size,
	350	nforce2_driver.name);
	351	if (error)
7c1f59c9	352	return error;
54fb4a05	353
d6072f84	354	if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
1da177e4 LT	355	dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
1da177e4 LT	356	smbus->base, smbus->base+smbus->size-1, name);
97140342	357	return -EBUSY;
1da177e4	358	}
ad04d5c3	359	smbus->adapter.owner = THIS_MODULE;
3401b2ff	360	smbus->adapter.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD;
ad04d5c3	361	smbus->adapter.algo = &smbus_algorithm;
1da177e4 LT	362	smbus->adapter.algo_data = smbus;
1da177e4 LT	363	smbus->adapter.dev.parent = &dev->dev;
2096b956	364	snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
1da177e4 LT	365	"SMBus nForce2 adapter at %04x", smbus->base);
	366
	367	error = i2c_add_adapter(&smbus->adapter);
	368	if (error) {
1da177e4	369	release_region(smbus->base, smbus->size);
97140342	370	return error;
1da177e4	371	}
5c38dc89 LN	372	dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n",
5c38dc89 LN	373	smbus->base);
1da177e4 LT	374	return 0;
	375	}
	376
	377
0b255e92	378	static int nforce2_probe(struct pci_dev dev, const struct pci_device_id id)
1da177e4 LT	379	{
	380	struct nforce2_smbus *smbuses;
	381	int res1, res2;
	382
	383	/* we support 2 SMBus adapters */
5c38dc89 LN	384	smbuses = kzalloc(2 * sizeof(struct nforce2_smbus), GFP_KERNEL);
5c38dc89 LN	385	if (!smbuses)
1da177e4	386	return -ENOMEM;
1da177e4 LT	387	pci_set_drvdata(dev, smbuses);
1da177e4 LT	388
5c38dc89	389	switch (dev->device) {
541b6a7a	390	case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS:
b53c8221 OR	391	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
	392	case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
	393	smbuses[0].blockops = 1;
	394	smbuses[1].blockops = 1;
d49584c4 OR	395	smbuses[0].can_abort = 1;
d49584c4 OR	396	smbuses[1].can_abort = 1;
b53c8221 OR	397	}
b53c8221 OR	398
1da177e4	399	/* SMBus adapter 1 */
5c7ae658	400	res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
7c4fda1a	401	if (res1 < 0)
1da177e4	402	smbuses[0].base = 0; /* to have a check value */
7c4fda1a	403
5c7ae658	404	/* SMBus adapter 2 */
08851d6e JD	405	if (dmi_check_system(nforce2_dmi_blacklist2)) {
	406	dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n");
	407	res2 = -EPERM;
	408	smbuses[1].base = 0;
	409	} else {
	410	res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1],
	411	"SMB2");
7c4fda1a	412	if (res2 < 0)
08851d6e	413	smbuses[1].base = 0; /* to have a check value */
1da177e4	414	}
7c4fda1a	415
1da177e4 LT	416	if ((res1 < 0) && (res2 < 0)) {
	417	/* we did not find even one of the SMBuses, so we give up */
	418	kfree(smbuses);
	419	return -ENODEV;
	420	}
	421
279e9024	422	nforce2_set_reference(&smbuses[0].adapter);
1da177e4 LT	423	return 0;
	424	}
	425
	426
0b255e92	427	static void nforce2_remove(struct pci_dev *dev)
1da177e4	428	{
b18a5c80	429	struct nforce2_smbus *smbuses = pci_get_drvdata(dev);
1da177e4	430
279e9024	431	nforce2_set_reference(NULL);
1da177e4 LT	432	if (smbuses[0].base) {
	433	i2c_del_adapter(&smbuses[0].adapter);
	434	release_region(smbuses[0].base, smbuses[0].size);
	435	}
	436	if (smbuses[1].base) {
	437	i2c_del_adapter(&smbuses[1].adapter);
	438	release_region(smbuses[1].base, smbuses[1].size);
	439	}
	440	kfree(smbuses);
	441	}
	442
	443	static struct pci_driver nforce2_driver = {
	444	.name = "nForce2_smbus",
	445	.id_table = nforce2_ids,
	446	.probe = nforce2_probe,
0b255e92	447	.remove = nforce2_remove,
1da177e4 LT	448	};
1da177e4 LT	449
56f21788	450	module_pci_driver(nforce2_driver);