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3f9900f1 | 1 | /* |
1804edd1 | 2 | * Copyright (C) 2009 ST-Ericsson SA |
3f9900f1 | 3 | * Copyright (C) 2009 STMicroelectronics |
4 | * | |
5 | * I2C master mode controller driver, used in Nomadik 8815 | |
6 | * and Ux500 platforms. | |
7 | * | |
8 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
9 | * Author: Sachin Verma <sachin.verma@st.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2, as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
3f9900f1 | 20 | #include <linux/interrupt.h> |
21 | #include <linux/i2c.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/io.h> | |
25 | ||
26 | #include <plat/i2c.h> | |
27 | ||
28 | #define DRIVER_NAME "nmk-i2c" | |
29 | ||
30 | /* I2C Controller register offsets */ | |
31 | #define I2C_CR (0x000) | |
32 | #define I2C_SCR (0x004) | |
33 | #define I2C_HSMCR (0x008) | |
34 | #define I2C_MCR (0x00C) | |
35 | #define I2C_TFR (0x010) | |
36 | #define I2C_SR (0x014) | |
37 | #define I2C_RFR (0x018) | |
38 | #define I2C_TFTR (0x01C) | |
39 | #define I2C_RFTR (0x020) | |
40 | #define I2C_DMAR (0x024) | |
41 | #define I2C_BRCR (0x028) | |
42 | #define I2C_IMSCR (0x02C) | |
43 | #define I2C_RISR (0x030) | |
44 | #define I2C_MISR (0x034) | |
45 | #define I2C_ICR (0x038) | |
46 | ||
47 | /* Control registers */ | |
48 | #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ | |
49 | #define I2C_CR_OM (0x3 << 1) /* Operating mode */ | |
50 | #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ | |
51 | #define I2C_CR_SM (0x3 << 4) /* Speed mode */ | |
52 | #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ | |
53 | #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ | |
54 | #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ | |
55 | #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ | |
56 | #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ | |
57 | #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ | |
58 | #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ | |
59 | #define I2C_CR_FON (0x3 << 13) /* Filtering on */ | |
60 | #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ | |
61 | ||
62 | /* Master controller (MCR) register */ | |
63 | #define I2C_MCR_OP (0x1 << 0) /* Operation */ | |
64 | #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ | |
65 | #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ | |
66 | #define I2C_MCR_SB (0x1 << 11) /* Extended address */ | |
67 | #define I2C_MCR_AM (0x3 << 12) /* Address type */ | |
68 | #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ | |
69 | #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ | |
70 | ||
71 | /* Status register (SR) */ | |
72 | #define I2C_SR_OP (0x3 << 0) /* Operation */ | |
73 | #define I2C_SR_STATUS (0x3 << 2) /* controller status */ | |
74 | #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ | |
75 | #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ | |
76 | #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ | |
77 | ||
78 | /* Interrupt mask set/clear (IMSCR) bits */ | |
79 | #define I2C_IT_TXFE (0x1 << 0) | |
80 | #define I2C_IT_TXFNE (0x1 << 1) | |
81 | #define I2C_IT_TXFF (0x1 << 2) | |
82 | #define I2C_IT_TXFOVR (0x1 << 3) | |
83 | #define I2C_IT_RXFE (0x1 << 4) | |
84 | #define I2C_IT_RXFNF (0x1 << 5) | |
85 | #define I2C_IT_RXFF (0x1 << 6) | |
86 | #define I2C_IT_RFSR (0x1 << 16) | |
87 | #define I2C_IT_RFSE (0x1 << 17) | |
88 | #define I2C_IT_WTSR (0x1 << 18) | |
89 | #define I2C_IT_MTD (0x1 << 19) | |
90 | #define I2C_IT_STD (0x1 << 20) | |
91 | #define I2C_IT_MAL (0x1 << 24) | |
92 | #define I2C_IT_BERR (0x1 << 25) | |
93 | #define I2C_IT_MTDWS (0x1 << 28) | |
94 | ||
95 | #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) | |
96 | ||
97 | /* some bits in ICR are reserved */ | |
98 | #define I2C_CLEAR_ALL_INTS 0x131f007f | |
99 | ||
100 | /* first three msb bits are reserved */ | |
101 | #define IRQ_MASK(mask) (mask & 0x1fffffff) | |
102 | ||
103 | /* maximum threshold value */ | |
104 | #define MAX_I2C_FIFO_THRESHOLD 15 | |
105 | ||
106 | enum i2c_status { | |
107 | I2C_NOP, | |
108 | I2C_ON_GOING, | |
109 | I2C_OK, | |
110 | I2C_ABORT | |
111 | }; | |
112 | ||
113 | /* operation */ | |
114 | enum i2c_operation { | |
115 | I2C_NO_OPERATION = 0xff, | |
116 | I2C_WRITE = 0x00, | |
117 | I2C_READ = 0x01 | |
118 | }; | |
119 | ||
120 | /* controller response timeout in ms */ | |
121 | #define I2C_TIMEOUT_MS 500 | |
122 | ||
123 | /** | |
124 | * struct i2c_nmk_client - client specific data | |
125 | * @slave_adr: 7-bit slave address | |
126 | * @count: no. bytes to be transfered | |
127 | * @buffer: client data buffer | |
128 | * @xfer_bytes: bytes transfered till now | |
129 | * @operation: current I2C operation | |
130 | */ | |
131 | struct i2c_nmk_client { | |
132 | unsigned short slave_adr; | |
133 | unsigned long count; | |
134 | unsigned char *buffer; | |
135 | unsigned long xfer_bytes; | |
136 | enum i2c_operation operation; | |
137 | }; | |
138 | ||
139 | /** | |
140 | * struct nmk_i2c_dev - private data structure of the controller | |
141 | * @pdev: parent platform device | |
142 | * @adap: corresponding I2C adapter | |
143 | * @irq: interrupt line for the controller | |
144 | * @virtbase: virtual io memory area | |
145 | * @clk: hardware i2c block clock | |
146 | * @cfg: machine provided controller configuration | |
147 | * @cli: holder of client specific data | |
148 | * @stop: stop condition | |
149 | * @xfer_complete: acknowledge completion for a I2C message | |
150 | * @result: controller propogated result | |
151 | */ | |
152 | struct nmk_i2c_dev { | |
153 | struct platform_device *pdev; | |
154 | struct i2c_adapter adap; | |
155 | int irq; | |
156 | void __iomem *virtbase; | |
157 | struct clk *clk; | |
158 | struct nmk_i2c_controller cfg; | |
159 | struct i2c_nmk_client cli; | |
160 | int stop; | |
161 | struct completion xfer_complete; | |
162 | int result; | |
163 | }; | |
164 | ||
165 | /* controller's abort causes */ | |
166 | static const char *abort_causes[] = { | |
167 | "no ack received after address transmission", | |
168 | "no ack received during data phase", | |
169 | "ack received after xmission of master code", | |
170 | "master lost arbitration", | |
171 | "slave restarts", | |
172 | "slave reset", | |
173 | "overflow, maxsize is 2047 bytes", | |
174 | }; | |
175 | ||
176 | static inline void i2c_set_bit(void __iomem *reg, u32 mask) | |
177 | { | |
178 | writel(readl(reg) | mask, reg); | |
179 | } | |
180 | ||
181 | static inline void i2c_clr_bit(void __iomem *reg, u32 mask) | |
182 | { | |
183 | writel(readl(reg) & ~mask, reg); | |
184 | } | |
185 | ||
186 | /** | |
187 | * flush_i2c_fifo() - This function flushes the I2C FIFO | |
188 | * @dev: private data of I2C Driver | |
189 | * | |
190 | * This function flushes the I2C Tx and Rx FIFOs. It returns | |
191 | * 0 on successful flushing of FIFO | |
192 | */ | |
193 | static int flush_i2c_fifo(struct nmk_i2c_dev *dev) | |
194 | { | |
195 | #define LOOP_ATTEMPTS 10 | |
196 | int i; | |
197 | unsigned long timeout; | |
198 | ||
199 | /* | |
200 | * flush the transmit and receive FIFO. The flushing | |
201 | * operation takes several cycles before to be completed. | |
202 | * On the completion, the I2C internal logic clears these | |
203 | * bits, until then no one must access Tx, Rx FIFO and | |
204 | * should poll on these bits waiting for the completion. | |
205 | */ | |
206 | writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); | |
207 | ||
208 | for (i = 0; i < LOOP_ATTEMPTS; i++) { | |
209 | timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS); | |
210 | ||
211 | while (!time_after(jiffies, timeout)) { | |
212 | if ((readl(dev->virtbase + I2C_CR) & | |
213 | (I2C_CR_FTX | I2C_CR_FRX)) == 0) | |
214 | return 0; | |
215 | } | |
216 | } | |
217 | ||
218 | dev_err(&dev->pdev->dev, "flushing operation timed out " | |
219 | "giving up after %d attempts", LOOP_ATTEMPTS); | |
220 | ||
221 | return -ETIMEDOUT; | |
222 | } | |
223 | ||
224 | /** | |
225 | * disable_all_interrupts() - Disable all interrupts of this I2c Bus | |
226 | * @dev: private data of I2C Driver | |
227 | */ | |
228 | static void disable_all_interrupts(struct nmk_i2c_dev *dev) | |
229 | { | |
230 | u32 mask = IRQ_MASK(0); | |
231 | writel(mask, dev->virtbase + I2C_IMSCR); | |
232 | } | |
233 | ||
234 | /** | |
235 | * clear_all_interrupts() - Clear all interrupts of I2C Controller | |
236 | * @dev: private data of I2C Driver | |
237 | */ | |
238 | static void clear_all_interrupts(struct nmk_i2c_dev *dev) | |
239 | { | |
240 | u32 mask; | |
241 | mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); | |
242 | writel(mask, dev->virtbase + I2C_ICR); | |
243 | } | |
244 | ||
245 | /** | |
246 | * init_hw() - initialize the I2C hardware | |
247 | * @dev: private data of I2C Driver | |
248 | */ | |
249 | static int init_hw(struct nmk_i2c_dev *dev) | |
250 | { | |
251 | int stat; | |
252 | ||
253 | stat = flush_i2c_fifo(dev); | |
254 | if (stat) | |
255 | return stat; | |
256 | ||
257 | /* disable the controller */ | |
258 | i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
259 | ||
260 | disable_all_interrupts(dev); | |
261 | ||
262 | clear_all_interrupts(dev); | |
263 | ||
264 | dev->cli.operation = I2C_NO_OPERATION; | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | /* enable peripheral, master mode operation */ | |
270 | #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) | |
271 | ||
272 | /** | |
273 | * load_i2c_mcr_reg() - load the MCR register | |
274 | * @dev: private data of controller | |
275 | */ | |
276 | static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev) | |
277 | { | |
278 | u32 mcr = 0; | |
279 | ||
280 | /* 7-bit address transaction */ | |
281 | mcr |= GEN_MASK(1, I2C_MCR_AM, 12); | |
282 | mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); | |
283 | ||
284 | /* start byte procedure not applied */ | |
285 | mcr |= GEN_MASK(0, I2C_MCR_SB, 11); | |
286 | ||
287 | /* check the operation, master read/write? */ | |
288 | if (dev->cli.operation == I2C_WRITE) | |
289 | mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); | |
290 | else | |
291 | mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); | |
292 | ||
293 | /* stop or repeated start? */ | |
294 | if (dev->stop) | |
295 | mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); | |
296 | else | |
297 | mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); | |
298 | ||
299 | mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); | |
300 | ||
301 | return mcr; | |
302 | } | |
303 | ||
304 | /** | |
305 | * setup_i2c_controller() - setup the controller | |
306 | * @dev: private data of controller | |
307 | */ | |
308 | static void setup_i2c_controller(struct nmk_i2c_dev *dev) | |
309 | { | |
310 | u32 brcr1, brcr2; | |
311 | u32 i2c_clk, div; | |
312 | ||
313 | writel(0x0, dev->virtbase + I2C_CR); | |
314 | writel(0x0, dev->virtbase + I2C_HSMCR); | |
315 | writel(0x0, dev->virtbase + I2C_TFTR); | |
316 | writel(0x0, dev->virtbase + I2C_RFTR); | |
317 | writel(0x0, dev->virtbase + I2C_DMAR); | |
318 | ||
319 | /* | |
320 | * set the slsu: | |
321 | * | |
322 | * slsu defines the data setup time after SCL clock | |
323 | * stretching in terms of i2c clk cycles. The | |
324 | * needed setup time for the three modes are 250ns, | |
325 | * 100ns, 10ns repectively thus leading to the values | |
326 | * of 14, 6, 2 for a 48 MHz i2c clk. | |
327 | */ | |
328 | writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); | |
329 | ||
330 | i2c_clk = clk_get_rate(dev->clk); | |
331 | ||
332 | /* fallback to std. mode if machine has not provided it */ | |
333 | if (dev->cfg.clk_freq == 0) | |
334 | dev->cfg.clk_freq = 100000; | |
335 | ||
336 | /* | |
337 | * The spec says, in case of std. mode the divider is | |
338 | * 2 whereas it is 3 for fast and fastplus mode of | |
339 | * operation. TODO - high speed support. | |
340 | */ | |
341 | div = (dev->cfg.clk_freq > 100000) ? 3 : 2; | |
342 | ||
343 | /* | |
344 | * generate the mask for baud rate counters. The controller | |
345 | * has two baud rate counters. One is used for High speed | |
346 | * operation, and the other is for std, fast mode, fast mode | |
347 | * plus operation. Currently we do not supprt high speed mode | |
348 | * so set brcr1 to 0. | |
349 | */ | |
350 | brcr1 = 0 << 16; | |
351 | brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; | |
352 | ||
353 | /* set the baud rate counter register */ | |
354 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
355 | ||
356 | /* | |
357 | * set the speed mode. Currently we support | |
358 | * only standard and fast mode of operation | |
359 | * TODO - support for fast mode plus (upto 1Mb/s) | |
360 | * and high speed (up to 3.4 Mb/s) | |
361 | */ | |
362 | if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { | |
363 | dev_err(&dev->pdev->dev, "do not support this mode " | |
364 | "defaulting to std. mode\n"); | |
365 | brcr2 = i2c_clk/(100000 * 2) & 0xffff; | |
366 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
367 | writel(I2C_FREQ_MODE_STANDARD << 4, | |
368 | dev->virtbase + I2C_CR); | |
369 | } | |
370 | writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); | |
371 | ||
372 | /* set the Tx and Rx FIFO threshold */ | |
373 | writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); | |
374 | writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); | |
375 | } | |
376 | ||
377 | /** | |
378 | * read_i2c() - Read from I2C client device | |
379 | * @dev: private data of I2C Driver | |
380 | * | |
381 | * This function reads from i2c client device when controller is in | |
382 | * master mode. There is a completion timeout. If there is no transfer | |
383 | * before timeout error is returned. | |
384 | */ | |
385 | static int read_i2c(struct nmk_i2c_dev *dev) | |
386 | { | |
387 | u32 status = 0; | |
388 | u32 mcr; | |
389 | u32 irq_mask = 0; | |
390 | int timeout; | |
391 | ||
392 | mcr = load_i2c_mcr_reg(dev); | |
393 | writel(mcr, dev->virtbase + I2C_MCR); | |
394 | ||
395 | /* load the current CR value */ | |
396 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
397 | dev->virtbase + I2C_CR); | |
398 | ||
399 | /* enable the controller */ | |
400 | i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
401 | ||
402 | init_completion(&dev->xfer_complete); | |
403 | ||
404 | /* enable interrupts by setting the mask */ | |
405 | irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | | |
406 | I2C_IT_MAL | I2C_IT_BERR); | |
407 | ||
408 | if (dev->stop) | |
409 | irq_mask |= I2C_IT_MTD; | |
410 | else | |
411 | irq_mask |= I2C_IT_MTDWS; | |
412 | ||
413 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
414 | ||
415 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
416 | dev->virtbase + I2C_IMSCR); | |
417 | ||
418 | timeout = wait_for_completion_interruptible_timeout( | |
419 | &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); | |
420 | ||
421 | if (timeout < 0) { | |
422 | dev_err(&dev->pdev->dev, | |
423 | "wait_for_completion_interruptible_timeout" | |
424 | "returned %d waiting for event\n", timeout); | |
425 | status = timeout; | |
426 | } | |
427 | ||
428 | if (timeout == 0) { | |
429 | /* controler has timedout, re-init the h/w */ | |
430 | dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); | |
431 | (void) init_hw(dev); | |
432 | status = -ETIMEDOUT; | |
433 | } | |
3f9900f1 | 434 | return status; |
435 | } | |
436 | ||
437 | /** | |
438 | * write_i2c() - Write data to I2C client. | |
439 | * @dev: private data of I2C Driver | |
440 | * | |
441 | * This function writes data to I2C client | |
442 | */ | |
443 | static int write_i2c(struct nmk_i2c_dev *dev) | |
444 | { | |
445 | u32 status = 0; | |
446 | u32 mcr; | |
447 | u32 irq_mask = 0; | |
448 | int timeout; | |
449 | ||
450 | mcr = load_i2c_mcr_reg(dev); | |
451 | ||
452 | writel(mcr, dev->virtbase + I2C_MCR); | |
453 | ||
454 | /* load the current CR value */ | |
455 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
456 | dev->virtbase + I2C_CR); | |
457 | ||
458 | /* enable the controller */ | |
459 | i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
460 | ||
461 | init_completion(&dev->xfer_complete); | |
462 | ||
463 | /* enable interrupts by settings the masks */ | |
464 | irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR | | |
465 | I2C_IT_MAL | I2C_IT_BERR); | |
466 | ||
467 | /* | |
468 | * check if we want to transfer a single or multiple bytes, if so | |
469 | * set the MTDWS bit (Master Transaction Done Without Stop) | |
470 | * to start repeated start operation | |
471 | */ | |
472 | if (dev->stop) | |
473 | irq_mask |= I2C_IT_MTD; | |
474 | else | |
475 | irq_mask |= I2C_IT_MTDWS; | |
476 | ||
477 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
478 | ||
479 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
480 | dev->virtbase + I2C_IMSCR); | |
481 | ||
482 | timeout = wait_for_completion_interruptible_timeout( | |
483 | &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); | |
484 | ||
485 | if (timeout < 0) { | |
486 | dev_err(&dev->pdev->dev, | |
487 | "wait_for_completion_interruptible_timeout" | |
488 | "returned %d waiting for event\n", timeout); | |
489 | status = timeout; | |
490 | } | |
491 | ||
492 | if (timeout == 0) { | |
493 | /* controler has timedout, re-init the h/w */ | |
494 | dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); | |
495 | (void) init_hw(dev); | |
496 | status = -ETIMEDOUT; | |
497 | } | |
498 | ||
499 | return status; | |
500 | } | |
501 | ||
502 | /** | |
503 | * nmk_i2c_xfer() - I2C transfer function used by kernel framework | |
1804edd1 LW |
504 | * @i2c_adap: Adapter pointer to the controller |
505 | * @msgs: Pointer to data to be written. | |
506 | * @num_msgs: Number of messages to be executed | |
3f9900f1 | 507 | * |
508 | * This is the function called by the generic kernel i2c_transfer() | |
509 | * or i2c_smbus...() API calls. Note that this code is protected by the | |
510 | * semaphore set in the kernel i2c_transfer() function. | |
511 | * | |
512 | * NOTE: | |
513 | * READ TRANSFER : We impose a restriction of the first message to be the | |
514 | * index message for any read transaction. | |
515 | * - a no index is coded as '0', | |
516 | * - 2byte big endian index is coded as '3' | |
517 | * !!! msg[0].buf holds the actual index. | |
518 | * This is compatible with generic messages of smbus emulator | |
519 | * that send a one byte index. | |
520 | * eg. a I2C transation to read 2 bytes from index 0 | |
521 | * idx = 0; | |
522 | * msg[0].addr = client->addr; | |
523 | * msg[0].flags = 0x0; | |
524 | * msg[0].len = 1; | |
525 | * msg[0].buf = &idx; | |
526 | * | |
527 | * msg[1].addr = client->addr; | |
528 | * msg[1].flags = I2C_M_RD; | |
529 | * msg[1].len = 2; | |
530 | * msg[1].buf = rd_buff | |
531 | * i2c_transfer(adap, msg, 2); | |
532 | * | |
533 | * WRITE TRANSFER : The I2C standard interface interprets all data as payload. | |
534 | * If you want to emulate an SMBUS write transaction put the | |
535 | * index as first byte(or first and second) in the payload. | |
536 | * eg. a I2C transation to write 2 bytes from index 1 | |
537 | * wr_buff[0] = 0x1; | |
538 | * wr_buff[1] = 0x23; | |
539 | * wr_buff[2] = 0x46; | |
540 | * msg[0].flags = 0x0; | |
541 | * msg[0].len = 3; | |
542 | * msg[0].buf = wr_buff; | |
543 | * i2c_transfer(adap, msg, 1); | |
544 | * | |
545 | * To read or write a block of data (multiple bytes) using SMBUS emulation | |
546 | * please use the i2c_smbus_read_i2c_block_data() | |
547 | * or i2c_smbus_write_i2c_block_data() API | |
548 | */ | |
549 | static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, | |
550 | struct i2c_msg msgs[], int num_msgs) | |
551 | { | |
552 | int status; | |
553 | int i; | |
554 | u32 cause; | |
555 | struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); | |
556 | ||
557 | status = init_hw(dev); | |
558 | if (status) | |
559 | return status; | |
560 | ||
561 | /* setup the i2c controller */ | |
562 | setup_i2c_controller(dev); | |
563 | ||
564 | for (i = 0; i < num_msgs; i++) { | |
565 | if (unlikely(msgs[i].flags & I2C_M_TEN)) { | |
566 | dev_err(&dev->pdev->dev, "10 bit addressing" | |
567 | "not supported\n"); | |
568 | return -EINVAL; | |
569 | } | |
570 | dev->cli.slave_adr = msgs[i].addr; | |
571 | dev->cli.buffer = msgs[i].buf; | |
572 | dev->cli.count = msgs[i].len; | |
573 | dev->stop = (i < (num_msgs - 1)) ? 0 : 1; | |
574 | dev->result = 0; | |
575 | ||
576 | if (msgs[i].flags & I2C_M_RD) { | |
577 | /* it is a read operation */ | |
578 | dev->cli.operation = I2C_READ; | |
579 | status = read_i2c(dev); | |
580 | } else { | |
581 | /* write operation */ | |
582 | dev->cli.operation = I2C_WRITE; | |
583 | status = write_i2c(dev); | |
584 | } | |
585 | if (status || (dev->result)) { | |
586 | /* get the abort cause */ | |
587 | cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7; | |
588 | dev_err(&dev->pdev->dev, "error during I2C" | |
589 | "message xfer: %d\n", cause); | |
590 | dev_err(&dev->pdev->dev, "%s\n", | |
591 | cause >= ARRAY_SIZE(abort_causes) | |
592 | ? "unknown reason" : abort_causes[cause]); | |
593 | return status; | |
594 | } | |
595 | mdelay(1); | |
596 | } | |
597 | /* return the no. messages processed */ | |
598 | if (status) | |
599 | return status; | |
600 | else | |
601 | return num_msgs; | |
602 | } | |
603 | ||
604 | /** | |
605 | * disable_interrupts() - disable the interrupts | |
606 | * @dev: private data of controller | |
1804edd1 | 607 | * @irq: interrupt number |
3f9900f1 | 608 | */ |
609 | static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) | |
610 | { | |
611 | irq = IRQ_MASK(irq); | |
612 | writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), | |
613 | dev->virtbase + I2C_IMSCR); | |
614 | return 0; | |
615 | } | |
616 | ||
617 | /** | |
618 | * i2c_irq_handler() - interrupt routine | |
619 | * @irq: interrupt number | |
620 | * @arg: data passed to the handler | |
621 | * | |
622 | * This is the interrupt handler for the i2c driver. Currently | |
623 | * it handles the major interrupts like Rx & Tx FIFO management | |
624 | * interrupts, master transaction interrupts, arbitration and | |
625 | * bus error interrupts. The rest of the interrupts are treated as | |
626 | * unhandled. | |
627 | */ | |
628 | static irqreturn_t i2c_irq_handler(int irq, void *arg) | |
629 | { | |
630 | struct nmk_i2c_dev *dev = arg; | |
631 | u32 tft, rft; | |
632 | u32 count; | |
633 | u32 misr; | |
634 | u32 src = 0; | |
635 | ||
636 | /* load Tx FIFO and Rx FIFO threshold values */ | |
637 | tft = readl(dev->virtbase + I2C_TFTR); | |
638 | rft = readl(dev->virtbase + I2C_RFTR); | |
639 | ||
640 | /* read interrupt status register */ | |
641 | misr = readl(dev->virtbase + I2C_MISR); | |
642 | ||
643 | src = __ffs(misr); | |
644 | switch ((1 << src)) { | |
645 | ||
646 | /* Transmit FIFO nearly empty interrupt */ | |
647 | case I2C_IT_TXFNE: | |
648 | { | |
649 | if (dev->cli.operation == I2C_READ) { | |
650 | /* | |
651 | * in read operation why do we care for writing? | |
652 | * so disable the Transmit FIFO interrupt | |
653 | */ | |
654 | disable_interrupts(dev, I2C_IT_TXFNE); | |
655 | } else { | |
656 | for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2); | |
657 | (count > 0) && | |
658 | (dev->cli.count != 0); | |
659 | count--) { | |
660 | /* write to the Tx FIFO */ | |
661 | writeb(*dev->cli.buffer, | |
662 | dev->virtbase + I2C_TFR); | |
663 | dev->cli.buffer++; | |
664 | dev->cli.count--; | |
665 | dev->cli.xfer_bytes++; | |
666 | } | |
667 | /* | |
668 | * if done, close the transfer by disabling the | |
669 | * corresponding TXFNE interrupt | |
670 | */ | |
671 | if (dev->cli.count == 0) | |
672 | disable_interrupts(dev, I2C_IT_TXFNE); | |
673 | } | |
674 | } | |
675 | break; | |
676 | ||
677 | /* | |
678 | * Rx FIFO nearly full interrupt. | |
679 | * This is set when the numer of entries in Rx FIFO is | |
680 | * greater or equal than the threshold value programmed | |
681 | * in RFT | |
682 | */ | |
683 | case I2C_IT_RXFNF: | |
684 | for (count = rft; count > 0; count--) { | |
685 | /* Read the Rx FIFO */ | |
686 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
687 | dev->cli.buffer++; | |
688 | } | |
689 | dev->cli.count -= rft; | |
690 | dev->cli.xfer_bytes += rft; | |
691 | break; | |
692 | ||
693 | /* Rx FIFO full */ | |
694 | case I2C_IT_RXFF: | |
695 | for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { | |
696 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
697 | dev->cli.buffer++; | |
698 | } | |
699 | dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; | |
700 | dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; | |
701 | break; | |
702 | ||
703 | /* Master Transaction Done with/without stop */ | |
704 | case I2C_IT_MTD: | |
705 | case I2C_IT_MTDWS: | |
706 | if (dev->cli.operation == I2C_READ) { | |
1df3ab1b RV |
707 | while (!(readl(dev->virtbase + I2C_RISR) |
708 | & I2C_IT_RXFE)) { | |
3f9900f1 | 709 | if (dev->cli.count == 0) |
710 | break; | |
711 | *dev->cli.buffer = | |
712 | readb(dev->virtbase + I2C_RFR); | |
713 | dev->cli.buffer++; | |
714 | dev->cli.count--; | |
715 | dev->cli.xfer_bytes++; | |
716 | } | |
717 | } | |
718 | ||
719 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD); | |
720 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS); | |
721 | ||
722 | disable_interrupts(dev, | |
723 | (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF | |
724 | | I2C_IT_TXFOVR | I2C_IT_RXFNF | |
725 | | I2C_IT_RXFF | I2C_IT_RXFE)); | |
726 | ||
727 | if (dev->cli.count) { | |
728 | dev->result = -1; | |
729 | dev_err(&dev->pdev->dev, "%lu bytes still remain to be" | |
730 | "xfered\n", dev->cli.count); | |
731 | (void) init_hw(dev); | |
732 | } | |
733 | complete(&dev->xfer_complete); | |
734 | ||
735 | break; | |
736 | ||
737 | /* Master Arbitration lost interrupt */ | |
738 | case I2C_IT_MAL: | |
739 | dev->result = -1; | |
740 | (void) init_hw(dev); | |
741 | ||
742 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); | |
743 | complete(&dev->xfer_complete); | |
744 | ||
745 | break; | |
746 | ||
747 | /* | |
748 | * Bus Error interrupt. | |
749 | * This happens when an unexpected start/stop condition occurs | |
750 | * during the transaction. | |
751 | */ | |
752 | case I2C_IT_BERR: | |
753 | dev->result = -1; | |
754 | /* get the status */ | |
755 | if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) | |
756 | (void) init_hw(dev); | |
757 | ||
758 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); | |
759 | complete(&dev->xfer_complete); | |
760 | ||
761 | break; | |
762 | ||
763 | /* | |
764 | * Tx FIFO overrun interrupt. | |
765 | * This is set when a write operation in Tx FIFO is performed and | |
766 | * the Tx FIFO is full. | |
767 | */ | |
768 | case I2C_IT_TXFOVR: | |
769 | dev->result = -1; | |
770 | (void) init_hw(dev); | |
771 | ||
772 | dev_err(&dev->pdev->dev, "Tx Fifo Over run\n"); | |
773 | complete(&dev->xfer_complete); | |
774 | ||
775 | break; | |
776 | ||
777 | /* unhandled interrupts by this driver - TODO*/ | |
778 | case I2C_IT_TXFE: | |
779 | case I2C_IT_TXFF: | |
780 | case I2C_IT_RXFE: | |
781 | case I2C_IT_RFSR: | |
782 | case I2C_IT_RFSE: | |
783 | case I2C_IT_WTSR: | |
784 | case I2C_IT_STD: | |
785 | dev_err(&dev->pdev->dev, "unhandled Interrupt\n"); | |
786 | break; | |
787 | default: | |
788 | dev_err(&dev->pdev->dev, "spurious Interrupt..\n"); | |
789 | break; | |
790 | } | |
791 | ||
792 | return IRQ_HANDLED; | |
793 | } | |
794 | ||
795 | static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) | |
796 | { | |
797 | return I2C_FUNC_I2C | |
798 | | I2C_FUNC_SMBUS_BYTE_DATA | |
799 | | I2C_FUNC_SMBUS_WORD_DATA | |
800 | | I2C_FUNC_SMBUS_I2C_BLOCK; | |
801 | } | |
802 | ||
803 | static const struct i2c_algorithm nmk_i2c_algo = { | |
804 | .master_xfer = nmk_i2c_xfer, | |
805 | .functionality = nmk_i2c_functionality | |
806 | }; | |
807 | ||
808 | static int __devinit nmk_i2c_probe(struct platform_device *pdev) | |
809 | { | |
810 | int ret = 0; | |
811 | struct resource *res; | |
812 | struct nmk_i2c_controller *pdata = | |
813 | pdev->dev.platform_data; | |
814 | struct nmk_i2c_dev *dev; | |
815 | struct i2c_adapter *adap; | |
816 | ||
817 | dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); | |
818 | if (!dev) { | |
819 | dev_err(&pdev->dev, "cannot allocate memory\n"); | |
820 | ret = -ENOMEM; | |
821 | goto err_no_mem; | |
822 | } | |
823 | ||
824 | dev->pdev = pdev; | |
825 | platform_set_drvdata(pdev, dev); | |
826 | ||
827 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
828 | if (!res) { | |
829 | ret = -ENOENT; | |
830 | goto err_no_resource; | |
831 | } | |
832 | ||
833 | if (request_mem_region(res->start, resource_size(res), | |
834 | DRIVER_NAME "I/O region") == NULL) { | |
835 | ret = -EBUSY; | |
836 | goto err_no_region; | |
837 | } | |
838 | ||
839 | dev->virtbase = ioremap(res->start, resource_size(res)); | |
840 | if (!dev->virtbase) { | |
841 | ret = -ENOMEM; | |
842 | goto err_no_ioremap; | |
843 | } | |
844 | ||
845 | dev->irq = platform_get_irq(pdev, 0); | |
846 | ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED, | |
847 | DRIVER_NAME, dev); | |
848 | if (ret) { | |
849 | dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq); | |
850 | goto err_irq; | |
851 | } | |
852 | ||
853 | dev->clk = clk_get(&pdev->dev, NULL); | |
854 | if (IS_ERR(dev->clk)) { | |
855 | dev_err(&pdev->dev, "could not get i2c clock\n"); | |
856 | ret = PTR_ERR(dev->clk); | |
857 | goto err_no_clk; | |
858 | } | |
859 | ||
860 | clk_enable(dev->clk); | |
861 | ||
862 | adap = &dev->adap; | |
863 | adap->dev.parent = &pdev->dev; | |
864 | adap->owner = THIS_MODULE; | |
865 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
866 | adap->algo = &nmk_i2c_algo; | |
867 | ||
868 | /* fetch the controller id */ | |
869 | adap->nr = pdev->id; | |
870 | ||
871 | /* fetch the controller configuration from machine */ | |
872 | dev->cfg.clk_freq = pdata->clk_freq; | |
873 | dev->cfg.slsu = pdata->slsu; | |
874 | dev->cfg.tft = pdata->tft; | |
875 | dev->cfg.rft = pdata->rft; | |
876 | dev->cfg.sm = pdata->sm; | |
877 | ||
878 | i2c_set_adapdata(adap, dev); | |
879 | ||
880 | ret = init_hw(dev); | |
881 | if (ret != 0) { | |
882 | dev_err(&pdev->dev, "error in initializing i2c hardware\n"); | |
883 | goto err_init_hw; | |
884 | } | |
885 | ||
886 | dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual " | |
887 | "base %p\n", pdev->id, dev->virtbase); | |
888 | ||
889 | ret = i2c_add_numbered_adapter(adap); | |
890 | if (ret) { | |
891 | dev_err(&pdev->dev, "failed to add adapter\n"); | |
892 | goto err_add_adap; | |
893 | } | |
894 | ||
895 | return 0; | |
896 | ||
897 | err_init_hw: | |
898 | clk_disable(dev->clk); | |
899 | err_add_adap: | |
900 | clk_put(dev->clk); | |
901 | err_no_clk: | |
902 | free_irq(dev->irq, dev); | |
903 | err_irq: | |
904 | iounmap(dev->virtbase); | |
905 | err_no_ioremap: | |
906 | release_mem_region(res->start, resource_size(res)); | |
907 | err_no_region: | |
908 | platform_set_drvdata(pdev, NULL); | |
909 | err_no_resource: | |
910 | kfree(dev); | |
911 | err_no_mem: | |
912 | ||
913 | return ret; | |
914 | } | |
915 | ||
916 | static int __devexit nmk_i2c_remove(struct platform_device *pdev) | |
917 | { | |
a1c27678 | 918 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
3f9900f1 | 919 | struct nmk_i2c_dev *dev = platform_get_drvdata(pdev); |
920 | ||
921 | i2c_del_adapter(&dev->adap); | |
922 | flush_i2c_fifo(dev); | |
923 | disable_all_interrupts(dev); | |
924 | clear_all_interrupts(dev); | |
925 | /* disable the controller */ | |
926 | i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
927 | free_irq(dev->irq, dev); | |
928 | iounmap(dev->virtbase); | |
a1c27678 RV |
929 | if (res) |
930 | release_mem_region(res->start, resource_size(res)); | |
3f9900f1 | 931 | clk_disable(dev->clk); |
932 | clk_put(dev->clk); | |
933 | platform_set_drvdata(pdev, NULL); | |
934 | kfree(dev); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static struct platform_driver nmk_i2c_driver = { | |
940 | .driver = { | |
941 | .owner = THIS_MODULE, | |
942 | .name = DRIVER_NAME, | |
943 | }, | |
944 | .probe = nmk_i2c_probe, | |
945 | .remove = __devexit_p(nmk_i2c_remove), | |
946 | }; | |
947 | ||
948 | static int __init nmk_i2c_init(void) | |
949 | { | |
950 | return platform_driver_register(&nmk_i2c_driver); | |
951 | } | |
952 | ||
953 | static void __exit nmk_i2c_exit(void) | |
954 | { | |
955 | platform_driver_unregister(&nmk_i2c_driver); | |
956 | } | |
957 | ||
958 | subsys_initcall(nmk_i2c_init); | |
959 | module_exit(nmk_i2c_exit); | |
960 | ||
961 | MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); | |
962 | MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); | |
963 | MODULE_LICENSE("GPL"); | |
964 | MODULE_ALIAS("platform:" DRIVER_NAME); |