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3f9900f1 | 1 | /* |
1804edd1 | 2 | * Copyright (C) 2009 ST-Ericsson SA |
3f9900f1 | 3 | * Copyright (C) 2009 STMicroelectronics |
4 | * | |
5 | * I2C master mode controller driver, used in Nomadik 8815 | |
6 | * and Ux500 platforms. | |
7 | * | |
8 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
9 | * Author: Sachin Verma <sachin.verma@st.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2, as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
23560214 AR |
17 | #include <linux/amba/bus.h> |
18 | #include <linux/atomic.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
3f9900f1 | 20 | #include <linux/interrupt.h> |
21 | #include <linux/i2c.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/io.h> | |
b0e751a9 | 25 | #include <linux/pm_runtime.h> |
af97bace | 26 | #include <linux/platform_data/i2c-nomadik.h> |
43fea581 LJ |
27 | #include <linux/of.h> |
28 | #include <linux/of_i2c.h> | |
24e9e157 | 29 | #include <linux/pinctrl/consumer.h> |
3f9900f1 | 30 | |
31 | #define DRIVER_NAME "nmk-i2c" | |
32 | ||
33 | /* I2C Controller register offsets */ | |
34 | #define I2C_CR (0x000) | |
35 | #define I2C_SCR (0x004) | |
36 | #define I2C_HSMCR (0x008) | |
37 | #define I2C_MCR (0x00C) | |
38 | #define I2C_TFR (0x010) | |
39 | #define I2C_SR (0x014) | |
40 | #define I2C_RFR (0x018) | |
41 | #define I2C_TFTR (0x01C) | |
42 | #define I2C_RFTR (0x020) | |
43 | #define I2C_DMAR (0x024) | |
44 | #define I2C_BRCR (0x028) | |
45 | #define I2C_IMSCR (0x02C) | |
46 | #define I2C_RISR (0x030) | |
47 | #define I2C_MISR (0x034) | |
48 | #define I2C_ICR (0x038) | |
49 | ||
50 | /* Control registers */ | |
51 | #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ | |
52 | #define I2C_CR_OM (0x3 << 1) /* Operating mode */ | |
53 | #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ | |
54 | #define I2C_CR_SM (0x3 << 4) /* Speed mode */ | |
55 | #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ | |
56 | #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ | |
57 | #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ | |
58 | #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ | |
59 | #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ | |
60 | #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ | |
61 | #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ | |
62 | #define I2C_CR_FON (0x3 << 13) /* Filtering on */ | |
63 | #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ | |
64 | ||
65 | /* Master controller (MCR) register */ | |
66 | #define I2C_MCR_OP (0x1 << 0) /* Operation */ | |
67 | #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ | |
8abf6fbb | 68 | #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ |
3f9900f1 | 69 | #define I2C_MCR_SB (0x1 << 11) /* Extended address */ |
70 | #define I2C_MCR_AM (0x3 << 12) /* Address type */ | |
8abf6fbb JA |
71 | #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ |
72 | #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ | |
3f9900f1 | 73 | |
74 | /* Status register (SR) */ | |
75 | #define I2C_SR_OP (0x3 << 0) /* Operation */ | |
76 | #define I2C_SR_STATUS (0x3 << 2) /* controller status */ | |
77 | #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ | |
78 | #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ | |
79 | #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ | |
80 | ||
81 | /* Interrupt mask set/clear (IMSCR) bits */ | |
8abf6fbb | 82 | #define I2C_IT_TXFE (0x1 << 0) |
3f9900f1 | 83 | #define I2C_IT_TXFNE (0x1 << 1) |
84 | #define I2C_IT_TXFF (0x1 << 2) | |
85 | #define I2C_IT_TXFOVR (0x1 << 3) | |
86 | #define I2C_IT_RXFE (0x1 << 4) | |
87 | #define I2C_IT_RXFNF (0x1 << 5) | |
88 | #define I2C_IT_RXFF (0x1 << 6) | |
89 | #define I2C_IT_RFSR (0x1 << 16) | |
90 | #define I2C_IT_RFSE (0x1 << 17) | |
91 | #define I2C_IT_WTSR (0x1 << 18) | |
92 | #define I2C_IT_MTD (0x1 << 19) | |
93 | #define I2C_IT_STD (0x1 << 20) | |
94 | #define I2C_IT_MAL (0x1 << 24) | |
95 | #define I2C_IT_BERR (0x1 << 25) | |
96 | #define I2C_IT_MTDWS (0x1 << 28) | |
97 | ||
98 | #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) | |
99 | ||
100 | /* some bits in ICR are reserved */ | |
101 | #define I2C_CLEAR_ALL_INTS 0x131f007f | |
102 | ||
103 | /* first three msb bits are reserved */ | |
104 | #define IRQ_MASK(mask) (mask & 0x1fffffff) | |
105 | ||
106 | /* maximum threshold value */ | |
107 | #define MAX_I2C_FIFO_THRESHOLD 15 | |
108 | ||
3a205be5 LW |
109 | /** |
110 | * struct i2c_vendor_data - per-vendor variations | |
111 | * @has_mtdws: variant has the MTDWS bit | |
112 | * @fifodepth: variant FIFO depth | |
113 | */ | |
114 | struct i2c_vendor_data { | |
115 | bool has_mtdws; | |
116 | u32 fifodepth; | |
117 | }; | |
118 | ||
3f9900f1 | 119 | enum i2c_status { |
120 | I2C_NOP, | |
121 | I2C_ON_GOING, | |
122 | I2C_OK, | |
123 | I2C_ABORT | |
124 | }; | |
125 | ||
126 | /* operation */ | |
127 | enum i2c_operation { | |
128 | I2C_NO_OPERATION = 0xff, | |
129 | I2C_WRITE = 0x00, | |
130 | I2C_READ = 0x01 | |
131 | }; | |
132 | ||
3f9900f1 | 133 | /** |
134 | * struct i2c_nmk_client - client specific data | |
135 | * @slave_adr: 7-bit slave address | |
25985edc | 136 | * @count: no. bytes to be transferred |
3f9900f1 | 137 | * @buffer: client data buffer |
25985edc | 138 | * @xfer_bytes: bytes transferred till now |
3f9900f1 | 139 | * @operation: current I2C operation |
140 | */ | |
141 | struct i2c_nmk_client { | |
142 | unsigned short slave_adr; | |
143 | unsigned long count; | |
144 | unsigned char *buffer; | |
145 | unsigned long xfer_bytes; | |
146 | enum i2c_operation operation; | |
147 | }; | |
148 | ||
149 | /** | |
8abf6fbb | 150 | * struct nmk_i2c_dev - private data structure of the controller. |
3a205be5 | 151 | * @vendor: vendor data for this variant. |
23560214 | 152 | * @adev: parent amba device. |
8abf6fbb JA |
153 | * @adap: corresponding I2C adapter. |
154 | * @irq: interrupt line for the controller. | |
155 | * @virtbase: virtual io memory area. | |
156 | * @clk: hardware i2c block clock. | |
157 | * @cfg: machine provided controller configuration. | |
158 | * @cli: holder of client specific data. | |
159 | * @stop: stop condition. | |
160 | * @xfer_complete: acknowledge completion for a I2C message. | |
161 | * @result: controller propogated result. | |
24e9e157 PC |
162 | * @pinctrl: pinctrl handle. |
163 | * @pins_default: default state for the pins. | |
164 | * @pins_idle: idle state for the pins. | |
165 | * @pins_sleep: sleep state for the pins. | |
8abf6fbb | 166 | * @busy: Busy doing transfer. |
3f9900f1 | 167 | */ |
168 | struct nmk_i2c_dev { | |
3a205be5 | 169 | struct i2c_vendor_data *vendor; |
23560214 | 170 | struct amba_device *adev; |
8abf6fbb JA |
171 | struct i2c_adapter adap; |
172 | int irq; | |
3f9900f1 | 173 | void __iomem *virtbase; |
174 | struct clk *clk; | |
175 | struct nmk_i2c_controller cfg; | |
176 | struct i2c_nmk_client cli; | |
8abf6fbb | 177 | int stop; |
3f9900f1 | 178 | struct completion xfer_complete; |
8abf6fbb | 179 | int result; |
24e9e157 PC |
180 | /* Three pin states - default, idle & sleep */ |
181 | struct pinctrl *pinctrl; | |
182 | struct pinctrl_state *pins_default; | |
183 | struct pinctrl_state *pins_idle; | |
184 | struct pinctrl_state *pins_sleep; | |
a20d2394 | 185 | bool busy; |
3f9900f1 | 186 | }; |
187 | ||
188 | /* controller's abort causes */ | |
189 | static const char *abort_causes[] = { | |
190 | "no ack received after address transmission", | |
191 | "no ack received during data phase", | |
192 | "ack received after xmission of master code", | |
193 | "master lost arbitration", | |
194 | "slave restarts", | |
195 | "slave reset", | |
196 | "overflow, maxsize is 2047 bytes", | |
197 | }; | |
198 | ||
199 | static inline void i2c_set_bit(void __iomem *reg, u32 mask) | |
200 | { | |
201 | writel(readl(reg) | mask, reg); | |
202 | } | |
203 | ||
204 | static inline void i2c_clr_bit(void __iomem *reg, u32 mask) | |
205 | { | |
206 | writel(readl(reg) & ~mask, reg); | |
207 | } | |
208 | ||
209 | /** | |
210 | * flush_i2c_fifo() - This function flushes the I2C FIFO | |
211 | * @dev: private data of I2C Driver | |
212 | * | |
213 | * This function flushes the I2C Tx and Rx FIFOs. It returns | |
214 | * 0 on successful flushing of FIFO | |
215 | */ | |
216 | static int flush_i2c_fifo(struct nmk_i2c_dev *dev) | |
217 | { | |
218 | #define LOOP_ATTEMPTS 10 | |
219 | int i; | |
220 | unsigned long timeout; | |
221 | ||
222 | /* | |
223 | * flush the transmit and receive FIFO. The flushing | |
224 | * operation takes several cycles before to be completed. | |
225 | * On the completion, the I2C internal logic clears these | |
226 | * bits, until then no one must access Tx, Rx FIFO and | |
227 | * should poll on these bits waiting for the completion. | |
228 | */ | |
229 | writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); | |
230 | ||
231 | for (i = 0; i < LOOP_ATTEMPTS; i++) { | |
cd20e4fa | 232 | timeout = jiffies + dev->adap.timeout; |
3f9900f1 | 233 | |
234 | while (!time_after(jiffies, timeout)) { | |
235 | if ((readl(dev->virtbase + I2C_CR) & | |
236 | (I2C_CR_FTX | I2C_CR_FRX)) == 0) | |
237 | return 0; | |
238 | } | |
239 | } | |
240 | ||
23560214 | 241 | dev_err(&dev->adev->dev, |
8abf6fbb JA |
242 | "flushing operation timed out giving up after %d attempts", |
243 | LOOP_ATTEMPTS); | |
3f9900f1 | 244 | |
245 | return -ETIMEDOUT; | |
246 | } | |
247 | ||
248 | /** | |
249 | * disable_all_interrupts() - Disable all interrupts of this I2c Bus | |
250 | * @dev: private data of I2C Driver | |
251 | */ | |
252 | static void disable_all_interrupts(struct nmk_i2c_dev *dev) | |
253 | { | |
254 | u32 mask = IRQ_MASK(0); | |
255 | writel(mask, dev->virtbase + I2C_IMSCR); | |
256 | } | |
257 | ||
258 | /** | |
259 | * clear_all_interrupts() - Clear all interrupts of I2C Controller | |
260 | * @dev: private data of I2C Driver | |
261 | */ | |
262 | static void clear_all_interrupts(struct nmk_i2c_dev *dev) | |
263 | { | |
264 | u32 mask; | |
265 | mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); | |
266 | writel(mask, dev->virtbase + I2C_ICR); | |
267 | } | |
268 | ||
269 | /** | |
270 | * init_hw() - initialize the I2C hardware | |
271 | * @dev: private data of I2C Driver | |
272 | */ | |
273 | static int init_hw(struct nmk_i2c_dev *dev) | |
274 | { | |
275 | int stat; | |
276 | ||
277 | stat = flush_i2c_fifo(dev); | |
278 | if (stat) | |
a20d2394 | 279 | goto exit; |
3f9900f1 | 280 | |
281 | /* disable the controller */ | |
282 | i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
283 | ||
284 | disable_all_interrupts(dev); | |
285 | ||
286 | clear_all_interrupts(dev); | |
287 | ||
288 | dev->cli.operation = I2C_NO_OPERATION; | |
289 | ||
a20d2394 | 290 | exit: |
a20d2394 | 291 | return stat; |
3f9900f1 | 292 | } |
293 | ||
294 | /* enable peripheral, master mode operation */ | |
8abf6fbb | 295 | #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) |
3f9900f1 | 296 | |
297 | /** | |
298 | * load_i2c_mcr_reg() - load the MCR register | |
299 | * @dev: private data of controller | |
51a0c8d0 | 300 | * @flags: message flags |
3f9900f1 | 301 | */ |
51a0c8d0 | 302 | static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 303 | { |
304 | u32 mcr = 0; | |
51a0c8d0 | 305 | unsigned short slave_adr_3msb_bits; |
3f9900f1 | 306 | |
3f9900f1 | 307 | mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); |
308 | ||
51a0c8d0 VS |
309 | if (unlikely(flags & I2C_M_TEN)) { |
310 | /* 10-bit address transaction */ | |
311 | mcr |= GEN_MASK(2, I2C_MCR_AM, 12); | |
312 | /* | |
313 | * Get the top 3 bits. | |
314 | * EA10 represents extended address in MCR. This includes | |
315 | * the extension (MSB bits) of the 7 bit address loaded | |
316 | * in A7 | |
317 | */ | |
318 | slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; | |
319 | ||
320 | mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); | |
321 | } else { | |
322 | /* 7-bit address transaction */ | |
323 | mcr |= GEN_MASK(1, I2C_MCR_AM, 12); | |
324 | } | |
325 | ||
3f9900f1 | 326 | /* start byte procedure not applied */ |
327 | mcr |= GEN_MASK(0, I2C_MCR_SB, 11); | |
328 | ||
329 | /* check the operation, master read/write? */ | |
330 | if (dev->cli.operation == I2C_WRITE) | |
331 | mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); | |
332 | else | |
333 | mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); | |
334 | ||
335 | /* stop or repeated start? */ | |
336 | if (dev->stop) | |
337 | mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); | |
338 | else | |
339 | mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); | |
340 | ||
341 | mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); | |
342 | ||
343 | return mcr; | |
344 | } | |
345 | ||
346 | /** | |
347 | * setup_i2c_controller() - setup the controller | |
348 | * @dev: private data of controller | |
349 | */ | |
350 | static void setup_i2c_controller(struct nmk_i2c_dev *dev) | |
351 | { | |
352 | u32 brcr1, brcr2; | |
353 | u32 i2c_clk, div; | |
354 | ||
355 | writel(0x0, dev->virtbase + I2C_CR); | |
356 | writel(0x0, dev->virtbase + I2C_HSMCR); | |
357 | writel(0x0, dev->virtbase + I2C_TFTR); | |
358 | writel(0x0, dev->virtbase + I2C_RFTR); | |
359 | writel(0x0, dev->virtbase + I2C_DMAR); | |
360 | ||
361 | /* | |
362 | * set the slsu: | |
363 | * | |
364 | * slsu defines the data setup time after SCL clock | |
365 | * stretching in terms of i2c clk cycles. The | |
366 | * needed setup time for the three modes are 250ns, | |
25985edc | 367 | * 100ns, 10ns respectively thus leading to the values |
3f9900f1 | 368 | * of 14, 6, 2 for a 48 MHz i2c clk. |
369 | */ | |
370 | writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); | |
371 | ||
372 | i2c_clk = clk_get_rate(dev->clk); | |
373 | ||
3f9900f1 | 374 | /* |
375 | * The spec says, in case of std. mode the divider is | |
376 | * 2 whereas it is 3 for fast and fastplus mode of | |
377 | * operation. TODO - high speed support. | |
378 | */ | |
379 | div = (dev->cfg.clk_freq > 100000) ? 3 : 2; | |
380 | ||
381 | /* | |
382 | * generate the mask for baud rate counters. The controller | |
383 | * has two baud rate counters. One is used for High speed | |
384 | * operation, and the other is for std, fast mode, fast mode | |
385 | * plus operation. Currently we do not supprt high speed mode | |
386 | * so set brcr1 to 0. | |
387 | */ | |
388 | brcr1 = 0 << 16; | |
389 | brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; | |
390 | ||
391 | /* set the baud rate counter register */ | |
392 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
393 | ||
394 | /* | |
395 | * set the speed mode. Currently we support | |
396 | * only standard and fast mode of operation | |
25985edc | 397 | * TODO - support for fast mode plus (up to 1Mb/s) |
3f9900f1 | 398 | * and high speed (up to 3.4 Mb/s) |
399 | */ | |
400 | if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { | |
23560214 | 401 | dev_err(&dev->adev->dev, |
8abf6fbb | 402 | "do not support this mode defaulting to std. mode\n"); |
3f9900f1 | 403 | brcr2 = i2c_clk/(100000 * 2) & 0xffff; |
404 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
405 | writel(I2C_FREQ_MODE_STANDARD << 4, | |
406 | dev->virtbase + I2C_CR); | |
407 | } | |
408 | writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); | |
409 | ||
410 | /* set the Tx and Rx FIFO threshold */ | |
411 | writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); | |
412 | writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); | |
413 | } | |
414 | ||
415 | /** | |
416 | * read_i2c() - Read from I2C client device | |
417 | * @dev: private data of I2C Driver | |
51a0c8d0 | 418 | * @flags: message flags |
3f9900f1 | 419 | * |
420 | * This function reads from i2c client device when controller is in | |
421 | * master mode. There is a completion timeout. If there is no transfer | |
422 | * before timeout error is returned. | |
423 | */ | |
51a0c8d0 | 424 | static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 425 | { |
426 | u32 status = 0; | |
876ae85c | 427 | u32 mcr, irq_mask; |
3f9900f1 | 428 | int timeout; |
429 | ||
51a0c8d0 | 430 | mcr = load_i2c_mcr_reg(dev, flags); |
3f9900f1 | 431 | writel(mcr, dev->virtbase + I2C_MCR); |
432 | ||
433 | /* load the current CR value */ | |
434 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
435 | dev->virtbase + I2C_CR); | |
436 | ||
437 | /* enable the controller */ | |
438 | i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
439 | ||
440 | init_completion(&dev->xfer_complete); | |
441 | ||
442 | /* enable interrupts by setting the mask */ | |
443 | irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | | |
444 | I2C_IT_MAL | I2C_IT_BERR); | |
445 | ||
3a205be5 | 446 | if (dev->stop || !dev->vendor->has_mtdws) |
3f9900f1 | 447 | irq_mask |= I2C_IT_MTD; |
448 | else | |
449 | irq_mask |= I2C_IT_MTDWS; | |
450 | ||
451 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
452 | ||
453 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
454 | dev->virtbase + I2C_IMSCR); | |
455 | ||
4b723a47 | 456 | timeout = wait_for_completion_timeout( |
cd20e4fa | 457 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 458 | |
3f9900f1 | 459 | if (timeout == 0) { |
0511f643 | 460 | /* Controller timed out */ |
23560214 | 461 | dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", |
4cb3f538 | 462 | dev->cli.slave_adr); |
3f9900f1 | 463 | status = -ETIMEDOUT; |
464 | } | |
3f9900f1 | 465 | return status; |
466 | } | |
467 | ||
55355341 VS |
468 | static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) |
469 | { | |
470 | int count; | |
471 | ||
472 | for (count = (no_bytes - 2); | |
473 | (count > 0) && | |
474 | (dev->cli.count != 0); | |
475 | count--) { | |
476 | /* write to the Tx FIFO */ | |
477 | writeb(*dev->cli.buffer, | |
478 | dev->virtbase + I2C_TFR); | |
479 | dev->cli.buffer++; | |
480 | dev->cli.count--; | |
481 | dev->cli.xfer_bytes++; | |
482 | } | |
483 | ||
484 | } | |
485 | ||
3f9900f1 | 486 | /** |
487 | * write_i2c() - Write data to I2C client. | |
488 | * @dev: private data of I2C Driver | |
51a0c8d0 | 489 | * @flags: message flags |
3f9900f1 | 490 | * |
491 | * This function writes data to I2C client | |
492 | */ | |
51a0c8d0 | 493 | static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 494 | { |
495 | u32 status = 0; | |
876ae85c | 496 | u32 mcr, irq_mask; |
3f9900f1 | 497 | int timeout; |
498 | ||
51a0c8d0 | 499 | mcr = load_i2c_mcr_reg(dev, flags); |
3f9900f1 | 500 | |
501 | writel(mcr, dev->virtbase + I2C_MCR); | |
502 | ||
503 | /* load the current CR value */ | |
504 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
505 | dev->virtbase + I2C_CR); | |
506 | ||
507 | /* enable the controller */ | |
508 | i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
509 | ||
510 | init_completion(&dev->xfer_complete); | |
511 | ||
512 | /* enable interrupts by settings the masks */ | |
55355341 VS |
513 | irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); |
514 | ||
515 | /* Fill the TX FIFO with transmit data */ | |
516 | fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); | |
517 | ||
518 | if (dev->cli.count != 0) | |
519 | irq_mask |= I2C_IT_TXFNE; | |
3f9900f1 | 520 | |
521 | /* | |
522 | * check if we want to transfer a single or multiple bytes, if so | |
523 | * set the MTDWS bit (Master Transaction Done Without Stop) | |
524 | * to start repeated start operation | |
525 | */ | |
3a205be5 | 526 | if (dev->stop || !dev->vendor->has_mtdws) |
3f9900f1 | 527 | irq_mask |= I2C_IT_MTD; |
528 | else | |
529 | irq_mask |= I2C_IT_MTDWS; | |
530 | ||
531 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
532 | ||
533 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
534 | dev->virtbase + I2C_IMSCR); | |
535 | ||
4b723a47 | 536 | timeout = wait_for_completion_timeout( |
cd20e4fa | 537 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 538 | |
3f9900f1 | 539 | if (timeout == 0) { |
0511f643 | 540 | /* Controller timed out */ |
23560214 | 541 | dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", |
4cb3f538 | 542 | dev->cli.slave_adr); |
3f9900f1 | 543 | status = -ETIMEDOUT; |
544 | } | |
545 | ||
546 | return status; | |
547 | } | |
548 | ||
82a44134 LW |
549 | /** |
550 | * nmk_i2c_xfer_one() - transmit a single I2C message | |
551 | * @dev: device with a message encoded into it | |
552 | * @flags: message flags | |
553 | */ | |
554 | static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) | |
555 | { | |
556 | int status; | |
557 | ||
558 | if (flags & I2C_M_RD) { | |
559 | /* read operation */ | |
560 | dev->cli.operation = I2C_READ; | |
51a0c8d0 | 561 | status = read_i2c(dev, flags); |
82a44134 LW |
562 | } else { |
563 | /* write operation */ | |
564 | dev->cli.operation = I2C_WRITE; | |
51a0c8d0 | 565 | status = write_i2c(dev, flags); |
82a44134 LW |
566 | } |
567 | ||
568 | if (status || (dev->result)) { | |
569 | u32 i2c_sr; | |
570 | u32 cause; | |
571 | ||
572 | i2c_sr = readl(dev->virtbase + I2C_SR); | |
573 | /* | |
574 | * Check if the controller I2C operation status | |
575 | * is set to ABORT(11b). | |
576 | */ | |
577 | if (((i2c_sr >> 2) & 0x3) == 0x3) { | |
578 | /* get the abort cause */ | |
579 | cause = (i2c_sr >> 4) & 0x7; | |
23560214 | 580 | dev_err(&dev->adev->dev, "%s\n", |
8abf6fbb | 581 | cause >= ARRAY_SIZE(abort_causes) ? |
82a44134 LW |
582 | "unknown reason" : |
583 | abort_causes[cause]); | |
584 | } | |
585 | ||
586 | (void) init_hw(dev); | |
587 | ||
588 | status = status ? status : dev->result; | |
589 | } | |
590 | ||
591 | return status; | |
592 | } | |
593 | ||
3f9900f1 | 594 | /** |
595 | * nmk_i2c_xfer() - I2C transfer function used by kernel framework | |
1804edd1 LW |
596 | * @i2c_adap: Adapter pointer to the controller |
597 | * @msgs: Pointer to data to be written. | |
598 | * @num_msgs: Number of messages to be executed | |
3f9900f1 | 599 | * |
600 | * This is the function called by the generic kernel i2c_transfer() | |
601 | * or i2c_smbus...() API calls. Note that this code is protected by the | |
602 | * semaphore set in the kernel i2c_transfer() function. | |
603 | * | |
604 | * NOTE: | |
605 | * READ TRANSFER : We impose a restriction of the first message to be the | |
8abf6fbb JA |
606 | * index message for any read transaction. |
607 | * - a no index is coded as '0', | |
608 | * - 2byte big endian index is coded as '3' | |
609 | * !!! msg[0].buf holds the actual index. | |
610 | * This is compatible with generic messages of smbus emulator | |
611 | * that send a one byte index. | |
612 | * eg. a I2C transation to read 2 bytes from index 0 | |
3f9900f1 | 613 | * idx = 0; |
614 | * msg[0].addr = client->addr; | |
615 | * msg[0].flags = 0x0; | |
616 | * msg[0].len = 1; | |
617 | * msg[0].buf = &idx; | |
618 | * | |
619 | * msg[1].addr = client->addr; | |
620 | * msg[1].flags = I2C_M_RD; | |
621 | * msg[1].len = 2; | |
622 | * msg[1].buf = rd_buff | |
623 | * i2c_transfer(adap, msg, 2); | |
624 | * | |
625 | * WRITE TRANSFER : The I2C standard interface interprets all data as payload. | |
626 | * If you want to emulate an SMBUS write transaction put the | |
627 | * index as first byte(or first and second) in the payload. | |
628 | * eg. a I2C transation to write 2 bytes from index 1 | |
629 | * wr_buff[0] = 0x1; | |
630 | * wr_buff[1] = 0x23; | |
631 | * wr_buff[2] = 0x46; | |
632 | * msg[0].flags = 0x0; | |
633 | * msg[0].len = 3; | |
634 | * msg[0].buf = wr_buff; | |
635 | * i2c_transfer(adap, msg, 1); | |
636 | * | |
637 | * To read or write a block of data (multiple bytes) using SMBUS emulation | |
638 | * please use the i2c_smbus_read_i2c_block_data() | |
639 | * or i2c_smbus_write_i2c_block_data() API | |
640 | */ | |
641 | static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, | |
642 | struct i2c_msg msgs[], int num_msgs) | |
643 | { | |
644 | int status; | |
645 | int i; | |
3f9900f1 | 646 | struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); |
ebd10e07 | 647 | int j; |
3f9900f1 | 648 | |
a20d2394 JA |
649 | dev->busy = true; |
650 | ||
23560214 | 651 | pm_runtime_get_sync(&dev->adev->dev); |
a20d2394 | 652 | |
817315f5 PB |
653 | status = clk_prepare_enable(dev->clk); |
654 | if (status) { | |
655 | dev_err(&dev->adev->dev, "can't prepare_enable clock\n"); | |
656 | goto out_clk; | |
657 | } | |
ebd10e07 | 658 | |
24e9e157 PC |
659 | /* Optionaly enable pins to be muxed in and configured */ |
660 | if (!IS_ERR(dev->pins_default)) { | |
661 | status = pinctrl_select_state(dev->pinctrl, | |
662 | dev->pins_default); | |
663 | if (status) | |
664 | dev_err(&dev->adev->dev, | |
665 | "could not set default pins\n"); | |
666 | } | |
667 | ||
3f9900f1 | 668 | status = init_hw(dev); |
669 | if (status) | |
ebd10e07 | 670 | goto out; |
8ef4f4e4 | 671 | |
82a44134 | 672 | /* Attempt three times to send the message queue */ |
ebd10e07 VS |
673 | for (j = 0; j < 3; j++) { |
674 | /* setup the i2c controller */ | |
675 | setup_i2c_controller(dev); | |
3f9900f1 | 676 | |
ebd10e07 | 677 | for (i = 0; i < num_msgs; i++) { |
ebd10e07 VS |
678 | dev->cli.slave_adr = msgs[i].addr; |
679 | dev->cli.buffer = msgs[i].buf; | |
680 | dev->cli.count = msgs[i].len; | |
681 | dev->stop = (i < (num_msgs - 1)) ? 0 : 1; | |
682 | dev->result = 0; | |
683 | ||
82a44134 LW |
684 | status = nmk_i2c_xfer_one(dev, msgs[i].flags); |
685 | if (status != 0) | |
ebd10e07 | 686 | break; |
3f9900f1 | 687 | } |
ebd10e07 VS |
688 | if (status == 0) |
689 | break; | |
3f9900f1 | 690 | } |
a20d2394 JA |
691 | |
692 | out: | |
817315f5 PB |
693 | clk_disable_unprepare(dev->clk); |
694 | out_clk: | |
24e9e157 PC |
695 | /* Optionally let pins go into idle state */ |
696 | if (!IS_ERR(dev->pins_idle)) { | |
697 | status = pinctrl_select_state(dev->pinctrl, | |
698 | dev->pins_idle); | |
699 | if (status) | |
700 | dev_err(&dev->adev->dev, | |
701 | "could not set pins to idle state\n"); | |
702 | } | |
703 | ||
23560214 | 704 | pm_runtime_put_sync(&dev->adev->dev); |
a20d2394 JA |
705 | |
706 | dev->busy = false; | |
8ef4f4e4 | 707 | |
3f9900f1 | 708 | /* return the no. messages processed */ |
709 | if (status) | |
710 | return status; | |
711 | else | |
712 | return num_msgs; | |
713 | } | |
714 | ||
715 | /** | |
716 | * disable_interrupts() - disable the interrupts | |
717 | * @dev: private data of controller | |
1804edd1 | 718 | * @irq: interrupt number |
3f9900f1 | 719 | */ |
720 | static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) | |
721 | { | |
722 | irq = IRQ_MASK(irq); | |
723 | writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), | |
724 | dev->virtbase + I2C_IMSCR); | |
725 | return 0; | |
726 | } | |
727 | ||
728 | /** | |
729 | * i2c_irq_handler() - interrupt routine | |
730 | * @irq: interrupt number | |
731 | * @arg: data passed to the handler | |
732 | * | |
733 | * This is the interrupt handler for the i2c driver. Currently | |
734 | * it handles the major interrupts like Rx & Tx FIFO management | |
735 | * interrupts, master transaction interrupts, arbitration and | |
736 | * bus error interrupts. The rest of the interrupts are treated as | |
737 | * unhandled. | |
738 | */ | |
739 | static irqreturn_t i2c_irq_handler(int irq, void *arg) | |
740 | { | |
741 | struct nmk_i2c_dev *dev = arg; | |
742 | u32 tft, rft; | |
743 | u32 count; | |
876ae85c | 744 | u32 misr, src; |
3f9900f1 | 745 | |
746 | /* load Tx FIFO and Rx FIFO threshold values */ | |
747 | tft = readl(dev->virtbase + I2C_TFTR); | |
748 | rft = readl(dev->virtbase + I2C_RFTR); | |
749 | ||
750 | /* read interrupt status register */ | |
751 | misr = readl(dev->virtbase + I2C_MISR); | |
752 | ||
753 | src = __ffs(misr); | |
754 | switch ((1 << src)) { | |
755 | ||
756 | /* Transmit FIFO nearly empty interrupt */ | |
757 | case I2C_IT_TXFNE: | |
758 | { | |
759 | if (dev->cli.operation == I2C_READ) { | |
760 | /* | |
761 | * in read operation why do we care for writing? | |
762 | * so disable the Transmit FIFO interrupt | |
763 | */ | |
764 | disable_interrupts(dev, I2C_IT_TXFNE); | |
765 | } else { | |
55355341 | 766 | fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); |
3f9900f1 | 767 | /* |
768 | * if done, close the transfer by disabling the | |
769 | * corresponding TXFNE interrupt | |
770 | */ | |
771 | if (dev->cli.count == 0) | |
772 | disable_interrupts(dev, I2C_IT_TXFNE); | |
773 | } | |
774 | } | |
775 | break; | |
776 | ||
777 | /* | |
778 | * Rx FIFO nearly full interrupt. | |
779 | * This is set when the numer of entries in Rx FIFO is | |
780 | * greater or equal than the threshold value programmed | |
781 | * in RFT | |
782 | */ | |
783 | case I2C_IT_RXFNF: | |
784 | for (count = rft; count > 0; count--) { | |
785 | /* Read the Rx FIFO */ | |
786 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
787 | dev->cli.buffer++; | |
788 | } | |
789 | dev->cli.count -= rft; | |
790 | dev->cli.xfer_bytes += rft; | |
791 | break; | |
792 | ||
793 | /* Rx FIFO full */ | |
794 | case I2C_IT_RXFF: | |
795 | for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { | |
796 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
797 | dev->cli.buffer++; | |
798 | } | |
799 | dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; | |
800 | dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; | |
801 | break; | |
802 | ||
803 | /* Master Transaction Done with/without stop */ | |
804 | case I2C_IT_MTD: | |
805 | case I2C_IT_MTDWS: | |
806 | if (dev->cli.operation == I2C_READ) { | |
1df3ab1b RV |
807 | while (!(readl(dev->virtbase + I2C_RISR) |
808 | & I2C_IT_RXFE)) { | |
3f9900f1 | 809 | if (dev->cli.count == 0) |
810 | break; | |
811 | *dev->cli.buffer = | |
812 | readb(dev->virtbase + I2C_RFR); | |
813 | dev->cli.buffer++; | |
814 | dev->cli.count--; | |
815 | dev->cli.xfer_bytes++; | |
816 | } | |
817 | } | |
818 | ||
b5e890f7 VS |
819 | disable_all_interrupts(dev); |
820 | clear_all_interrupts(dev); | |
3f9900f1 | 821 | |
822 | if (dev->cli.count) { | |
99381bec | 823 | dev->result = -EIO; |
23560214 | 824 | dev_err(&dev->adev->dev, |
8abf6fbb JA |
825 | "%lu bytes still remain to be xfered\n", |
826 | dev->cli.count); | |
3f9900f1 | 827 | (void) init_hw(dev); |
828 | } | |
829 | complete(&dev->xfer_complete); | |
830 | ||
831 | break; | |
832 | ||
833 | /* Master Arbitration lost interrupt */ | |
834 | case I2C_IT_MAL: | |
99381bec | 835 | dev->result = -EIO; |
3f9900f1 | 836 | (void) init_hw(dev); |
837 | ||
838 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); | |
839 | complete(&dev->xfer_complete); | |
840 | ||
841 | break; | |
842 | ||
843 | /* | |
844 | * Bus Error interrupt. | |
845 | * This happens when an unexpected start/stop condition occurs | |
846 | * during the transaction. | |
847 | */ | |
848 | case I2C_IT_BERR: | |
99381bec | 849 | dev->result = -EIO; |
3f9900f1 | 850 | /* get the status */ |
851 | if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) | |
852 | (void) init_hw(dev); | |
853 | ||
854 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); | |
855 | complete(&dev->xfer_complete); | |
856 | ||
857 | break; | |
858 | ||
859 | /* | |
860 | * Tx FIFO overrun interrupt. | |
861 | * This is set when a write operation in Tx FIFO is performed and | |
862 | * the Tx FIFO is full. | |
863 | */ | |
864 | case I2C_IT_TXFOVR: | |
99381bec | 865 | dev->result = -EIO; |
3f9900f1 | 866 | (void) init_hw(dev); |
867 | ||
23560214 | 868 | dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); |
3f9900f1 | 869 | complete(&dev->xfer_complete); |
870 | ||
871 | break; | |
872 | ||
873 | /* unhandled interrupts by this driver - TODO*/ | |
874 | case I2C_IT_TXFE: | |
875 | case I2C_IT_TXFF: | |
876 | case I2C_IT_RXFE: | |
877 | case I2C_IT_RFSR: | |
878 | case I2C_IT_RFSE: | |
879 | case I2C_IT_WTSR: | |
880 | case I2C_IT_STD: | |
23560214 | 881 | dev_err(&dev->adev->dev, "unhandled Interrupt\n"); |
3f9900f1 | 882 | break; |
883 | default: | |
23560214 | 884 | dev_err(&dev->adev->dev, "spurious Interrupt..\n"); |
3f9900f1 | 885 | break; |
886 | } | |
887 | ||
888 | return IRQ_HANDLED; | |
889 | } | |
890 | ||
a20d2394 JA |
891 | |
892 | #ifdef CONFIG_PM | |
b0e751a9 | 893 | static int nmk_i2c_suspend(struct device *dev) |
a20d2394 | 894 | { |
23560214 AR |
895 | struct amba_device *adev = to_amba_device(dev); |
896 | struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); | |
24e9e157 | 897 | int ret; |
a20d2394 | 898 | |
b0e751a9 | 899 | if (nmk_i2c->busy) |
a20d2394 | 900 | return -EBUSY; |
b0e751a9 | 901 | |
24e9e157 PC |
902 | if (!IS_ERR(nmk_i2c->pins_sleep)) { |
903 | ret = pinctrl_select_state(nmk_i2c->pinctrl, | |
904 | nmk_i2c->pins_sleep); | |
905 | if (ret) | |
906 | dev_err(dev, "could not set pins to sleep state\n"); | |
907 | } | |
908 | ||
b0e751a9 RV |
909 | return 0; |
910 | } | |
911 | ||
912 | static int nmk_i2c_resume(struct device *dev) | |
913 | { | |
24e9e157 PC |
914 | struct amba_device *adev = to_amba_device(dev); |
915 | struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); | |
916 | int ret; | |
917 | ||
918 | /* First go to the default state */ | |
919 | if (!IS_ERR(nmk_i2c->pins_default)) { | |
920 | ret = pinctrl_select_state(nmk_i2c->pinctrl, | |
921 | nmk_i2c->pins_default); | |
922 | if (ret) | |
923 | dev_err(dev, "could not set pins to default state\n"); | |
924 | } | |
925 | /* Then let's idle the pins until the next transfer happens */ | |
926 | if (!IS_ERR(nmk_i2c->pins_idle)) { | |
927 | ret = pinctrl_select_state(nmk_i2c->pinctrl, | |
928 | nmk_i2c->pins_idle); | |
929 | if (ret) | |
930 | dev_err(dev, "could not set pins to idle state\n"); | |
931 | } | |
b0e751a9 | 932 | return 0; |
a20d2394 JA |
933 | } |
934 | #else | |
935 | #define nmk_i2c_suspend NULL | |
b0e751a9 | 936 | #define nmk_i2c_resume NULL |
a20d2394 JA |
937 | #endif |
938 | ||
b0e751a9 RV |
939 | /* |
940 | * We use noirq so that we suspend late and resume before the wakeup interrupt | |
941 | * to ensure that we do the !pm_runtime_suspended() check in resume before | |
942 | * there has been a regular pm runtime resume (via pm_runtime_get_sync()). | |
943 | */ | |
944 | static const struct dev_pm_ops nmk_i2c_pm = { | |
945 | .suspend_noirq = nmk_i2c_suspend, | |
946 | .resume_noirq = nmk_i2c_resume, | |
947 | }; | |
948 | ||
3f9900f1 | 949 | static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) |
950 | { | |
51a0c8d0 | 951 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; |
3f9900f1 | 952 | } |
953 | ||
954 | static const struct i2c_algorithm nmk_i2c_algo = { | |
955 | .master_xfer = nmk_i2c_xfer, | |
956 | .functionality = nmk_i2c_functionality | |
957 | }; | |
958 | ||
b007a3ef LJ |
959 | static struct nmk_i2c_controller u8500_i2c = { |
960 | /* | |
961 | * Slave data setup time; 250ns, 100ns, and 10ns, which | |
962 | * is 14, 6 and 2 respectively for a 48Mhz i2c clock. | |
963 | */ | |
964 | .slsu = 0xe, | |
965 | .tft = 1, /* Tx FIFO threshold */ | |
966 | .rft = 8, /* Rx FIFO threshold */ | |
967 | .clk_freq = 400000, /* fast mode operation */ | |
968 | .timeout = 200, /* Slave response timeout(ms) */ | |
969 | .sm = I2C_FREQ_MODE_FAST, | |
970 | }; | |
971 | ||
43fea581 LJ |
972 | static void nmk_i2c_of_probe(struct device_node *np, |
973 | struct nmk_i2c_controller *pdata) | |
974 | { | |
975 | of_property_read_u32(np, "clock-frequency", &pdata->clk_freq); | |
976 | ||
977 | /* This driver only supports 'standard' and 'fast' modes of operation. */ | |
978 | if (pdata->clk_freq <= 100000) | |
979 | pdata->sm = I2C_FREQ_MODE_STANDARD; | |
980 | else | |
981 | pdata->sm = I2C_FREQ_MODE_FAST; | |
982 | } | |
983 | ||
23560214 AR |
984 | static atomic_t adapter_id = ATOMIC_INIT(0); |
985 | ||
986 | static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) | |
3f9900f1 | 987 | { |
988 | int ret = 0; | |
b007a3ef | 989 | struct nmk_i2c_controller *pdata = adev->dev.platform_data; |
43fea581 | 990 | struct device_node *np = adev->dev.of_node; |
3f9900f1 | 991 | struct nmk_i2c_dev *dev; |
992 | struct i2c_adapter *adap; | |
3a205be5 LW |
993 | struct i2c_vendor_data *vendor = id->data; |
994 | u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; | |
3f9900f1 | 995 | |
43fea581 LJ |
996 | if (!pdata) { |
997 | if (np) { | |
998 | pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL); | |
999 | if (!pdata) { | |
1000 | ret = -ENOMEM; | |
1001 | goto err_no_mem; | |
1002 | } | |
1003 | /* Provide the default configuration as a base. */ | |
1004 | memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller)); | |
1005 | nmk_i2c_of_probe(np, pdata); | |
1006 | } else | |
1007 | /* No i2c configuration found, using the default. */ | |
1008 | pdata = &u8500_i2c; | |
1009 | } | |
b007a3ef | 1010 | |
3a205be5 LW |
1011 | if (pdata->tft > max_fifo_threshold) { |
1012 | dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n", | |
1013 | pdata->tft, max_fifo_threshold); | |
1014 | pdata->tft = max_fifo_threshold; | |
1015 | } | |
1016 | ||
1017 | if (pdata->rft > max_fifo_threshold) { | |
1018 | dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n", | |
1019 | pdata->rft, max_fifo_threshold); | |
1020 | pdata->rft = max_fifo_threshold; | |
1021 | } | |
1022 | ||
3f9900f1 | 1023 | dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); |
1024 | if (!dev) { | |
23560214 | 1025 | dev_err(&adev->dev, "cannot allocate memory\n"); |
3f9900f1 | 1026 | ret = -ENOMEM; |
1027 | goto err_no_mem; | |
1028 | } | |
3a205be5 | 1029 | dev->vendor = vendor; |
a20d2394 | 1030 | dev->busy = false; |
23560214 AR |
1031 | dev->adev = adev; |
1032 | amba_set_drvdata(adev, dev); | |
3f9900f1 | 1033 | |
24e9e157 PC |
1034 | dev->pinctrl = devm_pinctrl_get(&adev->dev); |
1035 | if (IS_ERR(dev->pinctrl)) { | |
1036 | ret = PTR_ERR(dev->pinctrl); | |
1037 | goto err_pinctrl; | |
1038 | } | |
1039 | ||
1040 | dev->pins_default = pinctrl_lookup_state(dev->pinctrl, | |
1041 | PINCTRL_STATE_DEFAULT); | |
1042 | if (IS_ERR(dev->pins_default)) { | |
1043 | dev_err(&adev->dev, "could not get default pinstate\n"); | |
1044 | } else { | |
1045 | ret = pinctrl_select_state(dev->pinctrl, | |
1046 | dev->pins_default); | |
1047 | if (ret) | |
1048 | dev_dbg(&adev->dev, "could not set default pinstate\n"); | |
1049 | } | |
1050 | ||
1051 | dev->pins_idle = pinctrl_lookup_state(dev->pinctrl, | |
1052 | PINCTRL_STATE_IDLE); | |
1053 | if (IS_ERR(dev->pins_idle)) { | |
1054 | dev_dbg(&adev->dev, "could not get idle pinstate\n"); | |
1055 | } else { | |
1056 | /* If possible, let's go to idle until the first transfer */ | |
1057 | ret = pinctrl_select_state(dev->pinctrl, | |
1058 | dev->pins_idle); | |
1059 | if (ret) | |
1060 | dev_dbg(&adev->dev, "could not set idle pinstate\n"); | |
1061 | } | |
1062 | ||
1063 | dev->pins_sleep = pinctrl_lookup_state(dev->pinctrl, | |
1064 | PINCTRL_STATE_SLEEP); | |
1065 | if (IS_ERR(dev->pins_sleep)) | |
1066 | dev_dbg(&adev->dev, "could not get sleep pinstate\n"); | |
1067 | ||
23560214 | 1068 | dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
3f9900f1 | 1069 | if (!dev->virtbase) { |
1070 | ret = -ENOMEM; | |
1071 | goto err_no_ioremap; | |
1072 | } | |
1073 | ||
23560214 | 1074 | dev->irq = adev->irq[0]; |
4311051c | 1075 | ret = request_irq(dev->irq, i2c_irq_handler, 0, |
3f9900f1 | 1076 | DRIVER_NAME, dev); |
1077 | if (ret) { | |
23560214 | 1078 | dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); |
3f9900f1 | 1079 | goto err_irq; |
1080 | } | |
1081 | ||
23560214 | 1082 | pm_suspend_ignore_children(&adev->dev, true); |
b0e751a9 | 1083 | |
23560214 | 1084 | dev->clk = clk_get(&adev->dev, NULL); |
3f9900f1 | 1085 | if (IS_ERR(dev->clk)) { |
23560214 | 1086 | dev_err(&adev->dev, "could not get i2c clock\n"); |
3f9900f1 | 1087 | ret = PTR_ERR(dev->clk); |
1088 | goto err_no_clk; | |
1089 | } | |
1090 | ||
3f9900f1 | 1091 | adap = &dev->adap; |
43fea581 | 1092 | adap->dev.of_node = np; |
23560214 | 1093 | adap->dev.parent = &adev->dev; |
3f9900f1 | 1094 | adap->owner = THIS_MODULE; |
1095 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1096 | adap->algo = &nmk_i2c_algo; | |
98582d95 | 1097 | adap->timeout = msecs_to_jiffies(pdata->timeout); |
23560214 | 1098 | adap->nr = atomic_read(&adapter_id); |
6d779a4c | 1099 | snprintf(adap->name, sizeof(adap->name), |
23560214 AR |
1100 | "Nomadik I2C%d at %pR", adap->nr, &adev->res); |
1101 | atomic_inc(&adapter_id); | |
3f9900f1 | 1102 | |
1103 | /* fetch the controller configuration from machine */ | |
1104 | dev->cfg.clk_freq = pdata->clk_freq; | |
1105 | dev->cfg.slsu = pdata->slsu; | |
1106 | dev->cfg.tft = pdata->tft; | |
1107 | dev->cfg.rft = pdata->rft; | |
1108 | dev->cfg.sm = pdata->sm; | |
1109 | ||
1110 | i2c_set_adapdata(adap, dev); | |
1111 | ||
23560214 | 1112 | dev_info(&adev->dev, |
8abf6fbb JA |
1113 | "initialize %s on virtual base %p\n", |
1114 | adap->name, dev->virtbase); | |
3f9900f1 | 1115 | |
1116 | ret = i2c_add_numbered_adapter(adap); | |
1117 | if (ret) { | |
23560214 | 1118 | dev_err(&adev->dev, "failed to add adapter\n"); |
3f9900f1 | 1119 | goto err_add_adap; |
1120 | } | |
1121 | ||
43fea581 LJ |
1122 | of_i2c_register_devices(adap); |
1123 | ||
23560214 AR |
1124 | pm_runtime_put(&adev->dev); |
1125 | ||
3f9900f1 | 1126 | return 0; |
1127 | ||
3f9900f1 | 1128 | err_add_adap: |
1129 | clk_put(dev->clk); | |
1130 | err_no_clk: | |
1131 | free_irq(dev->irq, dev); | |
1132 | err_irq: | |
1133 | iounmap(dev->virtbase); | |
1134 | err_no_ioremap: | |
3f9900f1 | 1135 | kfree(dev); |
24e9e157 | 1136 | err_pinctrl: |
3f9900f1 | 1137 | err_no_mem: |
1138 | ||
1139 | return ret; | |
1140 | } | |
1141 | ||
23560214 | 1142 | static int nmk_i2c_remove(struct amba_device *adev) |
3f9900f1 | 1143 | { |
23560214 AR |
1144 | struct resource *res = &adev->res; |
1145 | struct nmk_i2c_dev *dev = amba_get_drvdata(adev); | |
3f9900f1 | 1146 | |
1147 | i2c_del_adapter(&dev->adap); | |
1148 | flush_i2c_fifo(dev); | |
1149 | disable_all_interrupts(dev); | |
1150 | clear_all_interrupts(dev); | |
1151 | /* disable the controller */ | |
1152 | i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
1153 | free_irq(dev->irq, dev); | |
1154 | iounmap(dev->virtbase); | |
a1c27678 RV |
1155 | if (res) |
1156 | release_mem_region(res->start, resource_size(res)); | |
3f9900f1 | 1157 | clk_put(dev->clk); |
23560214 | 1158 | pm_runtime_disable(&adev->dev); |
3f9900f1 | 1159 | kfree(dev); |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
3a205be5 LW |
1164 | static struct i2c_vendor_data vendor_stn8815 = { |
1165 | .has_mtdws = false, | |
1166 | .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ | |
1167 | }; | |
1168 | ||
1169 | static struct i2c_vendor_data vendor_db8500 = { | |
1170 | .has_mtdws = true, | |
1171 | .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ | |
1172 | }; | |
1173 | ||
23560214 AR |
1174 | static struct amba_id nmk_i2c_ids[] = { |
1175 | { | |
1176 | .id = 0x00180024, | |
1177 | .mask = 0x00ffffff, | |
3a205be5 | 1178 | .data = &vendor_stn8815, |
23560214 AR |
1179 | }, |
1180 | { | |
1181 | .id = 0x00380024, | |
1182 | .mask = 0x00ffffff, | |
3a205be5 | 1183 | .data = &vendor_db8500, |
23560214 AR |
1184 | }, |
1185 | {}, | |
1186 | }; | |
1187 | ||
1188 | MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); | |
1189 | ||
1190 | static struct amba_driver nmk_i2c_driver = { | |
1191 | .drv = { | |
3f9900f1 | 1192 | .owner = THIS_MODULE, |
1193 | .name = DRIVER_NAME, | |
b0e751a9 | 1194 | .pm = &nmk_i2c_pm, |
3f9900f1 | 1195 | }, |
23560214 | 1196 | .id_table = nmk_i2c_ids, |
3f9900f1 | 1197 | .probe = nmk_i2c_probe, |
23560214 | 1198 | .remove = nmk_i2c_remove, |
3f9900f1 | 1199 | }; |
1200 | ||
1201 | static int __init nmk_i2c_init(void) | |
1202 | { | |
23560214 | 1203 | return amba_driver_register(&nmk_i2c_driver); |
3f9900f1 | 1204 | } |
1205 | ||
1206 | static void __exit nmk_i2c_exit(void) | |
1207 | { | |
23560214 | 1208 | amba_driver_unregister(&nmk_i2c_driver); |
3f9900f1 | 1209 | } |
1210 | ||
1211 | subsys_initcall(nmk_i2c_init); | |
1212 | module_exit(nmk_i2c_exit); | |
1213 | ||
1214 | MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); | |
1215 | MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); | |
1216 | MODULE_LICENSE("GPL"); |