]>
Commit | Line | Data |
---|---|---|
3f9900f1 | 1 | /* |
1804edd1 | 2 | * Copyright (C) 2009 ST-Ericsson SA |
3f9900f1 | 3 | * Copyright (C) 2009 STMicroelectronics |
4 | * | |
5 | * I2C master mode controller driver, used in Nomadik 8815 | |
6 | * and Ux500 platforms. | |
7 | * | |
8 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
9 | * Author: Sachin Verma <sachin.verma@st.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2, as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
23560214 | 17 | #include <linux/amba/bus.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
3f9900f1 | 19 | #include <linux/interrupt.h> |
20 | #include <linux/i2c.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
b0e751a9 | 24 | #include <linux/pm_runtime.h> |
af97bace | 25 | #include <linux/platform_data/i2c-nomadik.h> |
43fea581 | 26 | #include <linux/of.h> |
24e9e157 | 27 | #include <linux/pinctrl/consumer.h> |
3f9900f1 | 28 | |
29 | #define DRIVER_NAME "nmk-i2c" | |
30 | ||
31 | /* I2C Controller register offsets */ | |
32 | #define I2C_CR (0x000) | |
33 | #define I2C_SCR (0x004) | |
34 | #define I2C_HSMCR (0x008) | |
35 | #define I2C_MCR (0x00C) | |
36 | #define I2C_TFR (0x010) | |
37 | #define I2C_SR (0x014) | |
38 | #define I2C_RFR (0x018) | |
39 | #define I2C_TFTR (0x01C) | |
40 | #define I2C_RFTR (0x020) | |
41 | #define I2C_DMAR (0x024) | |
42 | #define I2C_BRCR (0x028) | |
43 | #define I2C_IMSCR (0x02C) | |
44 | #define I2C_RISR (0x030) | |
45 | #define I2C_MISR (0x034) | |
46 | #define I2C_ICR (0x038) | |
47 | ||
48 | /* Control registers */ | |
49 | #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ | |
50 | #define I2C_CR_OM (0x3 << 1) /* Operating mode */ | |
51 | #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ | |
52 | #define I2C_CR_SM (0x3 << 4) /* Speed mode */ | |
53 | #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ | |
54 | #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ | |
55 | #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ | |
56 | #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ | |
57 | #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ | |
58 | #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ | |
59 | #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ | |
60 | #define I2C_CR_FON (0x3 << 13) /* Filtering on */ | |
61 | #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ | |
62 | ||
63 | /* Master controller (MCR) register */ | |
64 | #define I2C_MCR_OP (0x1 << 0) /* Operation */ | |
65 | #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ | |
8abf6fbb | 66 | #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ |
3f9900f1 | 67 | #define I2C_MCR_SB (0x1 << 11) /* Extended address */ |
68 | #define I2C_MCR_AM (0x3 << 12) /* Address type */ | |
8abf6fbb JA |
69 | #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ |
70 | #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ | |
3f9900f1 | 71 | |
72 | /* Status register (SR) */ | |
73 | #define I2C_SR_OP (0x3 << 0) /* Operation */ | |
74 | #define I2C_SR_STATUS (0x3 << 2) /* controller status */ | |
75 | #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ | |
76 | #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ | |
77 | #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ | |
78 | ||
79 | /* Interrupt mask set/clear (IMSCR) bits */ | |
8abf6fbb | 80 | #define I2C_IT_TXFE (0x1 << 0) |
3f9900f1 | 81 | #define I2C_IT_TXFNE (0x1 << 1) |
82 | #define I2C_IT_TXFF (0x1 << 2) | |
83 | #define I2C_IT_TXFOVR (0x1 << 3) | |
84 | #define I2C_IT_RXFE (0x1 << 4) | |
85 | #define I2C_IT_RXFNF (0x1 << 5) | |
86 | #define I2C_IT_RXFF (0x1 << 6) | |
87 | #define I2C_IT_RFSR (0x1 << 16) | |
88 | #define I2C_IT_RFSE (0x1 << 17) | |
89 | #define I2C_IT_WTSR (0x1 << 18) | |
90 | #define I2C_IT_MTD (0x1 << 19) | |
91 | #define I2C_IT_STD (0x1 << 20) | |
92 | #define I2C_IT_MAL (0x1 << 24) | |
93 | #define I2C_IT_BERR (0x1 << 25) | |
94 | #define I2C_IT_MTDWS (0x1 << 28) | |
95 | ||
96 | #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) | |
97 | ||
98 | /* some bits in ICR are reserved */ | |
99 | #define I2C_CLEAR_ALL_INTS 0x131f007f | |
100 | ||
101 | /* first three msb bits are reserved */ | |
102 | #define IRQ_MASK(mask) (mask & 0x1fffffff) | |
103 | ||
104 | /* maximum threshold value */ | |
105 | #define MAX_I2C_FIFO_THRESHOLD 15 | |
106 | ||
3a205be5 LW |
107 | /** |
108 | * struct i2c_vendor_data - per-vendor variations | |
109 | * @has_mtdws: variant has the MTDWS bit | |
110 | * @fifodepth: variant FIFO depth | |
111 | */ | |
112 | struct i2c_vendor_data { | |
113 | bool has_mtdws; | |
114 | u32 fifodepth; | |
115 | }; | |
116 | ||
3f9900f1 | 117 | enum i2c_status { |
118 | I2C_NOP, | |
119 | I2C_ON_GOING, | |
120 | I2C_OK, | |
121 | I2C_ABORT | |
122 | }; | |
123 | ||
124 | /* operation */ | |
125 | enum i2c_operation { | |
126 | I2C_NO_OPERATION = 0xff, | |
127 | I2C_WRITE = 0x00, | |
128 | I2C_READ = 0x01 | |
129 | }; | |
130 | ||
3f9900f1 | 131 | /** |
132 | * struct i2c_nmk_client - client specific data | |
133 | * @slave_adr: 7-bit slave address | |
25985edc | 134 | * @count: no. bytes to be transferred |
3f9900f1 | 135 | * @buffer: client data buffer |
25985edc | 136 | * @xfer_bytes: bytes transferred till now |
3f9900f1 | 137 | * @operation: current I2C operation |
138 | */ | |
139 | struct i2c_nmk_client { | |
140 | unsigned short slave_adr; | |
141 | unsigned long count; | |
142 | unsigned char *buffer; | |
143 | unsigned long xfer_bytes; | |
144 | enum i2c_operation operation; | |
145 | }; | |
146 | ||
147 | /** | |
8abf6fbb | 148 | * struct nmk_i2c_dev - private data structure of the controller. |
3a205be5 | 149 | * @vendor: vendor data for this variant. |
23560214 | 150 | * @adev: parent amba device. |
8abf6fbb JA |
151 | * @adap: corresponding I2C adapter. |
152 | * @irq: interrupt line for the controller. | |
153 | * @virtbase: virtual io memory area. | |
154 | * @clk: hardware i2c block clock. | |
155 | * @cfg: machine provided controller configuration. | |
156 | * @cli: holder of client specific data. | |
157 | * @stop: stop condition. | |
158 | * @xfer_complete: acknowledge completion for a I2C message. | |
159 | * @result: controller propogated result. | |
8abf6fbb | 160 | * @busy: Busy doing transfer. |
3f9900f1 | 161 | */ |
162 | struct nmk_i2c_dev { | |
3a205be5 | 163 | struct i2c_vendor_data *vendor; |
23560214 | 164 | struct amba_device *adev; |
8abf6fbb JA |
165 | struct i2c_adapter adap; |
166 | int irq; | |
3f9900f1 | 167 | void __iomem *virtbase; |
168 | struct clk *clk; | |
169 | struct nmk_i2c_controller cfg; | |
170 | struct i2c_nmk_client cli; | |
8abf6fbb | 171 | int stop; |
3f9900f1 | 172 | struct completion xfer_complete; |
8abf6fbb | 173 | int result; |
a20d2394 | 174 | bool busy; |
3f9900f1 | 175 | }; |
176 | ||
177 | /* controller's abort causes */ | |
178 | static const char *abort_causes[] = { | |
179 | "no ack received after address transmission", | |
180 | "no ack received during data phase", | |
181 | "ack received after xmission of master code", | |
182 | "master lost arbitration", | |
183 | "slave restarts", | |
184 | "slave reset", | |
185 | "overflow, maxsize is 2047 bytes", | |
186 | }; | |
187 | ||
188 | static inline void i2c_set_bit(void __iomem *reg, u32 mask) | |
189 | { | |
190 | writel(readl(reg) | mask, reg); | |
191 | } | |
192 | ||
193 | static inline void i2c_clr_bit(void __iomem *reg, u32 mask) | |
194 | { | |
195 | writel(readl(reg) & ~mask, reg); | |
196 | } | |
197 | ||
198 | /** | |
199 | * flush_i2c_fifo() - This function flushes the I2C FIFO | |
200 | * @dev: private data of I2C Driver | |
201 | * | |
202 | * This function flushes the I2C Tx and Rx FIFOs. It returns | |
203 | * 0 on successful flushing of FIFO | |
204 | */ | |
205 | static int flush_i2c_fifo(struct nmk_i2c_dev *dev) | |
206 | { | |
207 | #define LOOP_ATTEMPTS 10 | |
208 | int i; | |
209 | unsigned long timeout; | |
210 | ||
211 | /* | |
212 | * flush the transmit and receive FIFO. The flushing | |
213 | * operation takes several cycles before to be completed. | |
214 | * On the completion, the I2C internal logic clears these | |
215 | * bits, until then no one must access Tx, Rx FIFO and | |
216 | * should poll on these bits waiting for the completion. | |
217 | */ | |
218 | writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); | |
219 | ||
220 | for (i = 0; i < LOOP_ATTEMPTS; i++) { | |
cd20e4fa | 221 | timeout = jiffies + dev->adap.timeout; |
3f9900f1 | 222 | |
223 | while (!time_after(jiffies, timeout)) { | |
224 | if ((readl(dev->virtbase + I2C_CR) & | |
225 | (I2C_CR_FTX | I2C_CR_FRX)) == 0) | |
226 | return 0; | |
227 | } | |
228 | } | |
229 | ||
23560214 | 230 | dev_err(&dev->adev->dev, |
8abf6fbb JA |
231 | "flushing operation timed out giving up after %d attempts", |
232 | LOOP_ATTEMPTS); | |
3f9900f1 | 233 | |
234 | return -ETIMEDOUT; | |
235 | } | |
236 | ||
237 | /** | |
238 | * disable_all_interrupts() - Disable all interrupts of this I2c Bus | |
239 | * @dev: private data of I2C Driver | |
240 | */ | |
241 | static void disable_all_interrupts(struct nmk_i2c_dev *dev) | |
242 | { | |
243 | u32 mask = IRQ_MASK(0); | |
244 | writel(mask, dev->virtbase + I2C_IMSCR); | |
245 | } | |
246 | ||
247 | /** | |
248 | * clear_all_interrupts() - Clear all interrupts of I2C Controller | |
249 | * @dev: private data of I2C Driver | |
250 | */ | |
251 | static void clear_all_interrupts(struct nmk_i2c_dev *dev) | |
252 | { | |
253 | u32 mask; | |
254 | mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); | |
255 | writel(mask, dev->virtbase + I2C_ICR); | |
256 | } | |
257 | ||
258 | /** | |
259 | * init_hw() - initialize the I2C hardware | |
260 | * @dev: private data of I2C Driver | |
261 | */ | |
262 | static int init_hw(struct nmk_i2c_dev *dev) | |
263 | { | |
264 | int stat; | |
265 | ||
266 | stat = flush_i2c_fifo(dev); | |
267 | if (stat) | |
a20d2394 | 268 | goto exit; |
3f9900f1 | 269 | |
270 | /* disable the controller */ | |
271 | i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
272 | ||
273 | disable_all_interrupts(dev); | |
274 | ||
275 | clear_all_interrupts(dev); | |
276 | ||
277 | dev->cli.operation = I2C_NO_OPERATION; | |
278 | ||
a20d2394 | 279 | exit: |
a20d2394 | 280 | return stat; |
3f9900f1 | 281 | } |
282 | ||
283 | /* enable peripheral, master mode operation */ | |
8abf6fbb | 284 | #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) |
3f9900f1 | 285 | |
286 | /** | |
287 | * load_i2c_mcr_reg() - load the MCR register | |
288 | * @dev: private data of controller | |
51a0c8d0 | 289 | * @flags: message flags |
3f9900f1 | 290 | */ |
51a0c8d0 | 291 | static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 292 | { |
293 | u32 mcr = 0; | |
51a0c8d0 | 294 | unsigned short slave_adr_3msb_bits; |
3f9900f1 | 295 | |
3f9900f1 | 296 | mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); |
297 | ||
51a0c8d0 VS |
298 | if (unlikely(flags & I2C_M_TEN)) { |
299 | /* 10-bit address transaction */ | |
300 | mcr |= GEN_MASK(2, I2C_MCR_AM, 12); | |
301 | /* | |
302 | * Get the top 3 bits. | |
303 | * EA10 represents extended address in MCR. This includes | |
304 | * the extension (MSB bits) of the 7 bit address loaded | |
305 | * in A7 | |
306 | */ | |
307 | slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; | |
308 | ||
309 | mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); | |
310 | } else { | |
311 | /* 7-bit address transaction */ | |
312 | mcr |= GEN_MASK(1, I2C_MCR_AM, 12); | |
313 | } | |
314 | ||
3f9900f1 | 315 | /* start byte procedure not applied */ |
316 | mcr |= GEN_MASK(0, I2C_MCR_SB, 11); | |
317 | ||
318 | /* check the operation, master read/write? */ | |
319 | if (dev->cli.operation == I2C_WRITE) | |
320 | mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); | |
321 | else | |
322 | mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); | |
323 | ||
324 | /* stop or repeated start? */ | |
325 | if (dev->stop) | |
326 | mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); | |
327 | else | |
328 | mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); | |
329 | ||
330 | mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); | |
331 | ||
332 | return mcr; | |
333 | } | |
334 | ||
335 | /** | |
336 | * setup_i2c_controller() - setup the controller | |
337 | * @dev: private data of controller | |
338 | */ | |
339 | static void setup_i2c_controller(struct nmk_i2c_dev *dev) | |
340 | { | |
341 | u32 brcr1, brcr2; | |
342 | u32 i2c_clk, div; | |
343 | ||
344 | writel(0x0, dev->virtbase + I2C_CR); | |
345 | writel(0x0, dev->virtbase + I2C_HSMCR); | |
346 | writel(0x0, dev->virtbase + I2C_TFTR); | |
347 | writel(0x0, dev->virtbase + I2C_RFTR); | |
348 | writel(0x0, dev->virtbase + I2C_DMAR); | |
349 | ||
350 | /* | |
351 | * set the slsu: | |
352 | * | |
353 | * slsu defines the data setup time after SCL clock | |
354 | * stretching in terms of i2c clk cycles. The | |
355 | * needed setup time for the three modes are 250ns, | |
25985edc | 356 | * 100ns, 10ns respectively thus leading to the values |
3f9900f1 | 357 | * of 14, 6, 2 for a 48 MHz i2c clk. |
358 | */ | |
359 | writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); | |
360 | ||
361 | i2c_clk = clk_get_rate(dev->clk); | |
362 | ||
3f9900f1 | 363 | /* |
364 | * The spec says, in case of std. mode the divider is | |
365 | * 2 whereas it is 3 for fast and fastplus mode of | |
366 | * operation. TODO - high speed support. | |
367 | */ | |
368 | div = (dev->cfg.clk_freq > 100000) ? 3 : 2; | |
369 | ||
370 | /* | |
371 | * generate the mask for baud rate counters. The controller | |
372 | * has two baud rate counters. One is used for High speed | |
373 | * operation, and the other is for std, fast mode, fast mode | |
374 | * plus operation. Currently we do not supprt high speed mode | |
375 | * so set brcr1 to 0. | |
376 | */ | |
377 | brcr1 = 0 << 16; | |
378 | brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; | |
379 | ||
380 | /* set the baud rate counter register */ | |
381 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
382 | ||
383 | /* | |
384 | * set the speed mode. Currently we support | |
385 | * only standard and fast mode of operation | |
25985edc | 386 | * TODO - support for fast mode plus (up to 1Mb/s) |
3f9900f1 | 387 | * and high speed (up to 3.4 Mb/s) |
388 | */ | |
389 | if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { | |
23560214 | 390 | dev_err(&dev->adev->dev, |
8abf6fbb | 391 | "do not support this mode defaulting to std. mode\n"); |
3f9900f1 | 392 | brcr2 = i2c_clk/(100000 * 2) & 0xffff; |
393 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
394 | writel(I2C_FREQ_MODE_STANDARD << 4, | |
395 | dev->virtbase + I2C_CR); | |
396 | } | |
397 | writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); | |
398 | ||
399 | /* set the Tx and Rx FIFO threshold */ | |
400 | writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); | |
401 | writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); | |
402 | } | |
403 | ||
404 | /** | |
405 | * read_i2c() - Read from I2C client device | |
406 | * @dev: private data of I2C Driver | |
51a0c8d0 | 407 | * @flags: message flags |
3f9900f1 | 408 | * |
409 | * This function reads from i2c client device when controller is in | |
410 | * master mode. There is a completion timeout. If there is no transfer | |
411 | * before timeout error is returned. | |
412 | */ | |
51a0c8d0 | 413 | static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 414 | { |
415 | u32 status = 0; | |
876ae85c | 416 | u32 mcr, irq_mask; |
3f9900f1 | 417 | int timeout; |
418 | ||
51a0c8d0 | 419 | mcr = load_i2c_mcr_reg(dev, flags); |
3f9900f1 | 420 | writel(mcr, dev->virtbase + I2C_MCR); |
421 | ||
422 | /* load the current CR value */ | |
423 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
424 | dev->virtbase + I2C_CR); | |
425 | ||
426 | /* enable the controller */ | |
427 | i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
428 | ||
429 | init_completion(&dev->xfer_complete); | |
430 | ||
431 | /* enable interrupts by setting the mask */ | |
432 | irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | | |
433 | I2C_IT_MAL | I2C_IT_BERR); | |
434 | ||
3a205be5 | 435 | if (dev->stop || !dev->vendor->has_mtdws) |
3f9900f1 | 436 | irq_mask |= I2C_IT_MTD; |
437 | else | |
438 | irq_mask |= I2C_IT_MTDWS; | |
439 | ||
440 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
441 | ||
442 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
443 | dev->virtbase + I2C_IMSCR); | |
444 | ||
4b723a47 | 445 | timeout = wait_for_completion_timeout( |
cd20e4fa | 446 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 447 | |
3f9900f1 | 448 | if (timeout == 0) { |
0511f643 | 449 | /* Controller timed out */ |
23560214 | 450 | dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", |
4cb3f538 | 451 | dev->cli.slave_adr); |
3f9900f1 | 452 | status = -ETIMEDOUT; |
453 | } | |
3f9900f1 | 454 | return status; |
455 | } | |
456 | ||
55355341 VS |
457 | static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) |
458 | { | |
459 | int count; | |
460 | ||
461 | for (count = (no_bytes - 2); | |
462 | (count > 0) && | |
463 | (dev->cli.count != 0); | |
464 | count--) { | |
465 | /* write to the Tx FIFO */ | |
466 | writeb(*dev->cli.buffer, | |
467 | dev->virtbase + I2C_TFR); | |
468 | dev->cli.buffer++; | |
469 | dev->cli.count--; | |
470 | dev->cli.xfer_bytes++; | |
471 | } | |
472 | ||
473 | } | |
474 | ||
3f9900f1 | 475 | /** |
476 | * write_i2c() - Write data to I2C client. | |
477 | * @dev: private data of I2C Driver | |
51a0c8d0 | 478 | * @flags: message flags |
3f9900f1 | 479 | * |
480 | * This function writes data to I2C client | |
481 | */ | |
51a0c8d0 | 482 | static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) |
3f9900f1 | 483 | { |
484 | u32 status = 0; | |
876ae85c | 485 | u32 mcr, irq_mask; |
3f9900f1 | 486 | int timeout; |
487 | ||
51a0c8d0 | 488 | mcr = load_i2c_mcr_reg(dev, flags); |
3f9900f1 | 489 | |
490 | writel(mcr, dev->virtbase + I2C_MCR); | |
491 | ||
492 | /* load the current CR value */ | |
493 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
494 | dev->virtbase + I2C_CR); | |
495 | ||
496 | /* enable the controller */ | |
497 | i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
498 | ||
499 | init_completion(&dev->xfer_complete); | |
500 | ||
501 | /* enable interrupts by settings the masks */ | |
55355341 VS |
502 | irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); |
503 | ||
504 | /* Fill the TX FIFO with transmit data */ | |
505 | fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); | |
506 | ||
507 | if (dev->cli.count != 0) | |
508 | irq_mask |= I2C_IT_TXFNE; | |
3f9900f1 | 509 | |
510 | /* | |
511 | * check if we want to transfer a single or multiple bytes, if so | |
512 | * set the MTDWS bit (Master Transaction Done Without Stop) | |
513 | * to start repeated start operation | |
514 | */ | |
3a205be5 | 515 | if (dev->stop || !dev->vendor->has_mtdws) |
3f9900f1 | 516 | irq_mask |= I2C_IT_MTD; |
517 | else | |
518 | irq_mask |= I2C_IT_MTDWS; | |
519 | ||
520 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
521 | ||
522 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
523 | dev->virtbase + I2C_IMSCR); | |
524 | ||
4b723a47 | 525 | timeout = wait_for_completion_timeout( |
cd20e4fa | 526 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 527 | |
3f9900f1 | 528 | if (timeout == 0) { |
0511f643 | 529 | /* Controller timed out */ |
23560214 | 530 | dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", |
4cb3f538 | 531 | dev->cli.slave_adr); |
3f9900f1 | 532 | status = -ETIMEDOUT; |
533 | } | |
534 | ||
535 | return status; | |
536 | } | |
537 | ||
82a44134 LW |
538 | /** |
539 | * nmk_i2c_xfer_one() - transmit a single I2C message | |
540 | * @dev: device with a message encoded into it | |
541 | * @flags: message flags | |
542 | */ | |
543 | static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) | |
544 | { | |
545 | int status; | |
546 | ||
547 | if (flags & I2C_M_RD) { | |
548 | /* read operation */ | |
549 | dev->cli.operation = I2C_READ; | |
51a0c8d0 | 550 | status = read_i2c(dev, flags); |
82a44134 LW |
551 | } else { |
552 | /* write operation */ | |
553 | dev->cli.operation = I2C_WRITE; | |
51a0c8d0 | 554 | status = write_i2c(dev, flags); |
82a44134 LW |
555 | } |
556 | ||
557 | if (status || (dev->result)) { | |
558 | u32 i2c_sr; | |
559 | u32 cause; | |
560 | ||
561 | i2c_sr = readl(dev->virtbase + I2C_SR); | |
562 | /* | |
563 | * Check if the controller I2C operation status | |
564 | * is set to ABORT(11b). | |
565 | */ | |
566 | if (((i2c_sr >> 2) & 0x3) == 0x3) { | |
567 | /* get the abort cause */ | |
568 | cause = (i2c_sr >> 4) & 0x7; | |
23560214 | 569 | dev_err(&dev->adev->dev, "%s\n", |
8abf6fbb | 570 | cause >= ARRAY_SIZE(abort_causes) ? |
82a44134 LW |
571 | "unknown reason" : |
572 | abort_causes[cause]); | |
573 | } | |
574 | ||
575 | (void) init_hw(dev); | |
576 | ||
577 | status = status ? status : dev->result; | |
578 | } | |
579 | ||
580 | return status; | |
581 | } | |
582 | ||
3f9900f1 | 583 | /** |
584 | * nmk_i2c_xfer() - I2C transfer function used by kernel framework | |
1804edd1 LW |
585 | * @i2c_adap: Adapter pointer to the controller |
586 | * @msgs: Pointer to data to be written. | |
587 | * @num_msgs: Number of messages to be executed | |
3f9900f1 | 588 | * |
589 | * This is the function called by the generic kernel i2c_transfer() | |
590 | * or i2c_smbus...() API calls. Note that this code is protected by the | |
591 | * semaphore set in the kernel i2c_transfer() function. | |
592 | * | |
593 | * NOTE: | |
594 | * READ TRANSFER : We impose a restriction of the first message to be the | |
8abf6fbb JA |
595 | * index message for any read transaction. |
596 | * - a no index is coded as '0', | |
597 | * - 2byte big endian index is coded as '3' | |
598 | * !!! msg[0].buf holds the actual index. | |
599 | * This is compatible with generic messages of smbus emulator | |
600 | * that send a one byte index. | |
601 | * eg. a I2C transation to read 2 bytes from index 0 | |
3f9900f1 | 602 | * idx = 0; |
603 | * msg[0].addr = client->addr; | |
604 | * msg[0].flags = 0x0; | |
605 | * msg[0].len = 1; | |
606 | * msg[0].buf = &idx; | |
607 | * | |
608 | * msg[1].addr = client->addr; | |
609 | * msg[1].flags = I2C_M_RD; | |
610 | * msg[1].len = 2; | |
611 | * msg[1].buf = rd_buff | |
612 | * i2c_transfer(adap, msg, 2); | |
613 | * | |
614 | * WRITE TRANSFER : The I2C standard interface interprets all data as payload. | |
615 | * If you want to emulate an SMBUS write transaction put the | |
616 | * index as first byte(or first and second) in the payload. | |
617 | * eg. a I2C transation to write 2 bytes from index 1 | |
618 | * wr_buff[0] = 0x1; | |
619 | * wr_buff[1] = 0x23; | |
620 | * wr_buff[2] = 0x46; | |
621 | * msg[0].flags = 0x0; | |
622 | * msg[0].len = 3; | |
623 | * msg[0].buf = wr_buff; | |
624 | * i2c_transfer(adap, msg, 1); | |
625 | * | |
626 | * To read or write a block of data (multiple bytes) using SMBUS emulation | |
627 | * please use the i2c_smbus_read_i2c_block_data() | |
628 | * or i2c_smbus_write_i2c_block_data() API | |
629 | */ | |
630 | static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, | |
631 | struct i2c_msg msgs[], int num_msgs) | |
632 | { | |
633 | int status; | |
634 | int i; | |
3f9900f1 | 635 | struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); |
ebd10e07 | 636 | int j; |
3f9900f1 | 637 | |
a20d2394 JA |
638 | dev->busy = true; |
639 | ||
23560214 | 640 | pm_runtime_get_sync(&dev->adev->dev); |
a20d2394 | 641 | |
817315f5 PB |
642 | status = clk_prepare_enable(dev->clk); |
643 | if (status) { | |
644 | dev_err(&dev->adev->dev, "can't prepare_enable clock\n"); | |
645 | goto out_clk; | |
646 | } | |
ebd10e07 | 647 | |
24e9e157 | 648 | /* Optionaly enable pins to be muxed in and configured */ |
ac844b62 | 649 | pinctrl_pm_select_default_state(&dev->adev->dev); |
24e9e157 | 650 | |
3f9900f1 | 651 | status = init_hw(dev); |
652 | if (status) | |
ebd10e07 | 653 | goto out; |
8ef4f4e4 | 654 | |
82a44134 | 655 | /* Attempt three times to send the message queue */ |
ebd10e07 VS |
656 | for (j = 0; j < 3; j++) { |
657 | /* setup the i2c controller */ | |
658 | setup_i2c_controller(dev); | |
3f9900f1 | 659 | |
ebd10e07 | 660 | for (i = 0; i < num_msgs; i++) { |
ebd10e07 VS |
661 | dev->cli.slave_adr = msgs[i].addr; |
662 | dev->cli.buffer = msgs[i].buf; | |
663 | dev->cli.count = msgs[i].len; | |
664 | dev->stop = (i < (num_msgs - 1)) ? 0 : 1; | |
665 | dev->result = 0; | |
666 | ||
82a44134 LW |
667 | status = nmk_i2c_xfer_one(dev, msgs[i].flags); |
668 | if (status != 0) | |
ebd10e07 | 669 | break; |
3f9900f1 | 670 | } |
ebd10e07 VS |
671 | if (status == 0) |
672 | break; | |
3f9900f1 | 673 | } |
a20d2394 JA |
674 | |
675 | out: | |
817315f5 PB |
676 | clk_disable_unprepare(dev->clk); |
677 | out_clk: | |
24e9e157 | 678 | /* Optionally let pins go into idle state */ |
ac844b62 | 679 | pinctrl_pm_select_idle_state(&dev->adev->dev); |
24e9e157 | 680 | |
23560214 | 681 | pm_runtime_put_sync(&dev->adev->dev); |
a20d2394 JA |
682 | |
683 | dev->busy = false; | |
8ef4f4e4 | 684 | |
3f9900f1 | 685 | /* return the no. messages processed */ |
686 | if (status) | |
687 | return status; | |
688 | else | |
689 | return num_msgs; | |
690 | } | |
691 | ||
692 | /** | |
693 | * disable_interrupts() - disable the interrupts | |
694 | * @dev: private data of controller | |
1804edd1 | 695 | * @irq: interrupt number |
3f9900f1 | 696 | */ |
697 | static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) | |
698 | { | |
699 | irq = IRQ_MASK(irq); | |
700 | writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), | |
701 | dev->virtbase + I2C_IMSCR); | |
702 | return 0; | |
703 | } | |
704 | ||
705 | /** | |
706 | * i2c_irq_handler() - interrupt routine | |
707 | * @irq: interrupt number | |
708 | * @arg: data passed to the handler | |
709 | * | |
710 | * This is the interrupt handler for the i2c driver. Currently | |
711 | * it handles the major interrupts like Rx & Tx FIFO management | |
712 | * interrupts, master transaction interrupts, arbitration and | |
713 | * bus error interrupts. The rest of the interrupts are treated as | |
714 | * unhandled. | |
715 | */ | |
716 | static irqreturn_t i2c_irq_handler(int irq, void *arg) | |
717 | { | |
718 | struct nmk_i2c_dev *dev = arg; | |
719 | u32 tft, rft; | |
720 | u32 count; | |
876ae85c | 721 | u32 misr, src; |
3f9900f1 | 722 | |
723 | /* load Tx FIFO and Rx FIFO threshold values */ | |
724 | tft = readl(dev->virtbase + I2C_TFTR); | |
725 | rft = readl(dev->virtbase + I2C_RFTR); | |
726 | ||
727 | /* read interrupt status register */ | |
728 | misr = readl(dev->virtbase + I2C_MISR); | |
729 | ||
730 | src = __ffs(misr); | |
731 | switch ((1 << src)) { | |
732 | ||
733 | /* Transmit FIFO nearly empty interrupt */ | |
734 | case I2C_IT_TXFNE: | |
735 | { | |
736 | if (dev->cli.operation == I2C_READ) { | |
737 | /* | |
738 | * in read operation why do we care for writing? | |
739 | * so disable the Transmit FIFO interrupt | |
740 | */ | |
741 | disable_interrupts(dev, I2C_IT_TXFNE); | |
742 | } else { | |
55355341 | 743 | fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); |
3f9900f1 | 744 | /* |
745 | * if done, close the transfer by disabling the | |
746 | * corresponding TXFNE interrupt | |
747 | */ | |
748 | if (dev->cli.count == 0) | |
749 | disable_interrupts(dev, I2C_IT_TXFNE); | |
750 | } | |
751 | } | |
752 | break; | |
753 | ||
754 | /* | |
755 | * Rx FIFO nearly full interrupt. | |
756 | * This is set when the numer of entries in Rx FIFO is | |
757 | * greater or equal than the threshold value programmed | |
758 | * in RFT | |
759 | */ | |
760 | case I2C_IT_RXFNF: | |
761 | for (count = rft; count > 0; count--) { | |
762 | /* Read the Rx FIFO */ | |
763 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
764 | dev->cli.buffer++; | |
765 | } | |
766 | dev->cli.count -= rft; | |
767 | dev->cli.xfer_bytes += rft; | |
768 | break; | |
769 | ||
770 | /* Rx FIFO full */ | |
771 | case I2C_IT_RXFF: | |
772 | for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { | |
773 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
774 | dev->cli.buffer++; | |
775 | } | |
776 | dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; | |
777 | dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; | |
778 | break; | |
779 | ||
780 | /* Master Transaction Done with/without stop */ | |
781 | case I2C_IT_MTD: | |
782 | case I2C_IT_MTDWS: | |
783 | if (dev->cli.operation == I2C_READ) { | |
1df3ab1b RV |
784 | while (!(readl(dev->virtbase + I2C_RISR) |
785 | & I2C_IT_RXFE)) { | |
3f9900f1 | 786 | if (dev->cli.count == 0) |
787 | break; | |
788 | *dev->cli.buffer = | |
789 | readb(dev->virtbase + I2C_RFR); | |
790 | dev->cli.buffer++; | |
791 | dev->cli.count--; | |
792 | dev->cli.xfer_bytes++; | |
793 | } | |
794 | } | |
795 | ||
b5e890f7 VS |
796 | disable_all_interrupts(dev); |
797 | clear_all_interrupts(dev); | |
3f9900f1 | 798 | |
799 | if (dev->cli.count) { | |
99381bec | 800 | dev->result = -EIO; |
23560214 | 801 | dev_err(&dev->adev->dev, |
8abf6fbb JA |
802 | "%lu bytes still remain to be xfered\n", |
803 | dev->cli.count); | |
3f9900f1 | 804 | (void) init_hw(dev); |
805 | } | |
806 | complete(&dev->xfer_complete); | |
807 | ||
808 | break; | |
809 | ||
810 | /* Master Arbitration lost interrupt */ | |
811 | case I2C_IT_MAL: | |
99381bec | 812 | dev->result = -EIO; |
3f9900f1 | 813 | (void) init_hw(dev); |
814 | ||
815 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); | |
816 | complete(&dev->xfer_complete); | |
817 | ||
818 | break; | |
819 | ||
820 | /* | |
821 | * Bus Error interrupt. | |
822 | * This happens when an unexpected start/stop condition occurs | |
823 | * during the transaction. | |
824 | */ | |
825 | case I2C_IT_BERR: | |
99381bec | 826 | dev->result = -EIO; |
3f9900f1 | 827 | /* get the status */ |
828 | if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) | |
829 | (void) init_hw(dev); | |
830 | ||
831 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); | |
832 | complete(&dev->xfer_complete); | |
833 | ||
834 | break; | |
835 | ||
836 | /* | |
837 | * Tx FIFO overrun interrupt. | |
838 | * This is set when a write operation in Tx FIFO is performed and | |
839 | * the Tx FIFO is full. | |
840 | */ | |
841 | case I2C_IT_TXFOVR: | |
99381bec | 842 | dev->result = -EIO; |
3f9900f1 | 843 | (void) init_hw(dev); |
844 | ||
23560214 | 845 | dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); |
3f9900f1 | 846 | complete(&dev->xfer_complete); |
847 | ||
848 | break; | |
849 | ||
850 | /* unhandled interrupts by this driver - TODO*/ | |
851 | case I2C_IT_TXFE: | |
852 | case I2C_IT_TXFF: | |
853 | case I2C_IT_RXFE: | |
854 | case I2C_IT_RFSR: | |
855 | case I2C_IT_RFSE: | |
856 | case I2C_IT_WTSR: | |
857 | case I2C_IT_STD: | |
23560214 | 858 | dev_err(&dev->adev->dev, "unhandled Interrupt\n"); |
3f9900f1 | 859 | break; |
860 | default: | |
23560214 | 861 | dev_err(&dev->adev->dev, "spurious Interrupt..\n"); |
3f9900f1 | 862 | break; |
863 | } | |
864 | ||
865 | return IRQ_HANDLED; | |
866 | } | |
867 | ||
a20d2394 JA |
868 | |
869 | #ifdef CONFIG_PM | |
b0e751a9 | 870 | static int nmk_i2c_suspend(struct device *dev) |
a20d2394 | 871 | { |
23560214 AR |
872 | struct amba_device *adev = to_amba_device(dev); |
873 | struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); | |
a20d2394 | 874 | |
b0e751a9 | 875 | if (nmk_i2c->busy) |
a20d2394 | 876 | return -EBUSY; |
b0e751a9 | 877 | |
ac844b62 | 878 | pinctrl_pm_select_sleep_state(dev); |
24e9e157 | 879 | |
b0e751a9 RV |
880 | return 0; |
881 | } | |
882 | ||
883 | static int nmk_i2c_resume(struct device *dev) | |
884 | { | |
24e9e157 | 885 | /* First go to the default state */ |
ac844b62 | 886 | pinctrl_pm_select_default_state(dev); |
24e9e157 | 887 | /* Then let's idle the pins until the next transfer happens */ |
ac844b62 LW |
888 | pinctrl_pm_select_idle_state(dev); |
889 | ||
b0e751a9 | 890 | return 0; |
a20d2394 JA |
891 | } |
892 | #else | |
893 | #define nmk_i2c_suspend NULL | |
b0e751a9 | 894 | #define nmk_i2c_resume NULL |
a20d2394 JA |
895 | #endif |
896 | ||
b0e751a9 RV |
897 | /* |
898 | * We use noirq so that we suspend late and resume before the wakeup interrupt | |
899 | * to ensure that we do the !pm_runtime_suspended() check in resume before | |
900 | * there has been a regular pm runtime resume (via pm_runtime_get_sync()). | |
901 | */ | |
902 | static const struct dev_pm_ops nmk_i2c_pm = { | |
903 | .suspend_noirq = nmk_i2c_suspend, | |
904 | .resume_noirq = nmk_i2c_resume, | |
905 | }; | |
906 | ||
3f9900f1 | 907 | static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) |
908 | { | |
51a0c8d0 | 909 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; |
3f9900f1 | 910 | } |
911 | ||
912 | static const struct i2c_algorithm nmk_i2c_algo = { | |
913 | .master_xfer = nmk_i2c_xfer, | |
914 | .functionality = nmk_i2c_functionality | |
915 | }; | |
916 | ||
b007a3ef LJ |
917 | static struct nmk_i2c_controller u8500_i2c = { |
918 | /* | |
919 | * Slave data setup time; 250ns, 100ns, and 10ns, which | |
920 | * is 14, 6 and 2 respectively for a 48Mhz i2c clock. | |
921 | */ | |
922 | .slsu = 0xe, | |
923 | .tft = 1, /* Tx FIFO threshold */ | |
924 | .rft = 8, /* Rx FIFO threshold */ | |
925 | .clk_freq = 400000, /* fast mode operation */ | |
926 | .timeout = 200, /* Slave response timeout(ms) */ | |
927 | .sm = I2C_FREQ_MODE_FAST, | |
928 | }; | |
929 | ||
43fea581 LJ |
930 | static void nmk_i2c_of_probe(struct device_node *np, |
931 | struct nmk_i2c_controller *pdata) | |
932 | { | |
933 | of_property_read_u32(np, "clock-frequency", &pdata->clk_freq); | |
934 | ||
935 | /* This driver only supports 'standard' and 'fast' modes of operation. */ | |
936 | if (pdata->clk_freq <= 100000) | |
937 | pdata->sm = I2C_FREQ_MODE_STANDARD; | |
938 | else | |
939 | pdata->sm = I2C_FREQ_MODE_FAST; | |
940 | } | |
941 | ||
23560214 | 942 | static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) |
3f9900f1 | 943 | { |
944 | int ret = 0; | |
6d4028c6 | 945 | struct nmk_i2c_controller *pdata = dev_get_platdata(&adev->dev); |
43fea581 | 946 | struct device_node *np = adev->dev.of_node; |
3f9900f1 | 947 | struct nmk_i2c_dev *dev; |
948 | struct i2c_adapter *adap; | |
3a205be5 LW |
949 | struct i2c_vendor_data *vendor = id->data; |
950 | u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; | |
3f9900f1 | 951 | |
43fea581 LJ |
952 | if (!pdata) { |
953 | if (np) { | |
954 | pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL); | |
955 | if (!pdata) { | |
956 | ret = -ENOMEM; | |
957 | goto err_no_mem; | |
958 | } | |
959 | /* Provide the default configuration as a base. */ | |
960 | memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller)); | |
961 | nmk_i2c_of_probe(np, pdata); | |
962 | } else | |
963 | /* No i2c configuration found, using the default. */ | |
964 | pdata = &u8500_i2c; | |
965 | } | |
b007a3ef | 966 | |
3a205be5 LW |
967 | if (pdata->tft > max_fifo_threshold) { |
968 | dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n", | |
969 | pdata->tft, max_fifo_threshold); | |
970 | pdata->tft = max_fifo_threshold; | |
971 | } | |
972 | ||
973 | if (pdata->rft > max_fifo_threshold) { | |
974 | dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n", | |
975 | pdata->rft, max_fifo_threshold); | |
976 | pdata->rft = max_fifo_threshold; | |
977 | } | |
978 | ||
3f9900f1 | 979 | dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); |
980 | if (!dev) { | |
23560214 | 981 | dev_err(&adev->dev, "cannot allocate memory\n"); |
3f9900f1 | 982 | ret = -ENOMEM; |
983 | goto err_no_mem; | |
984 | } | |
3a205be5 | 985 | dev->vendor = vendor; |
a20d2394 | 986 | dev->busy = false; |
23560214 AR |
987 | dev->adev = adev; |
988 | amba_set_drvdata(adev, dev); | |
3f9900f1 | 989 | |
ac844b62 LW |
990 | /* Select default pin state */ |
991 | pinctrl_pm_select_default_state(&adev->dev); | |
992 | /* If possible, let's go to idle until the first transfer */ | |
993 | pinctrl_pm_select_idle_state(&adev->dev); | |
24e9e157 | 994 | |
23560214 | 995 | dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
3f9900f1 | 996 | if (!dev->virtbase) { |
997 | ret = -ENOMEM; | |
998 | goto err_no_ioremap; | |
999 | } | |
1000 | ||
23560214 | 1001 | dev->irq = adev->irq[0]; |
4311051c | 1002 | ret = request_irq(dev->irq, i2c_irq_handler, 0, |
3f9900f1 | 1003 | DRIVER_NAME, dev); |
1004 | if (ret) { | |
23560214 | 1005 | dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); |
3f9900f1 | 1006 | goto err_irq; |
1007 | } | |
1008 | ||
23560214 | 1009 | pm_suspend_ignore_children(&adev->dev, true); |
b0e751a9 | 1010 | |
23560214 | 1011 | dev->clk = clk_get(&adev->dev, NULL); |
3f9900f1 | 1012 | if (IS_ERR(dev->clk)) { |
23560214 | 1013 | dev_err(&adev->dev, "could not get i2c clock\n"); |
3f9900f1 | 1014 | ret = PTR_ERR(dev->clk); |
1015 | goto err_no_clk; | |
1016 | } | |
1017 | ||
3f9900f1 | 1018 | adap = &dev->adap; |
43fea581 | 1019 | adap->dev.of_node = np; |
23560214 | 1020 | adap->dev.parent = &adev->dev; |
3f9900f1 | 1021 | adap->owner = THIS_MODULE; |
1022 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1023 | adap->algo = &nmk_i2c_algo; | |
98582d95 | 1024 | adap->timeout = msecs_to_jiffies(pdata->timeout); |
6d779a4c | 1025 | snprintf(adap->name, sizeof(adap->name), |
d15b8575 | 1026 | "Nomadik I2C at %pR", &adev->res); |
3f9900f1 | 1027 | |
1028 | /* fetch the controller configuration from machine */ | |
1029 | dev->cfg.clk_freq = pdata->clk_freq; | |
1030 | dev->cfg.slsu = pdata->slsu; | |
1031 | dev->cfg.tft = pdata->tft; | |
1032 | dev->cfg.rft = pdata->rft; | |
1033 | dev->cfg.sm = pdata->sm; | |
1034 | ||
1035 | i2c_set_adapdata(adap, dev); | |
1036 | ||
23560214 | 1037 | dev_info(&adev->dev, |
8abf6fbb JA |
1038 | "initialize %s on virtual base %p\n", |
1039 | adap->name, dev->virtbase); | |
3f9900f1 | 1040 | |
d15b8575 | 1041 | ret = i2c_add_adapter(adap); |
3f9900f1 | 1042 | if (ret) { |
23560214 | 1043 | dev_err(&adev->dev, "failed to add adapter\n"); |
3f9900f1 | 1044 | goto err_add_adap; |
1045 | } | |
1046 | ||
23560214 AR |
1047 | pm_runtime_put(&adev->dev); |
1048 | ||
3f9900f1 | 1049 | return 0; |
1050 | ||
3f9900f1 | 1051 | err_add_adap: |
1052 | clk_put(dev->clk); | |
1053 | err_no_clk: | |
1054 | free_irq(dev->irq, dev); | |
1055 | err_irq: | |
1056 | iounmap(dev->virtbase); | |
1057 | err_no_ioremap: | |
3f9900f1 | 1058 | kfree(dev); |
1059 | err_no_mem: | |
1060 | ||
1061 | return ret; | |
1062 | } | |
1063 | ||
23560214 | 1064 | static int nmk_i2c_remove(struct amba_device *adev) |
3f9900f1 | 1065 | { |
23560214 AR |
1066 | struct resource *res = &adev->res; |
1067 | struct nmk_i2c_dev *dev = amba_get_drvdata(adev); | |
3f9900f1 | 1068 | |
1069 | i2c_del_adapter(&dev->adap); | |
1070 | flush_i2c_fifo(dev); | |
1071 | disable_all_interrupts(dev); | |
1072 | clear_all_interrupts(dev); | |
1073 | /* disable the controller */ | |
1074 | i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
1075 | free_irq(dev->irq, dev); | |
1076 | iounmap(dev->virtbase); | |
a1c27678 RV |
1077 | if (res) |
1078 | release_mem_region(res->start, resource_size(res)); | |
3f9900f1 | 1079 | clk_put(dev->clk); |
23560214 | 1080 | pm_runtime_disable(&adev->dev); |
3f9900f1 | 1081 | kfree(dev); |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
3a205be5 LW |
1086 | static struct i2c_vendor_data vendor_stn8815 = { |
1087 | .has_mtdws = false, | |
1088 | .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ | |
1089 | }; | |
1090 | ||
1091 | static struct i2c_vendor_data vendor_db8500 = { | |
1092 | .has_mtdws = true, | |
1093 | .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ | |
1094 | }; | |
1095 | ||
23560214 AR |
1096 | static struct amba_id nmk_i2c_ids[] = { |
1097 | { | |
1098 | .id = 0x00180024, | |
1099 | .mask = 0x00ffffff, | |
3a205be5 | 1100 | .data = &vendor_stn8815, |
23560214 AR |
1101 | }, |
1102 | { | |
1103 | .id = 0x00380024, | |
1104 | .mask = 0x00ffffff, | |
3a205be5 | 1105 | .data = &vendor_db8500, |
23560214 AR |
1106 | }, |
1107 | {}, | |
1108 | }; | |
1109 | ||
1110 | MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); | |
1111 | ||
1112 | static struct amba_driver nmk_i2c_driver = { | |
1113 | .drv = { | |
3f9900f1 | 1114 | .owner = THIS_MODULE, |
1115 | .name = DRIVER_NAME, | |
b0e751a9 | 1116 | .pm = &nmk_i2c_pm, |
3f9900f1 | 1117 | }, |
23560214 | 1118 | .id_table = nmk_i2c_ids, |
3f9900f1 | 1119 | .probe = nmk_i2c_probe, |
23560214 | 1120 | .remove = nmk_i2c_remove, |
3f9900f1 | 1121 | }; |
1122 | ||
1123 | static int __init nmk_i2c_init(void) | |
1124 | { | |
23560214 | 1125 | return amba_driver_register(&nmk_i2c_driver); |
3f9900f1 | 1126 | } |
1127 | ||
1128 | static void __exit nmk_i2c_exit(void) | |
1129 | { | |
23560214 | 1130 | amba_driver_unregister(&nmk_i2c_driver); |
3f9900f1 | 1131 | } |
1132 | ||
1133 | subsys_initcall(nmk_i2c_init); | |
1134 | module_exit(nmk_i2c_exit); | |
1135 | ||
1136 | MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); | |
1137 | MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); | |
1138 | MODULE_LICENSE("GPL"); |