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3f9900f1 | 1 | /* |
1804edd1 | 2 | * Copyright (C) 2009 ST-Ericsson SA |
3f9900f1 | 3 | * Copyright (C) 2009 STMicroelectronics |
4 | * | |
5 | * I2C master mode controller driver, used in Nomadik 8815 | |
6 | * and Ux500 platforms. | |
7 | * | |
8 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
9 | * Author: Sachin Verma <sachin.verma@st.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2, as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
3f9900f1 | 19 | #include <linux/interrupt.h> |
20 | #include <linux/i2c.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
a20d2394 | 24 | #include <linux/regulator/consumer.h> |
b0e751a9 | 25 | #include <linux/pm_runtime.h> |
3f9900f1 | 26 | |
27 | #include <plat/i2c.h> | |
28 | ||
29 | #define DRIVER_NAME "nmk-i2c" | |
30 | ||
31 | /* I2C Controller register offsets */ | |
32 | #define I2C_CR (0x000) | |
33 | #define I2C_SCR (0x004) | |
34 | #define I2C_HSMCR (0x008) | |
35 | #define I2C_MCR (0x00C) | |
36 | #define I2C_TFR (0x010) | |
37 | #define I2C_SR (0x014) | |
38 | #define I2C_RFR (0x018) | |
39 | #define I2C_TFTR (0x01C) | |
40 | #define I2C_RFTR (0x020) | |
41 | #define I2C_DMAR (0x024) | |
42 | #define I2C_BRCR (0x028) | |
43 | #define I2C_IMSCR (0x02C) | |
44 | #define I2C_RISR (0x030) | |
45 | #define I2C_MISR (0x034) | |
46 | #define I2C_ICR (0x038) | |
47 | ||
48 | /* Control registers */ | |
49 | #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ | |
50 | #define I2C_CR_OM (0x3 << 1) /* Operating mode */ | |
51 | #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ | |
52 | #define I2C_CR_SM (0x3 << 4) /* Speed mode */ | |
53 | #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ | |
54 | #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ | |
55 | #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ | |
56 | #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ | |
57 | #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ | |
58 | #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ | |
59 | #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ | |
60 | #define I2C_CR_FON (0x3 << 13) /* Filtering on */ | |
61 | #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ | |
62 | ||
63 | /* Master controller (MCR) register */ | |
64 | #define I2C_MCR_OP (0x1 << 0) /* Operation */ | |
65 | #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ | |
66 | #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ | |
67 | #define I2C_MCR_SB (0x1 << 11) /* Extended address */ | |
68 | #define I2C_MCR_AM (0x3 << 12) /* Address type */ | |
69 | #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ | |
70 | #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ | |
71 | ||
72 | /* Status register (SR) */ | |
73 | #define I2C_SR_OP (0x3 << 0) /* Operation */ | |
74 | #define I2C_SR_STATUS (0x3 << 2) /* controller status */ | |
75 | #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ | |
76 | #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ | |
77 | #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ | |
78 | ||
79 | /* Interrupt mask set/clear (IMSCR) bits */ | |
80 | #define I2C_IT_TXFE (0x1 << 0) | |
81 | #define I2C_IT_TXFNE (0x1 << 1) | |
82 | #define I2C_IT_TXFF (0x1 << 2) | |
83 | #define I2C_IT_TXFOVR (0x1 << 3) | |
84 | #define I2C_IT_RXFE (0x1 << 4) | |
85 | #define I2C_IT_RXFNF (0x1 << 5) | |
86 | #define I2C_IT_RXFF (0x1 << 6) | |
87 | #define I2C_IT_RFSR (0x1 << 16) | |
88 | #define I2C_IT_RFSE (0x1 << 17) | |
89 | #define I2C_IT_WTSR (0x1 << 18) | |
90 | #define I2C_IT_MTD (0x1 << 19) | |
91 | #define I2C_IT_STD (0x1 << 20) | |
92 | #define I2C_IT_MAL (0x1 << 24) | |
93 | #define I2C_IT_BERR (0x1 << 25) | |
94 | #define I2C_IT_MTDWS (0x1 << 28) | |
95 | ||
96 | #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) | |
97 | ||
98 | /* some bits in ICR are reserved */ | |
99 | #define I2C_CLEAR_ALL_INTS 0x131f007f | |
100 | ||
101 | /* first three msb bits are reserved */ | |
102 | #define IRQ_MASK(mask) (mask & 0x1fffffff) | |
103 | ||
104 | /* maximum threshold value */ | |
105 | #define MAX_I2C_FIFO_THRESHOLD 15 | |
106 | ||
107 | enum i2c_status { | |
108 | I2C_NOP, | |
109 | I2C_ON_GOING, | |
110 | I2C_OK, | |
111 | I2C_ABORT | |
112 | }; | |
113 | ||
114 | /* operation */ | |
115 | enum i2c_operation { | |
116 | I2C_NO_OPERATION = 0xff, | |
117 | I2C_WRITE = 0x00, | |
118 | I2C_READ = 0x01 | |
119 | }; | |
120 | ||
3f9900f1 | 121 | /** |
122 | * struct i2c_nmk_client - client specific data | |
123 | * @slave_adr: 7-bit slave address | |
25985edc | 124 | * @count: no. bytes to be transferred |
3f9900f1 | 125 | * @buffer: client data buffer |
25985edc | 126 | * @xfer_bytes: bytes transferred till now |
3f9900f1 | 127 | * @operation: current I2C operation |
128 | */ | |
129 | struct i2c_nmk_client { | |
130 | unsigned short slave_adr; | |
131 | unsigned long count; | |
132 | unsigned char *buffer; | |
133 | unsigned long xfer_bytes; | |
134 | enum i2c_operation operation; | |
135 | }; | |
136 | ||
137 | /** | |
138 | * struct nmk_i2c_dev - private data structure of the controller | |
139 | * @pdev: parent platform device | |
140 | * @adap: corresponding I2C adapter | |
141 | * @irq: interrupt line for the controller | |
142 | * @virtbase: virtual io memory area | |
143 | * @clk: hardware i2c block clock | |
144 | * @cfg: machine provided controller configuration | |
145 | * @cli: holder of client specific data | |
146 | * @stop: stop condition | |
147 | * @xfer_complete: acknowledge completion for a I2C message | |
148 | * @result: controller propogated result | |
a20d2394 | 149 | * @busy: Busy doing transfer |
3f9900f1 | 150 | */ |
151 | struct nmk_i2c_dev { | |
152 | struct platform_device *pdev; | |
153 | struct i2c_adapter adap; | |
154 | int irq; | |
155 | void __iomem *virtbase; | |
156 | struct clk *clk; | |
157 | struct nmk_i2c_controller cfg; | |
158 | struct i2c_nmk_client cli; | |
159 | int stop; | |
160 | struct completion xfer_complete; | |
161 | int result; | |
a20d2394 JA |
162 | struct regulator *regulator; |
163 | bool busy; | |
3f9900f1 | 164 | }; |
165 | ||
166 | /* controller's abort causes */ | |
167 | static const char *abort_causes[] = { | |
168 | "no ack received after address transmission", | |
169 | "no ack received during data phase", | |
170 | "ack received after xmission of master code", | |
171 | "master lost arbitration", | |
172 | "slave restarts", | |
173 | "slave reset", | |
174 | "overflow, maxsize is 2047 bytes", | |
175 | }; | |
176 | ||
177 | static inline void i2c_set_bit(void __iomem *reg, u32 mask) | |
178 | { | |
179 | writel(readl(reg) | mask, reg); | |
180 | } | |
181 | ||
182 | static inline void i2c_clr_bit(void __iomem *reg, u32 mask) | |
183 | { | |
184 | writel(readl(reg) & ~mask, reg); | |
185 | } | |
186 | ||
187 | /** | |
188 | * flush_i2c_fifo() - This function flushes the I2C FIFO | |
189 | * @dev: private data of I2C Driver | |
190 | * | |
191 | * This function flushes the I2C Tx and Rx FIFOs. It returns | |
192 | * 0 on successful flushing of FIFO | |
193 | */ | |
194 | static int flush_i2c_fifo(struct nmk_i2c_dev *dev) | |
195 | { | |
196 | #define LOOP_ATTEMPTS 10 | |
197 | int i; | |
198 | unsigned long timeout; | |
199 | ||
200 | /* | |
201 | * flush the transmit and receive FIFO. The flushing | |
202 | * operation takes several cycles before to be completed. | |
203 | * On the completion, the I2C internal logic clears these | |
204 | * bits, until then no one must access Tx, Rx FIFO and | |
205 | * should poll on these bits waiting for the completion. | |
206 | */ | |
207 | writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); | |
208 | ||
209 | for (i = 0; i < LOOP_ATTEMPTS; i++) { | |
cd20e4fa | 210 | timeout = jiffies + dev->adap.timeout; |
3f9900f1 | 211 | |
212 | while (!time_after(jiffies, timeout)) { | |
213 | if ((readl(dev->virtbase + I2C_CR) & | |
214 | (I2C_CR_FTX | I2C_CR_FRX)) == 0) | |
215 | return 0; | |
216 | } | |
217 | } | |
218 | ||
219 | dev_err(&dev->pdev->dev, "flushing operation timed out " | |
220 | "giving up after %d attempts", LOOP_ATTEMPTS); | |
221 | ||
222 | return -ETIMEDOUT; | |
223 | } | |
224 | ||
225 | /** | |
226 | * disable_all_interrupts() - Disable all interrupts of this I2c Bus | |
227 | * @dev: private data of I2C Driver | |
228 | */ | |
229 | static void disable_all_interrupts(struct nmk_i2c_dev *dev) | |
230 | { | |
231 | u32 mask = IRQ_MASK(0); | |
232 | writel(mask, dev->virtbase + I2C_IMSCR); | |
233 | } | |
234 | ||
235 | /** | |
236 | * clear_all_interrupts() - Clear all interrupts of I2C Controller | |
237 | * @dev: private data of I2C Driver | |
238 | */ | |
239 | static void clear_all_interrupts(struct nmk_i2c_dev *dev) | |
240 | { | |
241 | u32 mask; | |
242 | mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); | |
243 | writel(mask, dev->virtbase + I2C_ICR); | |
244 | } | |
245 | ||
246 | /** | |
247 | * init_hw() - initialize the I2C hardware | |
248 | * @dev: private data of I2C Driver | |
249 | */ | |
250 | static int init_hw(struct nmk_i2c_dev *dev) | |
251 | { | |
252 | int stat; | |
253 | ||
254 | stat = flush_i2c_fifo(dev); | |
255 | if (stat) | |
a20d2394 | 256 | goto exit; |
3f9900f1 | 257 | |
258 | /* disable the controller */ | |
259 | i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
260 | ||
261 | disable_all_interrupts(dev); | |
262 | ||
263 | clear_all_interrupts(dev); | |
264 | ||
265 | dev->cli.operation = I2C_NO_OPERATION; | |
266 | ||
a20d2394 | 267 | exit: |
a20d2394 | 268 | return stat; |
3f9900f1 | 269 | } |
270 | ||
271 | /* enable peripheral, master mode operation */ | |
272 | #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) | |
273 | ||
274 | /** | |
275 | * load_i2c_mcr_reg() - load the MCR register | |
276 | * @dev: private data of controller | |
277 | */ | |
278 | static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev) | |
279 | { | |
280 | u32 mcr = 0; | |
281 | ||
282 | /* 7-bit address transaction */ | |
283 | mcr |= GEN_MASK(1, I2C_MCR_AM, 12); | |
284 | mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); | |
285 | ||
286 | /* start byte procedure not applied */ | |
287 | mcr |= GEN_MASK(0, I2C_MCR_SB, 11); | |
288 | ||
289 | /* check the operation, master read/write? */ | |
290 | if (dev->cli.operation == I2C_WRITE) | |
291 | mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); | |
292 | else | |
293 | mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); | |
294 | ||
295 | /* stop or repeated start? */ | |
296 | if (dev->stop) | |
297 | mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); | |
298 | else | |
299 | mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); | |
300 | ||
301 | mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); | |
302 | ||
303 | return mcr; | |
304 | } | |
305 | ||
306 | /** | |
307 | * setup_i2c_controller() - setup the controller | |
308 | * @dev: private data of controller | |
309 | */ | |
310 | static void setup_i2c_controller(struct nmk_i2c_dev *dev) | |
311 | { | |
312 | u32 brcr1, brcr2; | |
313 | u32 i2c_clk, div; | |
314 | ||
315 | writel(0x0, dev->virtbase + I2C_CR); | |
316 | writel(0x0, dev->virtbase + I2C_HSMCR); | |
317 | writel(0x0, dev->virtbase + I2C_TFTR); | |
318 | writel(0x0, dev->virtbase + I2C_RFTR); | |
319 | writel(0x0, dev->virtbase + I2C_DMAR); | |
320 | ||
321 | /* | |
322 | * set the slsu: | |
323 | * | |
324 | * slsu defines the data setup time after SCL clock | |
325 | * stretching in terms of i2c clk cycles. The | |
326 | * needed setup time for the three modes are 250ns, | |
25985edc | 327 | * 100ns, 10ns respectively thus leading to the values |
3f9900f1 | 328 | * of 14, 6, 2 for a 48 MHz i2c clk. |
329 | */ | |
330 | writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); | |
331 | ||
332 | i2c_clk = clk_get_rate(dev->clk); | |
333 | ||
334 | /* fallback to std. mode if machine has not provided it */ | |
335 | if (dev->cfg.clk_freq == 0) | |
336 | dev->cfg.clk_freq = 100000; | |
337 | ||
338 | /* | |
339 | * The spec says, in case of std. mode the divider is | |
340 | * 2 whereas it is 3 for fast and fastplus mode of | |
341 | * operation. TODO - high speed support. | |
342 | */ | |
343 | div = (dev->cfg.clk_freq > 100000) ? 3 : 2; | |
344 | ||
345 | /* | |
346 | * generate the mask for baud rate counters. The controller | |
347 | * has two baud rate counters. One is used for High speed | |
348 | * operation, and the other is for std, fast mode, fast mode | |
349 | * plus operation. Currently we do not supprt high speed mode | |
350 | * so set brcr1 to 0. | |
351 | */ | |
352 | brcr1 = 0 << 16; | |
353 | brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; | |
354 | ||
355 | /* set the baud rate counter register */ | |
356 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
357 | ||
358 | /* | |
359 | * set the speed mode. Currently we support | |
360 | * only standard and fast mode of operation | |
25985edc | 361 | * TODO - support for fast mode plus (up to 1Mb/s) |
3f9900f1 | 362 | * and high speed (up to 3.4 Mb/s) |
363 | */ | |
364 | if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { | |
365 | dev_err(&dev->pdev->dev, "do not support this mode " | |
366 | "defaulting to std. mode\n"); | |
367 | brcr2 = i2c_clk/(100000 * 2) & 0xffff; | |
368 | writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); | |
369 | writel(I2C_FREQ_MODE_STANDARD << 4, | |
370 | dev->virtbase + I2C_CR); | |
371 | } | |
372 | writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); | |
373 | ||
374 | /* set the Tx and Rx FIFO threshold */ | |
375 | writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); | |
376 | writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); | |
377 | } | |
378 | ||
379 | /** | |
380 | * read_i2c() - Read from I2C client device | |
381 | * @dev: private data of I2C Driver | |
382 | * | |
383 | * This function reads from i2c client device when controller is in | |
384 | * master mode. There is a completion timeout. If there is no transfer | |
385 | * before timeout error is returned. | |
386 | */ | |
387 | static int read_i2c(struct nmk_i2c_dev *dev) | |
388 | { | |
389 | u32 status = 0; | |
390 | u32 mcr; | |
391 | u32 irq_mask = 0; | |
392 | int timeout; | |
393 | ||
394 | mcr = load_i2c_mcr_reg(dev); | |
395 | writel(mcr, dev->virtbase + I2C_MCR); | |
396 | ||
397 | /* load the current CR value */ | |
398 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
399 | dev->virtbase + I2C_CR); | |
400 | ||
401 | /* enable the controller */ | |
402 | i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
403 | ||
404 | init_completion(&dev->xfer_complete); | |
405 | ||
406 | /* enable interrupts by setting the mask */ | |
407 | irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | | |
408 | I2C_IT_MAL | I2C_IT_BERR); | |
409 | ||
410 | if (dev->stop) | |
411 | irq_mask |= I2C_IT_MTD; | |
412 | else | |
413 | irq_mask |= I2C_IT_MTDWS; | |
414 | ||
415 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
416 | ||
417 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
418 | dev->virtbase + I2C_IMSCR); | |
419 | ||
420 | timeout = wait_for_completion_interruptible_timeout( | |
cd20e4fa | 421 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 422 | |
423 | if (timeout < 0) { | |
424 | dev_err(&dev->pdev->dev, | |
425 | "wait_for_completion_interruptible_timeout" | |
426 | "returned %d waiting for event\n", timeout); | |
427 | status = timeout; | |
428 | } | |
429 | ||
430 | if (timeout == 0) { | |
b595076a | 431 | /* controller has timedout, re-init the h/w */ |
4cb3f538 VS |
432 | dev_err(&dev->pdev->dev, "read from slave 0x%x timed out\n", |
433 | dev->cli.slave_adr); | |
3f9900f1 | 434 | (void) init_hw(dev); |
435 | status = -ETIMEDOUT; | |
436 | } | |
3f9900f1 | 437 | return status; |
438 | } | |
439 | ||
55355341 VS |
440 | static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) |
441 | { | |
442 | int count; | |
443 | ||
444 | for (count = (no_bytes - 2); | |
445 | (count > 0) && | |
446 | (dev->cli.count != 0); | |
447 | count--) { | |
448 | /* write to the Tx FIFO */ | |
449 | writeb(*dev->cli.buffer, | |
450 | dev->virtbase + I2C_TFR); | |
451 | dev->cli.buffer++; | |
452 | dev->cli.count--; | |
453 | dev->cli.xfer_bytes++; | |
454 | } | |
455 | ||
456 | } | |
457 | ||
3f9900f1 | 458 | /** |
459 | * write_i2c() - Write data to I2C client. | |
460 | * @dev: private data of I2C Driver | |
461 | * | |
462 | * This function writes data to I2C client | |
463 | */ | |
464 | static int write_i2c(struct nmk_i2c_dev *dev) | |
465 | { | |
466 | u32 status = 0; | |
467 | u32 mcr; | |
468 | u32 irq_mask = 0; | |
469 | int timeout; | |
470 | ||
471 | mcr = load_i2c_mcr_reg(dev); | |
472 | ||
473 | writel(mcr, dev->virtbase + I2C_MCR); | |
474 | ||
475 | /* load the current CR value */ | |
476 | writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, | |
477 | dev->virtbase + I2C_CR); | |
478 | ||
479 | /* enable the controller */ | |
480 | i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); | |
481 | ||
482 | init_completion(&dev->xfer_complete); | |
483 | ||
484 | /* enable interrupts by settings the masks */ | |
55355341 VS |
485 | irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); |
486 | ||
487 | /* Fill the TX FIFO with transmit data */ | |
488 | fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); | |
489 | ||
490 | if (dev->cli.count != 0) | |
491 | irq_mask |= I2C_IT_TXFNE; | |
3f9900f1 | 492 | |
493 | /* | |
494 | * check if we want to transfer a single or multiple bytes, if so | |
495 | * set the MTDWS bit (Master Transaction Done Without Stop) | |
496 | * to start repeated start operation | |
497 | */ | |
498 | if (dev->stop) | |
499 | irq_mask |= I2C_IT_MTD; | |
500 | else | |
501 | irq_mask |= I2C_IT_MTDWS; | |
502 | ||
503 | irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); | |
504 | ||
505 | writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, | |
506 | dev->virtbase + I2C_IMSCR); | |
507 | ||
508 | timeout = wait_for_completion_interruptible_timeout( | |
cd20e4fa | 509 | &dev->xfer_complete, dev->adap.timeout); |
3f9900f1 | 510 | |
511 | if (timeout < 0) { | |
512 | dev_err(&dev->pdev->dev, | |
513 | "wait_for_completion_interruptible_timeout" | |
514 | "returned %d waiting for event\n", timeout); | |
515 | status = timeout; | |
516 | } | |
517 | ||
518 | if (timeout == 0) { | |
b595076a | 519 | /* controller has timedout, re-init the h/w */ |
4cb3f538 VS |
520 | dev_err(&dev->pdev->dev, "write to slave 0x%x timed out\n", |
521 | dev->cli.slave_adr); | |
3f9900f1 | 522 | (void) init_hw(dev); |
523 | status = -ETIMEDOUT; | |
524 | } | |
525 | ||
526 | return status; | |
527 | } | |
528 | ||
529 | /** | |
530 | * nmk_i2c_xfer() - I2C transfer function used by kernel framework | |
1804edd1 LW |
531 | * @i2c_adap: Adapter pointer to the controller |
532 | * @msgs: Pointer to data to be written. | |
533 | * @num_msgs: Number of messages to be executed | |
3f9900f1 | 534 | * |
535 | * This is the function called by the generic kernel i2c_transfer() | |
536 | * or i2c_smbus...() API calls. Note that this code is protected by the | |
537 | * semaphore set in the kernel i2c_transfer() function. | |
538 | * | |
539 | * NOTE: | |
540 | * READ TRANSFER : We impose a restriction of the first message to be the | |
541 | * index message for any read transaction. | |
542 | * - a no index is coded as '0', | |
543 | * - 2byte big endian index is coded as '3' | |
544 | * !!! msg[0].buf holds the actual index. | |
545 | * This is compatible with generic messages of smbus emulator | |
546 | * that send a one byte index. | |
547 | * eg. a I2C transation to read 2 bytes from index 0 | |
548 | * idx = 0; | |
549 | * msg[0].addr = client->addr; | |
550 | * msg[0].flags = 0x0; | |
551 | * msg[0].len = 1; | |
552 | * msg[0].buf = &idx; | |
553 | * | |
554 | * msg[1].addr = client->addr; | |
555 | * msg[1].flags = I2C_M_RD; | |
556 | * msg[1].len = 2; | |
557 | * msg[1].buf = rd_buff | |
558 | * i2c_transfer(adap, msg, 2); | |
559 | * | |
560 | * WRITE TRANSFER : The I2C standard interface interprets all data as payload. | |
561 | * If you want to emulate an SMBUS write transaction put the | |
562 | * index as first byte(or first and second) in the payload. | |
563 | * eg. a I2C transation to write 2 bytes from index 1 | |
564 | * wr_buff[0] = 0x1; | |
565 | * wr_buff[1] = 0x23; | |
566 | * wr_buff[2] = 0x46; | |
567 | * msg[0].flags = 0x0; | |
568 | * msg[0].len = 3; | |
569 | * msg[0].buf = wr_buff; | |
570 | * i2c_transfer(adap, msg, 1); | |
571 | * | |
572 | * To read or write a block of data (multiple bytes) using SMBUS emulation | |
573 | * please use the i2c_smbus_read_i2c_block_data() | |
574 | * or i2c_smbus_write_i2c_block_data() API | |
575 | */ | |
576 | static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, | |
577 | struct i2c_msg msgs[], int num_msgs) | |
578 | { | |
579 | int status; | |
580 | int i; | |
581 | u32 cause; | |
582 | struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); | |
4cb3f538 | 583 | u32 i2c_sr; |
ebd10e07 | 584 | int j; |
3f9900f1 | 585 | |
a20d2394 JA |
586 | dev->busy = true; |
587 | ||
588 | if (dev->regulator) | |
589 | regulator_enable(dev->regulator); | |
b0e751a9 | 590 | pm_runtime_get_sync(&dev->pdev->dev); |
a20d2394 | 591 | |
ebd10e07 VS |
592 | clk_enable(dev->clk); |
593 | ||
3f9900f1 | 594 | status = init_hw(dev); |
595 | if (status) | |
ebd10e07 | 596 | goto out; |
8ef4f4e4 | 597 | |
ebd10e07 VS |
598 | for (j = 0; j < 3; j++) { |
599 | /* setup the i2c controller */ | |
600 | setup_i2c_controller(dev); | |
3f9900f1 | 601 | |
ebd10e07 VS |
602 | for (i = 0; i < num_msgs; i++) { |
603 | if (unlikely(msgs[i].flags & I2C_M_TEN)) { | |
604 | dev_err(&dev->pdev->dev, "10 bit addressing" | |
605 | "not supported\n"); | |
a20d2394 | 606 | |
ebd10e07 VS |
607 | status = -EINVAL; |
608 | goto out; | |
609 | } | |
610 | dev->cli.slave_adr = msgs[i].addr; | |
611 | dev->cli.buffer = msgs[i].buf; | |
612 | dev->cli.count = msgs[i].len; | |
613 | dev->stop = (i < (num_msgs - 1)) ? 0 : 1; | |
614 | dev->result = 0; | |
615 | ||
616 | if (msgs[i].flags & I2C_M_RD) { | |
617 | /* it is a read operation */ | |
618 | dev->cli.operation = I2C_READ; | |
619 | status = read_i2c(dev); | |
620 | } else { | |
621 | /* write operation */ | |
622 | dev->cli.operation = I2C_WRITE; | |
623 | status = write_i2c(dev); | |
624 | } | |
625 | if (status || (dev->result)) { | |
626 | i2c_sr = readl(dev->virtbase + I2C_SR); | |
627 | /* | |
628 | * Check if the controller I2C operation status | |
629 | * is set to ABORT(11b). | |
630 | */ | |
631 | if (((i2c_sr >> 2) & 0x3) == 0x3) { | |
632 | /* get the abort cause */ | |
633 | cause = (i2c_sr >> 4) | |
634 | & 0x7; | |
635 | dev_err(&dev->pdev->dev, "%s\n", cause | |
636 | >= ARRAY_SIZE(abort_causes) ? | |
4cb3f538 VS |
637 | "unknown reason" : |
638 | abort_causes[cause]); | |
ebd10e07 VS |
639 | } |
640 | ||
641 | status = status ? status : dev->result; | |
a20d2394 | 642 | |
ebd10e07 VS |
643 | break; |
644 | } | |
3f9900f1 | 645 | } |
ebd10e07 VS |
646 | if (status == 0) |
647 | break; | |
3f9900f1 | 648 | } |
a20d2394 JA |
649 | |
650 | out: | |
8ef4f4e4 | 651 | clk_disable(dev->clk); |
b0e751a9 | 652 | pm_runtime_put_sync(&dev->pdev->dev); |
a20d2394 JA |
653 | if (dev->regulator) |
654 | regulator_disable(dev->regulator); | |
655 | ||
656 | dev->busy = false; | |
8ef4f4e4 | 657 | |
3f9900f1 | 658 | /* return the no. messages processed */ |
659 | if (status) | |
660 | return status; | |
661 | else | |
662 | return num_msgs; | |
663 | } | |
664 | ||
665 | /** | |
666 | * disable_interrupts() - disable the interrupts | |
667 | * @dev: private data of controller | |
1804edd1 | 668 | * @irq: interrupt number |
3f9900f1 | 669 | */ |
670 | static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) | |
671 | { | |
672 | irq = IRQ_MASK(irq); | |
673 | writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), | |
674 | dev->virtbase + I2C_IMSCR); | |
675 | return 0; | |
676 | } | |
677 | ||
678 | /** | |
679 | * i2c_irq_handler() - interrupt routine | |
680 | * @irq: interrupt number | |
681 | * @arg: data passed to the handler | |
682 | * | |
683 | * This is the interrupt handler for the i2c driver. Currently | |
684 | * it handles the major interrupts like Rx & Tx FIFO management | |
685 | * interrupts, master transaction interrupts, arbitration and | |
686 | * bus error interrupts. The rest of the interrupts are treated as | |
687 | * unhandled. | |
688 | */ | |
689 | static irqreturn_t i2c_irq_handler(int irq, void *arg) | |
690 | { | |
691 | struct nmk_i2c_dev *dev = arg; | |
692 | u32 tft, rft; | |
693 | u32 count; | |
694 | u32 misr; | |
695 | u32 src = 0; | |
696 | ||
697 | /* load Tx FIFO and Rx FIFO threshold values */ | |
698 | tft = readl(dev->virtbase + I2C_TFTR); | |
699 | rft = readl(dev->virtbase + I2C_RFTR); | |
700 | ||
701 | /* read interrupt status register */ | |
702 | misr = readl(dev->virtbase + I2C_MISR); | |
703 | ||
704 | src = __ffs(misr); | |
705 | switch ((1 << src)) { | |
706 | ||
707 | /* Transmit FIFO nearly empty interrupt */ | |
708 | case I2C_IT_TXFNE: | |
709 | { | |
710 | if (dev->cli.operation == I2C_READ) { | |
711 | /* | |
712 | * in read operation why do we care for writing? | |
713 | * so disable the Transmit FIFO interrupt | |
714 | */ | |
715 | disable_interrupts(dev, I2C_IT_TXFNE); | |
716 | } else { | |
55355341 | 717 | fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); |
3f9900f1 | 718 | /* |
719 | * if done, close the transfer by disabling the | |
720 | * corresponding TXFNE interrupt | |
721 | */ | |
722 | if (dev->cli.count == 0) | |
723 | disable_interrupts(dev, I2C_IT_TXFNE); | |
724 | } | |
725 | } | |
726 | break; | |
727 | ||
728 | /* | |
729 | * Rx FIFO nearly full interrupt. | |
730 | * This is set when the numer of entries in Rx FIFO is | |
731 | * greater or equal than the threshold value programmed | |
732 | * in RFT | |
733 | */ | |
734 | case I2C_IT_RXFNF: | |
735 | for (count = rft; count > 0; count--) { | |
736 | /* Read the Rx FIFO */ | |
737 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
738 | dev->cli.buffer++; | |
739 | } | |
740 | dev->cli.count -= rft; | |
741 | dev->cli.xfer_bytes += rft; | |
742 | break; | |
743 | ||
744 | /* Rx FIFO full */ | |
745 | case I2C_IT_RXFF: | |
746 | for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { | |
747 | *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); | |
748 | dev->cli.buffer++; | |
749 | } | |
750 | dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; | |
751 | dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; | |
752 | break; | |
753 | ||
754 | /* Master Transaction Done with/without stop */ | |
755 | case I2C_IT_MTD: | |
756 | case I2C_IT_MTDWS: | |
757 | if (dev->cli.operation == I2C_READ) { | |
1df3ab1b RV |
758 | while (!(readl(dev->virtbase + I2C_RISR) |
759 | & I2C_IT_RXFE)) { | |
3f9900f1 | 760 | if (dev->cli.count == 0) |
761 | break; | |
762 | *dev->cli.buffer = | |
763 | readb(dev->virtbase + I2C_RFR); | |
764 | dev->cli.buffer++; | |
765 | dev->cli.count--; | |
766 | dev->cli.xfer_bytes++; | |
767 | } | |
768 | } | |
769 | ||
b5e890f7 VS |
770 | disable_all_interrupts(dev); |
771 | clear_all_interrupts(dev); | |
3f9900f1 | 772 | |
773 | if (dev->cli.count) { | |
99381bec | 774 | dev->result = -EIO; |
3f9900f1 | 775 | dev_err(&dev->pdev->dev, "%lu bytes still remain to be" |
776 | "xfered\n", dev->cli.count); | |
777 | (void) init_hw(dev); | |
778 | } | |
779 | complete(&dev->xfer_complete); | |
780 | ||
781 | break; | |
782 | ||
783 | /* Master Arbitration lost interrupt */ | |
784 | case I2C_IT_MAL: | |
99381bec | 785 | dev->result = -EIO; |
3f9900f1 | 786 | (void) init_hw(dev); |
787 | ||
788 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); | |
789 | complete(&dev->xfer_complete); | |
790 | ||
791 | break; | |
792 | ||
793 | /* | |
794 | * Bus Error interrupt. | |
795 | * This happens when an unexpected start/stop condition occurs | |
796 | * during the transaction. | |
797 | */ | |
798 | case I2C_IT_BERR: | |
99381bec | 799 | dev->result = -EIO; |
3f9900f1 | 800 | /* get the status */ |
801 | if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) | |
802 | (void) init_hw(dev); | |
803 | ||
804 | i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); | |
805 | complete(&dev->xfer_complete); | |
806 | ||
807 | break; | |
808 | ||
809 | /* | |
810 | * Tx FIFO overrun interrupt. | |
811 | * This is set when a write operation in Tx FIFO is performed and | |
812 | * the Tx FIFO is full. | |
813 | */ | |
814 | case I2C_IT_TXFOVR: | |
99381bec | 815 | dev->result = -EIO; |
3f9900f1 | 816 | (void) init_hw(dev); |
817 | ||
818 | dev_err(&dev->pdev->dev, "Tx Fifo Over run\n"); | |
819 | complete(&dev->xfer_complete); | |
820 | ||
821 | break; | |
822 | ||
823 | /* unhandled interrupts by this driver - TODO*/ | |
824 | case I2C_IT_TXFE: | |
825 | case I2C_IT_TXFF: | |
826 | case I2C_IT_RXFE: | |
827 | case I2C_IT_RFSR: | |
828 | case I2C_IT_RFSE: | |
829 | case I2C_IT_WTSR: | |
830 | case I2C_IT_STD: | |
831 | dev_err(&dev->pdev->dev, "unhandled Interrupt\n"); | |
832 | break; | |
833 | default: | |
834 | dev_err(&dev->pdev->dev, "spurious Interrupt..\n"); | |
835 | break; | |
836 | } | |
837 | ||
838 | return IRQ_HANDLED; | |
839 | } | |
840 | ||
a20d2394 JA |
841 | |
842 | #ifdef CONFIG_PM | |
b0e751a9 | 843 | static int nmk_i2c_suspend(struct device *dev) |
a20d2394 | 844 | { |
b0e751a9 RV |
845 | struct platform_device *pdev = to_platform_device(dev); |
846 | struct nmk_i2c_dev *nmk_i2c = platform_get_drvdata(pdev); | |
a20d2394 | 847 | |
b0e751a9 | 848 | if (nmk_i2c->busy) |
a20d2394 | 849 | return -EBUSY; |
b0e751a9 RV |
850 | |
851 | return 0; | |
852 | } | |
853 | ||
854 | static int nmk_i2c_resume(struct device *dev) | |
855 | { | |
856 | return 0; | |
a20d2394 JA |
857 | } |
858 | #else | |
859 | #define nmk_i2c_suspend NULL | |
b0e751a9 | 860 | #define nmk_i2c_resume NULL |
a20d2394 JA |
861 | #endif |
862 | ||
b0e751a9 RV |
863 | /* |
864 | * We use noirq so that we suspend late and resume before the wakeup interrupt | |
865 | * to ensure that we do the !pm_runtime_suspended() check in resume before | |
866 | * there has been a regular pm runtime resume (via pm_runtime_get_sync()). | |
867 | */ | |
868 | static const struct dev_pm_ops nmk_i2c_pm = { | |
869 | .suspend_noirq = nmk_i2c_suspend, | |
870 | .resume_noirq = nmk_i2c_resume, | |
871 | }; | |
872 | ||
3f9900f1 | 873 | static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) |
874 | { | |
5680bc6e | 875 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
3f9900f1 | 876 | } |
877 | ||
878 | static const struct i2c_algorithm nmk_i2c_algo = { | |
879 | .master_xfer = nmk_i2c_xfer, | |
880 | .functionality = nmk_i2c_functionality | |
881 | }; | |
882 | ||
883 | static int __devinit nmk_i2c_probe(struct platform_device *pdev) | |
884 | { | |
885 | int ret = 0; | |
886 | struct resource *res; | |
887 | struct nmk_i2c_controller *pdata = | |
888 | pdev->dev.platform_data; | |
889 | struct nmk_i2c_dev *dev; | |
890 | struct i2c_adapter *adap; | |
891 | ||
892 | dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); | |
893 | if (!dev) { | |
894 | dev_err(&pdev->dev, "cannot allocate memory\n"); | |
895 | ret = -ENOMEM; | |
896 | goto err_no_mem; | |
897 | } | |
a20d2394 | 898 | dev->busy = false; |
3f9900f1 | 899 | dev->pdev = pdev; |
900 | platform_set_drvdata(pdev, dev); | |
901 | ||
902 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
903 | if (!res) { | |
904 | ret = -ENOENT; | |
905 | goto err_no_resource; | |
906 | } | |
907 | ||
908 | if (request_mem_region(res->start, resource_size(res), | |
909 | DRIVER_NAME "I/O region") == NULL) { | |
910 | ret = -EBUSY; | |
911 | goto err_no_region; | |
912 | } | |
913 | ||
914 | dev->virtbase = ioremap(res->start, resource_size(res)); | |
915 | if (!dev->virtbase) { | |
916 | ret = -ENOMEM; | |
917 | goto err_no_ioremap; | |
918 | } | |
919 | ||
920 | dev->irq = platform_get_irq(pdev, 0); | |
921 | ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED, | |
922 | DRIVER_NAME, dev); | |
923 | if (ret) { | |
924 | dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq); | |
925 | goto err_irq; | |
926 | } | |
927 | ||
a20d2394 JA |
928 | dev->regulator = regulator_get(&pdev->dev, "v-i2c"); |
929 | if (IS_ERR(dev->regulator)) { | |
930 | dev_warn(&pdev->dev, "could not get i2c regulator\n"); | |
931 | dev->regulator = NULL; | |
932 | } | |
933 | ||
b0e751a9 RV |
934 | pm_suspend_ignore_children(&pdev->dev, true); |
935 | pm_runtime_enable(&pdev->dev); | |
936 | ||
3f9900f1 | 937 | dev->clk = clk_get(&pdev->dev, NULL); |
938 | if (IS_ERR(dev->clk)) { | |
939 | dev_err(&pdev->dev, "could not get i2c clock\n"); | |
940 | ret = PTR_ERR(dev->clk); | |
941 | goto err_no_clk; | |
942 | } | |
943 | ||
3f9900f1 | 944 | adap = &dev->adap; |
945 | adap->dev.parent = &pdev->dev; | |
946 | adap->owner = THIS_MODULE; | |
947 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
948 | adap->algo = &nmk_i2c_algo; | |
cd20e4fa VS |
949 | adap->timeout = pdata->timeout ? msecs_to_jiffies(pdata->timeout) : |
950 | msecs_to_jiffies(20000); | |
6d779a4c LW |
951 | snprintf(adap->name, sizeof(adap->name), |
952 | "Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start); | |
3f9900f1 | 953 | |
954 | /* fetch the controller id */ | |
955 | adap->nr = pdev->id; | |
956 | ||
957 | /* fetch the controller configuration from machine */ | |
958 | dev->cfg.clk_freq = pdata->clk_freq; | |
959 | dev->cfg.slsu = pdata->slsu; | |
960 | dev->cfg.tft = pdata->tft; | |
961 | dev->cfg.rft = pdata->rft; | |
962 | dev->cfg.sm = pdata->sm; | |
963 | ||
964 | i2c_set_adapdata(adap, dev); | |
965 | ||
6d779a4c LW |
966 | dev_info(&pdev->dev, "initialize %s on virtual " |
967 | "base %p\n", adap->name, dev->virtbase); | |
3f9900f1 | 968 | |
969 | ret = i2c_add_numbered_adapter(adap); | |
970 | if (ret) { | |
971 | dev_err(&pdev->dev, "failed to add adapter\n"); | |
972 | goto err_add_adap; | |
973 | } | |
974 | ||
975 | return 0; | |
976 | ||
3f9900f1 | 977 | err_add_adap: |
978 | clk_put(dev->clk); | |
979 | err_no_clk: | |
a20d2394 JA |
980 | if (dev->regulator) |
981 | regulator_put(dev->regulator); | |
b0e751a9 | 982 | pm_runtime_disable(&pdev->dev); |
3f9900f1 | 983 | free_irq(dev->irq, dev); |
984 | err_irq: | |
985 | iounmap(dev->virtbase); | |
986 | err_no_ioremap: | |
987 | release_mem_region(res->start, resource_size(res)); | |
988 | err_no_region: | |
989 | platform_set_drvdata(pdev, NULL); | |
990 | err_no_resource: | |
991 | kfree(dev); | |
992 | err_no_mem: | |
993 | ||
994 | return ret; | |
995 | } | |
996 | ||
997 | static int __devexit nmk_i2c_remove(struct platform_device *pdev) | |
998 | { | |
a1c27678 | 999 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
3f9900f1 | 1000 | struct nmk_i2c_dev *dev = platform_get_drvdata(pdev); |
1001 | ||
1002 | i2c_del_adapter(&dev->adap); | |
1003 | flush_i2c_fifo(dev); | |
1004 | disable_all_interrupts(dev); | |
1005 | clear_all_interrupts(dev); | |
1006 | /* disable the controller */ | |
1007 | i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); | |
1008 | free_irq(dev->irq, dev); | |
1009 | iounmap(dev->virtbase); | |
a1c27678 RV |
1010 | if (res) |
1011 | release_mem_region(res->start, resource_size(res)); | |
3f9900f1 | 1012 | clk_put(dev->clk); |
a20d2394 JA |
1013 | if (dev->regulator) |
1014 | regulator_put(dev->regulator); | |
b0e751a9 | 1015 | pm_runtime_disable(&pdev->dev); |
3f9900f1 | 1016 | platform_set_drvdata(pdev, NULL); |
1017 | kfree(dev); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static struct platform_driver nmk_i2c_driver = { | |
1023 | .driver = { | |
1024 | .owner = THIS_MODULE, | |
1025 | .name = DRIVER_NAME, | |
b0e751a9 | 1026 | .pm = &nmk_i2c_pm, |
3f9900f1 | 1027 | }, |
1028 | .probe = nmk_i2c_probe, | |
1029 | .remove = __devexit_p(nmk_i2c_remove), | |
1030 | }; | |
1031 | ||
1032 | static int __init nmk_i2c_init(void) | |
1033 | { | |
1034 | return platform_driver_register(&nmk_i2c_driver); | |
1035 | } | |
1036 | ||
1037 | static void __exit nmk_i2c_exit(void) | |
1038 | { | |
1039 | platform_driver_unregister(&nmk_i2c_driver); | |
1040 | } | |
1041 | ||
1042 | subsys_initcall(nmk_i2c_init); | |
1043 | module_exit(nmk_i2c_exit); | |
1044 | ||
1045 | MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); | |
1046 | MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); | |
1047 | MODULE_LICENSE("GPL"); | |
1048 | MODULE_ALIAS("platform:" DRIVER_NAME); |