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Commit | Line | Data |
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18f98b1e PK |
1 | /* |
2 | * i2c-ocores.c: I2C bus driver for OpenCores I2C controller | |
3 | * (http://www.opencores.org/projects.cgi/web/i2c/overview). | |
4 | * | |
5 | * Peter Korsgaard <jacmet@sunsite.dk> | |
6 | * | |
a000b8c1 AL |
7 | * Support for the GRLIB port of the controller by |
8 | * Andreas Larsson <andreas@gaisler.com> | |
9 | * | |
18f98b1e PK |
10 | * This file is licensed under the terms of the GNU General Public License |
11 | * version 2. This program is licensed "as is" without any warranty of any | |
12 | * kind, whether express or implied. | |
13 | */ | |
14 | ||
e961a094 | 15 | #include <linux/clk.h> |
84dbf809 | 16 | #include <linux/err.h> |
18f98b1e PK |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
18f98b1e PK |
19 | #include <linux/errno.h> |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/wait.h> | |
24 | #include <linux/i2c-ocores.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
21782180 | 26 | #include <linux/io.h> |
8bb986a8 | 27 | #include <linux/log2.h> |
18f98b1e PK |
28 | |
29 | struct ocores_i2c { | |
30 | void __iomem *base; | |
8bb986a8 | 31 | u32 reg_shift; |
7326e38f | 32 | u32 reg_io_width; |
18f98b1e PK |
33 | wait_queue_head_t wait; |
34 | struct i2c_adapter adap; | |
35 | struct i2c_msg *msg; | |
36 | int pos; | |
37 | int nmsgs; | |
38 | int state; /* see STATE_ */ | |
e961a094 | 39 | struct clk *clk; |
3a33a854 MF |
40 | int ip_clock_khz; |
41 | int bus_clock_khz; | |
a000b8c1 AL |
42 | void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); |
43 | u8 (*getreg)(struct ocores_i2c *i2c, int reg); | |
18f98b1e PK |
44 | }; |
45 | ||
46 | /* registers */ | |
47 | #define OCI2C_PRELOW 0 | |
48 | #define OCI2C_PREHIGH 1 | |
49 | #define OCI2C_CONTROL 2 | |
50 | #define OCI2C_DATA 3 | |
1ded969f PK |
51 | #define OCI2C_CMD 4 /* write only */ |
52 | #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ | |
18f98b1e PK |
53 | |
54 | #define OCI2C_CTRL_IEN 0x40 | |
55 | #define OCI2C_CTRL_EN 0x80 | |
56 | ||
57 | #define OCI2C_CMD_START 0x91 | |
58 | #define OCI2C_CMD_STOP 0x41 | |
59 | #define OCI2C_CMD_READ 0x21 | |
60 | #define OCI2C_CMD_WRITE 0x11 | |
61 | #define OCI2C_CMD_READ_ACK 0x21 | |
62 | #define OCI2C_CMD_READ_NACK 0x29 | |
63 | #define OCI2C_CMD_IACK 0x01 | |
64 | ||
65 | #define OCI2C_STAT_IF 0x01 | |
66 | #define OCI2C_STAT_TIP 0x02 | |
67 | #define OCI2C_STAT_ARBLOST 0x20 | |
68 | #define OCI2C_STAT_BUSY 0x40 | |
69 | #define OCI2C_STAT_NACK 0x80 | |
70 | ||
71 | #define STATE_DONE 0 | |
72 | #define STATE_START 1 | |
73 | #define STATE_WRITE 2 | |
74 | #define STATE_READ 3 | |
75 | #define STATE_ERROR 4 | |
76 | ||
a000b8c1 AL |
77 | #define TYPE_OCORES 0 |
78 | #define TYPE_GRLIB 1 | |
79 | ||
80 | static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) | |
18f98b1e | 81 | { |
a000b8c1 AL |
82 | iowrite8(value, i2c->base + (reg << i2c->reg_shift)); |
83 | } | |
84 | ||
85 | static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) | |
86 | { | |
87 | iowrite16(value, i2c->base + (reg << i2c->reg_shift)); | |
88 | } | |
89 | ||
90 | static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) | |
91 | { | |
92 | iowrite32(value, i2c->base + (reg << i2c->reg_shift)); | |
93 | } | |
94 | ||
b2991676 MF |
95 | static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) |
96 | { | |
97 | iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); | |
98 | } | |
99 | ||
100 | static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) | |
101 | { | |
102 | iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); | |
103 | } | |
104 | ||
a000b8c1 AL |
105 | static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) |
106 | { | |
107 | return ioread8(i2c->base + (reg << i2c->reg_shift)); | |
108 | } | |
109 | ||
110 | static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) | |
111 | { | |
112 | return ioread16(i2c->base + (reg << i2c->reg_shift)); | |
113 | } | |
114 | ||
115 | static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) | |
116 | { | |
117 | return ioread32(i2c->base + (reg << i2c->reg_shift)); | |
118 | } | |
119 | ||
b2991676 MF |
120 | static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) |
121 | { | |
122 | return ioread16be(i2c->base + (reg << i2c->reg_shift)); | |
123 | } | |
124 | ||
125 | static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) | |
126 | { | |
127 | return ioread32be(i2c->base + (reg << i2c->reg_shift)); | |
128 | } | |
129 | ||
18f98b1e PK |
130 | static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) |
131 | { | |
a000b8c1 | 132 | i2c->setreg(i2c, reg, value); |
18f98b1e PK |
133 | } |
134 | ||
135 | static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) | |
136 | { | |
a000b8c1 | 137 | return i2c->getreg(i2c, reg); |
18f98b1e PK |
138 | } |
139 | ||
140 | static void ocores_process(struct ocores_i2c *i2c) | |
141 | { | |
142 | struct i2c_msg *msg = i2c->msg; | |
143 | u8 stat = oc_getreg(i2c, OCI2C_STATUS); | |
144 | ||
145 | if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { | |
146 | /* stop has been sent */ | |
147 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); | |
148 | wake_up(&i2c->wait); | |
149 | return; | |
150 | } | |
151 | ||
152 | /* error? */ | |
153 | if (stat & OCI2C_STAT_ARBLOST) { | |
154 | i2c->state = STATE_ERROR; | |
155 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
156 | return; | |
157 | } | |
158 | ||
159 | if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { | |
160 | i2c->state = | |
161 | (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; | |
162 | ||
163 | if (stat & OCI2C_STAT_NACK) { | |
164 | i2c->state = STATE_ERROR; | |
165 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
166 | return; | |
167 | } | |
168 | } else | |
169 | msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); | |
170 | ||
171 | /* end of msg? */ | |
172 | if (i2c->pos == msg->len) { | |
173 | i2c->nmsgs--; | |
174 | i2c->msg++; | |
175 | i2c->pos = 0; | |
176 | msg = i2c->msg; | |
177 | ||
178 | if (i2c->nmsgs) { /* end? */ | |
179 | /* send start? */ | |
180 | if (!(msg->flags & I2C_M_NOSTART)) { | |
181 | u8 addr = (msg->addr << 1); | |
182 | ||
183 | if (msg->flags & I2C_M_RD) | |
184 | addr |= 1; | |
185 | ||
186 | i2c->state = STATE_START; | |
187 | ||
188 | oc_setreg(i2c, OCI2C_DATA, addr); | |
189 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); | |
190 | return; | |
191 | } else | |
192 | i2c->state = (msg->flags & I2C_M_RD) | |
193 | ? STATE_READ : STATE_WRITE; | |
194 | } else { | |
195 | i2c->state = STATE_DONE; | |
196 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
197 | return; | |
198 | } | |
199 | } | |
200 | ||
201 | if (i2c->state == STATE_READ) { | |
202 | oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? | |
203 | OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); | |
204 | } else { | |
205 | oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); | |
206 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); | |
207 | } | |
208 | } | |
209 | ||
7d12e780 | 210 | static irqreturn_t ocores_isr(int irq, void *dev_id) |
18f98b1e PK |
211 | { |
212 | struct ocores_i2c *i2c = dev_id; | |
213 | ||
214 | ocores_process(i2c); | |
215 | ||
216 | return IRQ_HANDLED; | |
217 | } | |
218 | ||
219 | static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
220 | { | |
221 | struct ocores_i2c *i2c = i2c_get_adapdata(adap); | |
222 | ||
223 | i2c->msg = msgs; | |
224 | i2c->pos = 0; | |
225 | i2c->nmsgs = num; | |
226 | i2c->state = STATE_START; | |
227 | ||
228 | oc_setreg(i2c, OCI2C_DATA, | |
229 | (i2c->msg->addr << 1) | | |
230 | ((i2c->msg->flags & I2C_M_RD) ? 1:0)); | |
231 | ||
232 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); | |
233 | ||
234 | if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || | |
235 | (i2c->state == STATE_DONE), HZ)) | |
236 | return (i2c->state == STATE_DONE) ? num : -EIO; | |
237 | else | |
238 | return -ETIMEDOUT; | |
239 | } | |
240 | ||
3a33a854 | 241 | static int ocores_init(struct device *dev, struct ocores_i2c *i2c) |
18f98b1e PK |
242 | { |
243 | int prescale; | |
3a33a854 | 244 | int diff; |
18f98b1e PK |
245 | u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
246 | ||
247 | /* make sure the device is disabled */ | |
248 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
249 | ||
3a33a854 MF |
250 | prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; |
251 | prescale = clamp(prescale, 0, 0xffff); | |
252 | ||
253 | diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; | |
254 | if (abs(diff) > i2c->bus_clock_khz / 10) { | |
255 | dev_err(dev, | |
256 | "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", | |
257 | i2c->ip_clock_khz, i2c->bus_clock_khz); | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
18f98b1e PK |
261 | oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); |
262 | oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); | |
263 | ||
264 | /* Init the device */ | |
265 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); | |
266 | oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); | |
3a33a854 MF |
267 | |
268 | return 0; | |
18f98b1e PK |
269 | } |
270 | ||
271 | ||
272 | static u32 ocores_func(struct i2c_adapter *adap) | |
273 | { | |
274 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
275 | } | |
276 | ||
8f9082c5 | 277 | static const struct i2c_algorithm ocores_algorithm = { |
1ce97e07 WS |
278 | .master_xfer = ocores_xfer, |
279 | .functionality = ocores_func, | |
18f98b1e PK |
280 | }; |
281 | ||
282 | static struct i2c_adapter ocores_adapter = { | |
1ce97e07 WS |
283 | .owner = THIS_MODULE, |
284 | .name = "i2c-ocores", | |
285 | .class = I2C_CLASS_DEPRECATED, | |
286 | .algo = &ocores_algorithm, | |
18f98b1e PK |
287 | }; |
288 | ||
eae45e5d | 289 | static const struct of_device_id ocores_i2c_match[] = { |
a000b8c1 AL |
290 | { |
291 | .compatible = "opencores,i2c-ocores", | |
292 | .data = (void *)TYPE_OCORES, | |
293 | }, | |
294 | { | |
295 | .compatible = "aeroflexgaisler,i2cmst", | |
296 | .data = (void *)TYPE_GRLIB, | |
297 | }, | |
298 | {}, | |
299 | }; | |
300 | MODULE_DEVICE_TABLE(of, ocores_i2c_match); | |
301 | ||
049bb69d | 302 | #ifdef CONFIG_OF |
c5d54744 AL |
303 | /* Read and write functions for the GRLIB port of the controller. Registers are |
304 | * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one | |
305 | * register. The subsequent registers has their offset decreased accordingly. */ | |
306 | static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) | |
307 | { | |
308 | u32 rd; | |
309 | int rreg = reg; | |
310 | if (reg != OCI2C_PRELOW) | |
311 | rreg--; | |
312 | rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); | |
313 | if (reg == OCI2C_PREHIGH) | |
314 | return (u8)(rd >> 8); | |
315 | else | |
316 | return (u8)rd; | |
317 | } | |
318 | ||
319 | static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) | |
320 | { | |
321 | u32 curr, wr; | |
322 | int rreg = reg; | |
323 | if (reg != OCI2C_PRELOW) | |
324 | rreg--; | |
325 | if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { | |
326 | curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); | |
327 | if (reg == OCI2C_PRELOW) | |
328 | wr = (curr & 0xff00) | value; | |
329 | else | |
330 | wr = (((u32)value) << 8) | (curr & 0xff); | |
331 | } else { | |
332 | wr = value; | |
333 | } | |
334 | iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); | |
335 | } | |
336 | ||
9ae97a89 J |
337 | static int ocores_i2c_of_probe(struct platform_device *pdev, |
338 | struct ocores_i2c *i2c) | |
049bb69d | 339 | { |
8bb986a8 | 340 | struct device_node *np = pdev->dev.of_node; |
a000b8c1 | 341 | const struct of_device_id *match; |
8bb986a8 | 342 | u32 val; |
3a33a854 MF |
343 | u32 clock_frequency; |
344 | bool clock_frequency_present; | |
8bb986a8 GR |
345 | |
346 | if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { | |
347 | /* no 'reg-shift', check for deprecated 'regstep' */ | |
348 | if (!of_property_read_u32(np, "regstep", &val)) { | |
349 | if (!is_power_of_2(val)) { | |
350 | dev_err(&pdev->dev, "invalid regstep %d\n", | |
351 | val); | |
352 | return -EINVAL; | |
353 | } | |
354 | i2c->reg_shift = ilog2(val); | |
355 | dev_warn(&pdev->dev, | |
356 | "regstep property deprecated, use reg-shift\n"); | |
357 | } | |
049bb69d | 358 | } |
049bb69d | 359 | |
3a33a854 MF |
360 | clock_frequency_present = !of_property_read_u32(np, "clock-frequency", |
361 | &clock_frequency); | |
362 | i2c->bus_clock_khz = 100; | |
363 | ||
e961a094 MF |
364 | i2c->clk = devm_clk_get(&pdev->dev, NULL); |
365 | ||
366 | if (!IS_ERR(i2c->clk)) { | |
367 | int ret = clk_prepare_enable(i2c->clk); | |
368 | ||
369 | if (ret) { | |
370 | dev_err(&pdev->dev, | |
371 | "clk_prepare_enable failed: %d\n", ret); | |
372 | return ret; | |
373 | } | |
374 | i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; | |
375 | if (clock_frequency_present) | |
376 | i2c->bus_clock_khz = clock_frequency / 1000; | |
0d8fb599 WS |
377 | } |
378 | ||
379 | if (i2c->ip_clock_khz == 0) { | |
380 | if (of_property_read_u32(np, "opencores,ip-clock-frequency", | |
381 | &val)) { | |
382 | if (!clock_frequency_present) { | |
383 | dev_err(&pdev->dev, | |
384 | "Missing required parameter 'opencores,ip-clock-frequency'\n"); | |
385 | return -ENODEV; | |
386 | } | |
387 | i2c->ip_clock_khz = clock_frequency / 1000; | |
388 | dev_warn(&pdev->dev, | |
389 | "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); | |
390 | } else { | |
391 | i2c->ip_clock_khz = val / 1000; | |
392 | if (clock_frequency_present) | |
393 | i2c->bus_clock_khz = clock_frequency / 1000; | |
3a33a854 | 394 | } |
049bb69d | 395 | } |
049bb69d | 396 | |
7326e38f GR |
397 | of_property_read_u32(pdev->dev.of_node, "reg-io-width", |
398 | &i2c->reg_io_width); | |
a000b8c1 AL |
399 | |
400 | match = of_match_node(ocores_i2c_match, pdev->dev.of_node); | |
6beaddf2 | 401 | if (match && (long)match->data == TYPE_GRLIB) { |
a000b8c1 AL |
402 | dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); |
403 | i2c->setreg = oc_setreg_grlib; | |
404 | i2c->getreg = oc_getreg_grlib; | |
405 | } | |
406 | ||
049bb69d JB |
407 | return 0; |
408 | } | |
409 | #else | |
410 | #define ocores_i2c_of_probe(pdev,i2c) -ENODEV | |
411 | #endif | |
18f98b1e | 412 | |
0b255e92 | 413 | static int ocores_i2c_probe(struct platform_device *pdev) |
18f98b1e PK |
414 | { |
415 | struct ocores_i2c *i2c; | |
416 | struct ocores_i2c_platform_data *pdata; | |
f5f35a92 AL |
417 | struct resource *res; |
418 | int irq; | |
18f98b1e | 419 | int ret; |
dd14be4c | 420 | int i; |
18f98b1e | 421 | |
f5f35a92 AL |
422 | irq = platform_get_irq(pdev, 0); |
423 | if (irq < 0) | |
424 | return irq; | |
18f98b1e | 425 | |
47def5b8 | 426 | i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); |
18f98b1e PK |
427 | if (!i2c) |
428 | return -ENOMEM; | |
429 | ||
b7d12a86 | 430 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
431 | i2c->base = devm_ioremap_resource(&pdev->dev, res); |
432 | if (IS_ERR(i2c->base)) | |
433 | return PTR_ERR(i2c->base); | |
18f98b1e | 434 | |
6d4028c6 | 435 | pdata = dev_get_platdata(&pdev->dev); |
049bb69d | 436 | if (pdata) { |
8bb986a8 | 437 | i2c->reg_shift = pdata->reg_shift; |
7326e38f | 438 | i2c->reg_io_width = pdata->reg_io_width; |
3a33a854 MF |
439 | i2c->ip_clock_khz = pdata->clock_khz; |
440 | i2c->bus_clock_khz = 100; | |
049bb69d JB |
441 | } else { |
442 | ret = ocores_i2c_of_probe(pdev, i2c); | |
443 | if (ret) | |
444 | return ret; | |
445 | } | |
446 | ||
7326e38f GR |
447 | if (i2c->reg_io_width == 0) |
448 | i2c->reg_io_width = 1; /* Set to default value */ | |
449 | ||
a000b8c1 | 450 | if (!i2c->setreg || !i2c->getreg) { |
b2991676 MF |
451 | bool be = pdata ? pdata->big_endian : |
452 | of_device_is_big_endian(pdev->dev.of_node); | |
453 | ||
a000b8c1 AL |
454 | switch (i2c->reg_io_width) { |
455 | case 1: | |
456 | i2c->setreg = oc_setreg_8; | |
457 | i2c->getreg = oc_getreg_8; | |
458 | break; | |
459 | ||
460 | case 2: | |
b2991676 MF |
461 | i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; |
462 | i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; | |
a000b8c1 AL |
463 | break; |
464 | ||
465 | case 4: | |
b2991676 MF |
466 | i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; |
467 | i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; | |
a000b8c1 AL |
468 | break; |
469 | ||
470 | default: | |
471 | dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", | |
472 | i2c->reg_io_width); | |
473 | return -EINVAL; | |
474 | } | |
475 | } | |
476 | ||
3a33a854 MF |
477 | ret = ocores_init(&pdev->dev, i2c); |
478 | if (ret) | |
479 | return ret; | |
18f98b1e PK |
480 | |
481 | init_waitqueue_head(&i2c->wait); | |
f5f35a92 | 482 | ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, |
47def5b8 | 483 | pdev->name, i2c); |
18f98b1e PK |
484 | if (ret) { |
485 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
47def5b8 | 486 | return ret; |
18f98b1e PK |
487 | } |
488 | ||
489 | /* hook up driver to tree */ | |
490 | platform_set_drvdata(pdev, i2c); | |
491 | i2c->adap = ocores_adapter; | |
492 | i2c_set_adapdata(&i2c->adap, i2c); | |
493 | i2c->adap.dev.parent = &pdev->dev; | |
049bb69d | 494 | i2c->adap.dev.of_node = pdev->dev.of_node; |
18f98b1e PK |
495 | |
496 | /* add i2c adapter to i2c tree */ | |
497 | ret = i2c_add_adapter(&i2c->adap); | |
498 | if (ret) { | |
499 | dev_err(&pdev->dev, "Failed to add adapter\n"); | |
47def5b8 | 500 | return ret; |
18f98b1e PK |
501 | } |
502 | ||
dd14be4c | 503 | /* add in known devices to the bus */ |
049bb69d JB |
504 | if (pdata) { |
505 | for (i = 0; i < pdata->num_devices; i++) | |
506 | i2c_new_device(&i2c->adap, pdata->devices + i); | |
507 | } | |
dd14be4c | 508 | |
18f98b1e | 509 | return 0; |
18f98b1e PK |
510 | } |
511 | ||
0b255e92 | 512 | static int ocores_i2c_remove(struct platform_device *pdev) |
18f98b1e PK |
513 | { |
514 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
18f98b1e PK |
515 | |
516 | /* disable i2c logic */ | |
517 | oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) | |
518 | & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
519 | ||
520 | /* remove adapter & data */ | |
521 | i2c_del_adapter(&i2c->adap); | |
18f98b1e | 522 | |
e961a094 MF |
523 | if (!IS_ERR(i2c->clk)) |
524 | clk_disable_unprepare(i2c->clk); | |
525 | ||
18f98b1e PK |
526 | return 0; |
527 | } | |
528 | ||
f076e916 | 529 | #ifdef CONFIG_PM_SLEEP |
84603c7c | 530 | static int ocores_i2c_suspend(struct device *dev) |
2373c180 | 531 | { |
84603c7c | 532 | struct ocores_i2c *i2c = dev_get_drvdata(dev); |
2373c180 ML |
533 | u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
534 | ||
535 | /* make sure the device is disabled */ | |
536 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
537 | ||
e961a094 MF |
538 | if (!IS_ERR(i2c->clk)) |
539 | clk_disable_unprepare(i2c->clk); | |
2373c180 ML |
540 | return 0; |
541 | } | |
542 | ||
84603c7c | 543 | static int ocores_i2c_resume(struct device *dev) |
2373c180 | 544 | { |
84603c7c | 545 | struct ocores_i2c *i2c = dev_get_drvdata(dev); |
2373c180 | 546 | |
e961a094 | 547 | if (!IS_ERR(i2c->clk)) { |
0d8fb599 | 548 | unsigned long rate; |
e961a094 MF |
549 | int ret = clk_prepare_enable(i2c->clk); |
550 | ||
551 | if (ret) { | |
552 | dev_err(dev, | |
553 | "clk_prepare_enable failed: %d\n", ret); | |
554 | return ret; | |
555 | } | |
0d8fb599 WS |
556 | rate = clk_get_rate(i2c->clk) / 1000; |
557 | if (rate) | |
558 | i2c->ip_clock_khz = rate; | |
e961a094 | 559 | } |
3a33a854 | 560 | return ocores_init(dev, i2c); |
2373c180 | 561 | } |
84603c7c RW |
562 | |
563 | static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); | |
564 | #define OCORES_I2C_PM (&ocores_i2c_pm) | |
2373c180 | 565 | #else |
84603c7c | 566 | #define OCORES_I2C_PM NULL |
2373c180 ML |
567 | #endif |
568 | ||
18f98b1e | 569 | static struct platform_driver ocores_i2c_driver = { |
2373c180 | 570 | .probe = ocores_i2c_probe, |
0b255e92 | 571 | .remove = ocores_i2c_remove, |
2373c180 | 572 | .driver = { |
18f98b1e | 573 | .name = "ocores-i2c", |
c9e358df | 574 | .of_match_table = ocores_i2c_match, |
84603c7c | 575 | .pm = OCORES_I2C_PM, |
18f98b1e PK |
576 | }, |
577 | }; | |
578 | ||
a3664b51 | 579 | module_platform_driver(ocores_i2c_driver); |
18f98b1e PK |
580 | |
581 | MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); | |
582 | MODULE_DESCRIPTION("OpenCores I2C bus driver"); | |
583 | MODULE_LICENSE("GPL"); | |
a3664b51 | 584 | MODULE_ALIAS("platform:ocores-i2c"); |