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18f98b1e PK |
1 | /* |
2 | * i2c-ocores.c: I2C bus driver for OpenCores I2C controller | |
3 | * (http://www.opencores.org/projects.cgi/web/i2c/overview). | |
4 | * | |
5 | * Peter Korsgaard <jacmet@sunsite.dk> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
18f98b1e PK |
12 | #include <linux/kernel.h> |
13 | #include <linux/module.h> | |
18f98b1e PK |
14 | #include <linux/init.h> |
15 | #include <linux/errno.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/wait.h> | |
20 | #include <linux/i2c-ocores.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
18f98b1e PK |
22 | #include <asm/io.h> |
23 | ||
24 | struct ocores_i2c { | |
25 | void __iomem *base; | |
26 | int regstep; | |
27 | wait_queue_head_t wait; | |
28 | struct i2c_adapter adap; | |
29 | struct i2c_msg *msg; | |
30 | int pos; | |
31 | int nmsgs; | |
32 | int state; /* see STATE_ */ | |
2373c180 | 33 | int clock_khz; |
18f98b1e PK |
34 | }; |
35 | ||
36 | /* registers */ | |
37 | #define OCI2C_PRELOW 0 | |
38 | #define OCI2C_PREHIGH 1 | |
39 | #define OCI2C_CONTROL 2 | |
40 | #define OCI2C_DATA 3 | |
1ded969f PK |
41 | #define OCI2C_CMD 4 /* write only */ |
42 | #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ | |
18f98b1e PK |
43 | |
44 | #define OCI2C_CTRL_IEN 0x40 | |
45 | #define OCI2C_CTRL_EN 0x80 | |
46 | ||
47 | #define OCI2C_CMD_START 0x91 | |
48 | #define OCI2C_CMD_STOP 0x41 | |
49 | #define OCI2C_CMD_READ 0x21 | |
50 | #define OCI2C_CMD_WRITE 0x11 | |
51 | #define OCI2C_CMD_READ_ACK 0x21 | |
52 | #define OCI2C_CMD_READ_NACK 0x29 | |
53 | #define OCI2C_CMD_IACK 0x01 | |
54 | ||
55 | #define OCI2C_STAT_IF 0x01 | |
56 | #define OCI2C_STAT_TIP 0x02 | |
57 | #define OCI2C_STAT_ARBLOST 0x20 | |
58 | #define OCI2C_STAT_BUSY 0x40 | |
59 | #define OCI2C_STAT_NACK 0x80 | |
60 | ||
61 | #define STATE_DONE 0 | |
62 | #define STATE_START 1 | |
63 | #define STATE_WRITE 2 | |
64 | #define STATE_READ 3 | |
65 | #define STATE_ERROR 4 | |
66 | ||
67 | static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) | |
68 | { | |
69 | iowrite8(value, i2c->base + reg * i2c->regstep); | |
70 | } | |
71 | ||
72 | static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) | |
73 | { | |
74 | return ioread8(i2c->base + reg * i2c->regstep); | |
75 | } | |
76 | ||
77 | static void ocores_process(struct ocores_i2c *i2c) | |
78 | { | |
79 | struct i2c_msg *msg = i2c->msg; | |
80 | u8 stat = oc_getreg(i2c, OCI2C_STATUS); | |
81 | ||
82 | if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { | |
83 | /* stop has been sent */ | |
84 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); | |
85 | wake_up(&i2c->wait); | |
86 | return; | |
87 | } | |
88 | ||
89 | /* error? */ | |
90 | if (stat & OCI2C_STAT_ARBLOST) { | |
91 | i2c->state = STATE_ERROR; | |
92 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
93 | return; | |
94 | } | |
95 | ||
96 | if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { | |
97 | i2c->state = | |
98 | (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; | |
99 | ||
100 | if (stat & OCI2C_STAT_NACK) { | |
101 | i2c->state = STATE_ERROR; | |
102 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
103 | return; | |
104 | } | |
105 | } else | |
106 | msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); | |
107 | ||
108 | /* end of msg? */ | |
109 | if (i2c->pos == msg->len) { | |
110 | i2c->nmsgs--; | |
111 | i2c->msg++; | |
112 | i2c->pos = 0; | |
113 | msg = i2c->msg; | |
114 | ||
115 | if (i2c->nmsgs) { /* end? */ | |
116 | /* send start? */ | |
117 | if (!(msg->flags & I2C_M_NOSTART)) { | |
118 | u8 addr = (msg->addr << 1); | |
119 | ||
120 | if (msg->flags & I2C_M_RD) | |
121 | addr |= 1; | |
122 | ||
123 | i2c->state = STATE_START; | |
124 | ||
125 | oc_setreg(i2c, OCI2C_DATA, addr); | |
126 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); | |
127 | return; | |
128 | } else | |
129 | i2c->state = (msg->flags & I2C_M_RD) | |
130 | ? STATE_READ : STATE_WRITE; | |
131 | } else { | |
132 | i2c->state = STATE_DONE; | |
133 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); | |
134 | return; | |
135 | } | |
136 | } | |
137 | ||
138 | if (i2c->state == STATE_READ) { | |
139 | oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? | |
140 | OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); | |
141 | } else { | |
142 | oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); | |
143 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); | |
144 | } | |
145 | } | |
146 | ||
7d12e780 | 147 | static irqreturn_t ocores_isr(int irq, void *dev_id) |
18f98b1e PK |
148 | { |
149 | struct ocores_i2c *i2c = dev_id; | |
150 | ||
151 | ocores_process(i2c); | |
152 | ||
153 | return IRQ_HANDLED; | |
154 | } | |
155 | ||
156 | static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
157 | { | |
158 | struct ocores_i2c *i2c = i2c_get_adapdata(adap); | |
159 | ||
160 | i2c->msg = msgs; | |
161 | i2c->pos = 0; | |
162 | i2c->nmsgs = num; | |
163 | i2c->state = STATE_START; | |
164 | ||
165 | oc_setreg(i2c, OCI2C_DATA, | |
166 | (i2c->msg->addr << 1) | | |
167 | ((i2c->msg->flags & I2C_M_RD) ? 1:0)); | |
168 | ||
169 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); | |
170 | ||
171 | if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || | |
172 | (i2c->state == STATE_DONE), HZ)) | |
173 | return (i2c->state == STATE_DONE) ? num : -EIO; | |
174 | else | |
175 | return -ETIMEDOUT; | |
176 | } | |
177 | ||
2373c180 | 178 | static void ocores_init(struct ocores_i2c *i2c) |
18f98b1e PK |
179 | { |
180 | int prescale; | |
181 | u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); | |
182 | ||
183 | /* make sure the device is disabled */ | |
184 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
185 | ||
2373c180 | 186 | prescale = (i2c->clock_khz / (5*100)) - 1; |
18f98b1e PK |
187 | oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); |
188 | oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); | |
189 | ||
190 | /* Init the device */ | |
191 | oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); | |
192 | oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); | |
193 | } | |
194 | ||
195 | ||
196 | static u32 ocores_func(struct i2c_adapter *adap) | |
197 | { | |
198 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
199 | } | |
200 | ||
8f9082c5 | 201 | static const struct i2c_algorithm ocores_algorithm = { |
18f98b1e PK |
202 | .master_xfer = ocores_xfer, |
203 | .functionality = ocores_func, | |
204 | }; | |
205 | ||
206 | static struct i2c_adapter ocores_adapter = { | |
207 | .owner = THIS_MODULE, | |
208 | .name = "i2c-ocores", | |
3401b2ff | 209 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
18f98b1e | 210 | .algo = &ocores_algorithm, |
18f98b1e PK |
211 | }; |
212 | ||
213 | ||
214 | static int __devinit ocores_i2c_probe(struct platform_device *pdev) | |
215 | { | |
216 | struct ocores_i2c *i2c; | |
217 | struct ocores_i2c_platform_data *pdata; | |
218 | struct resource *res, *res2; | |
219 | int ret; | |
dd14be4c | 220 | int i; |
18f98b1e PK |
221 | |
222 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
223 | if (!res) | |
224 | return -ENODEV; | |
225 | ||
226 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
227 | if (!res2) | |
228 | return -ENODEV; | |
229 | ||
230 | pdata = (struct ocores_i2c_platform_data*) pdev->dev.platform_data; | |
231 | if (!pdata) | |
232 | return -ENODEV; | |
233 | ||
234 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); | |
235 | if (!i2c) | |
236 | return -ENOMEM; | |
237 | ||
c6ffddea | 238 | if (!request_mem_region(res->start, resource_size(res), |
18f98b1e PK |
239 | pdev->name)) { |
240 | dev_err(&pdev->dev, "Memory region busy\n"); | |
241 | ret = -EBUSY; | |
242 | goto request_mem_failed; | |
243 | } | |
244 | ||
c6ffddea | 245 | i2c->base = ioremap(res->start, resource_size(res)); |
18f98b1e PK |
246 | if (!i2c->base) { |
247 | dev_err(&pdev->dev, "Unable to map registers\n"); | |
248 | ret = -EIO; | |
249 | goto map_failed; | |
250 | } | |
251 | ||
252 | i2c->regstep = pdata->regstep; | |
2373c180 ML |
253 | i2c->clock_khz = pdata->clock_khz; |
254 | ocores_init(i2c); | |
18f98b1e PK |
255 | |
256 | init_waitqueue_head(&i2c->wait); | |
257 | ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c); | |
258 | if (ret) { | |
259 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
260 | goto request_irq_failed; | |
261 | } | |
262 | ||
263 | /* hook up driver to tree */ | |
264 | platform_set_drvdata(pdev, i2c); | |
265 | i2c->adap = ocores_adapter; | |
266 | i2c_set_adapdata(&i2c->adap, i2c); | |
267 | i2c->adap.dev.parent = &pdev->dev; | |
268 | ||
269 | /* add i2c adapter to i2c tree */ | |
270 | ret = i2c_add_adapter(&i2c->adap); | |
271 | if (ret) { | |
272 | dev_err(&pdev->dev, "Failed to add adapter\n"); | |
273 | goto add_adapter_failed; | |
274 | } | |
275 | ||
dd14be4c RR |
276 | /* add in known devices to the bus */ |
277 | for (i = 0; i < pdata->num_devices; i++) | |
278 | i2c_new_device(&i2c->adap, pdata->devices + i); | |
279 | ||
18f98b1e PK |
280 | return 0; |
281 | ||
282 | add_adapter_failed: | |
283 | free_irq(res2->start, i2c); | |
284 | request_irq_failed: | |
285 | iounmap(i2c->base); | |
286 | map_failed: | |
c6ffddea | 287 | release_mem_region(res->start, resource_size(res)); |
18f98b1e PK |
288 | request_mem_failed: |
289 | kfree(i2c); | |
290 | ||
291 | return ret; | |
292 | } | |
293 | ||
294 | static int __devexit ocores_i2c_remove(struct platform_device* pdev) | |
295 | { | |
296 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
297 | struct resource *res; | |
298 | ||
299 | /* disable i2c logic */ | |
300 | oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) | |
301 | & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
302 | ||
303 | /* remove adapter & data */ | |
304 | i2c_del_adapter(&i2c->adap); | |
305 | platform_set_drvdata(pdev, NULL); | |
306 | ||
307 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
308 | if (res) | |
309 | free_irq(res->start, i2c); | |
310 | ||
311 | iounmap(i2c->base); | |
312 | ||
313 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
314 | if (res) | |
c6ffddea | 315 | release_mem_region(res->start, resource_size(res)); |
18f98b1e PK |
316 | |
317 | kfree(i2c); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
2373c180 ML |
322 | #ifdef CONFIG_PM |
323 | static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state) | |
324 | { | |
325 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
326 | u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); | |
327 | ||
328 | /* make sure the device is disabled */ | |
329 | oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static int ocores_i2c_resume(struct platform_device *pdev) | |
335 | { | |
336 | struct ocores_i2c *i2c = platform_get_drvdata(pdev); | |
337 | ||
338 | ocores_init(i2c); | |
339 | ||
340 | return 0; | |
341 | } | |
342 | #else | |
343 | #define ocores_i2c_suspend NULL | |
344 | #define ocores_i2c_resume NULL | |
345 | #endif | |
346 | ||
add8eda7 KS |
347 | /* work with hotplug and coldplug */ |
348 | MODULE_ALIAS("platform:ocores-i2c"); | |
349 | ||
18f98b1e | 350 | static struct platform_driver ocores_i2c_driver = { |
2373c180 ML |
351 | .probe = ocores_i2c_probe, |
352 | .remove = __devexit_p(ocores_i2c_remove), | |
353 | .suspend = ocores_i2c_suspend, | |
354 | .resume = ocores_i2c_resume, | |
355 | .driver = { | |
18f98b1e PK |
356 | .owner = THIS_MODULE, |
357 | .name = "ocores-i2c", | |
358 | }, | |
359 | }; | |
360 | ||
361 | static int __init ocores_i2c_init(void) | |
362 | { | |
363 | return platform_driver_register(&ocores_i2c_driver); | |
364 | } | |
365 | ||
366 | static void __exit ocores_i2c_exit(void) | |
367 | { | |
368 | platform_driver_unregister(&ocores_i2c_driver); | |
369 | } | |
370 | ||
371 | module_init(ocores_i2c_init); | |
372 | module_exit(ocores_i2c_exit); | |
373 | ||
374 | MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); | |
375 | MODULE_DESCRIPTION("OpenCores I2C bus driver"); | |
376 | MODULE_LICENSE("GPL"); |