[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-octeon-core.h

#include <linux/atomic.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/i2c-smbus.h>
#include <linux/io.h>
#include <linux/kernel.h>

/* Controller command patterns */
#define SW_TWSI_V		BIT_ULL(63)	/* Valid bit */
#define SW_TWSI_EIA		BIT_ULL(61)	/* Extended internal address */
#define SW_TWSI_R		BIT_ULL(56)	/* Result or read bit */
#define SW_TWSI_SOVR		BIT_ULL(55)	/* Size override */
#define SW_TWSI_SIZE_SHIFT	52
#define SW_TWSI_ADDR_SHIFT	40
#define SW_TWSI_IA_SHIFT	32		/* Internal address */

/* Controller opcode word (bits 60:57) */
#define SW_TWSI_OP_SHIFT	57
#define SW_TWSI_OP_7		(0ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_7_IA		(1ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_10		(2ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_10_IA	(3ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_TWSI_CLK	(4ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_EOP		(6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */

/* Controller extended opcode word (bits 34:32) */
#define SW_TWSI_EOP_SHIFT	32
#define SW_TWSI_EOP_TWSI_DATA	(SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CTL	(SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CLKCTL	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_STAT	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_RST	(SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)

/* Controller command and status bits */
#define TWSI_CTL_CE		0x80	/* High level controller enable */
#define TWSI_CTL_ENAB		0x40	/* Bus enable */
#define TWSI_CTL_STA		0x20	/* Master-mode start, HW clears when done */
#define TWSI_CTL_STP		0x10	/* Master-mode stop, HW clears when done */
#define TWSI_CTL_IFLG		0x08	/* HW event, SW writes 0 to ACK */
#define TWSI_CTL_AAK		0x04	/* Assert ACK */

/* Status values */
#define STAT_ERROR		0x00
#define STAT_START		0x08
#define STAT_REP_START		0x10
#define STAT_TXADDR_ACK		0x18
#define STAT_TXADDR_NAK		0x20
#define STAT_TXDATA_ACK		0x28
#define STAT_TXDATA_NAK		0x30
#define STAT_LOST_ARB_38	0x38
#define STAT_RXADDR_ACK		0x40
#define STAT_RXADDR_NAK		0x48
#define STAT_RXDATA_ACK		0x50
#define STAT_RXDATA_NAK		0x58
#define STAT_SLAVE_60		0x60
#define STAT_LOST_ARB_68	0x68
#define STAT_SLAVE_70		0x70
#define STAT_LOST_ARB_78	0x78
#define STAT_SLAVE_80		0x80
#define STAT_SLAVE_88		0x88
#define STAT_GENDATA_ACK	0x90
#define STAT_GENDATA_NAK	0x98
#define STAT_SLAVE_A0		0xA0
#define STAT_SLAVE_A8		0xA8
#define STAT_LOST_ARB_B0	0xB0
#define STAT_SLAVE_LOST		0xB8
#define STAT_SLAVE_NAK		0xC0
#define STAT_SLAVE_ACK		0xC8
#define STAT_AD2W_ACK		0xD0
#define STAT_AD2W_NAK		0xD8
#define STAT_IDLE		0xF8

/* TWSI_INT values */
#define TWSI_INT_ST_INT		BIT_ULL(0)
#define TWSI_INT_TS_INT		BIT_ULL(1)
#define TWSI_INT_CORE_INT	BIT_ULL(2)
#define TWSI_INT_ST_EN		BIT_ULL(4)
#define TWSI_INT_TS_EN		BIT_ULL(5)
#define TWSI_INT_CORE_EN	BIT_ULL(6)
#define TWSI_INT_SDA_OVR	BIT_ULL(8)
#define TWSI_INT_SCL_OVR	BIT_ULL(9)
#define TWSI_INT_SDA		BIT_ULL(10)
#define TWSI_INT_SCL		BIT_ULL(11)

#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */

/* Register offsets */
struct octeon_i2c_reg_offset {
	unsigned int sw_twsi;
	unsigned int twsi_int;
	unsigned int sw_twsi_ext;
};

#define SW_TWSI(x)	(x->roff.sw_twsi)
#define TWSI_INT(x)	(x->roff.twsi_int)
#define SW_TWSI_EXT(x)	(x->roff.sw_twsi_ext)

struct octeon_i2c {
	wait_queue_head_t queue;
	struct i2c_adapter adap;
	struct octeon_i2c_reg_offset roff;
	struct clk *clk;
	int irq;
	int hlc_irq;		/* For cn7890 only */
	u32 twsi_freq;
	int sys_freq;
	void __iomem *twsi_base;
	struct device *dev;
	bool hlc_enabled;
	bool broken_irq_mode;
	bool broken_irq_check;
	void (*int_enable)(struct octeon_i2c *);
	void (*int_disable)(struct octeon_i2c *);
	void (*hlc_int_enable)(struct octeon_i2c *);
	void (*hlc_int_disable)(struct octeon_i2c *);
	atomic_t int_enable_cnt;
	atomic_t hlc_int_enable_cnt;
	struct i2c_smbus_alert_setup alert_data;
	struct i2c_client *ara;
};

static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
{
	__raw_writeq(val, addr);
	__raw_readq(addr);	/* wait for write to land */
}

/**
 * octeon_i2c_reg_write - write an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 * @data: Value to be written
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
{
	int tries = 1000;
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));
	do {
		tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
		if (--tries < 0)
			return;
	} while ((tmp & SW_TWSI_V) != 0);
}

#define octeon_i2c_ctl_write(i2c, val)					\
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
#define octeon_i2c_data_write(i2c, val)					\
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)

/**
 * octeon_i2c_reg_read - read lower bits of an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 *
 * Returns the data.
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
				      int *error)
{
	int tries = 1000;
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));
	do {
		tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
		if (--tries < 0) {
			/* signal that the returned data is invalid */
			if (error)
				*error = -EIO;
			return 0;
		}
	} while ((tmp & SW_TWSI_V) != 0);

	return tmp & 0xFF;
}

#define octeon_i2c_ctl_read(i2c)					\
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
#define octeon_i2c_data_read(i2c, error)				\
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
#define octeon_i2c_stat_read(i2c)					\
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)

/**
 * octeon_i2c_read_int - read the TWSI_INT register
 * @i2c: The struct octeon_i2c
 *
 * Returns the value of the register.
 */
static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
{
	return __raw_readq(i2c->twsi_base + TWSI_INT(i2c));
}

/**
 * octeon_i2c_write_int - write the TWSI_INT register
 * @i2c: The struct octeon_i2c
 * @data: Value to be written
 */
static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
{
	octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));
}

/* Prototypes */
irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
void octeon_i2c_set_clock(struct octeon_i2c *i2c);
extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;
Commit	Line	Data
ad83665b JG	1	#include <linux/atomic.h>
	2	#include <linux/clk.h>
	3	#include <linux/delay.h>
	4	#include <linux/device.h>
	5	#include <linux/i2c.h>
1e586671	6	#include <linux/i2c-smbus.h>
ad83665b JG	7	#include <linux/io.h>
ad83665b JG	8	#include <linux/kernel.h>
ad83665b	9
ad83665b JG	10	/* Controller command patterns */
	11	#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
	12	#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
	13	#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
	14	#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
	15	#define SW_TWSI_SIZE_SHIFT 52
	16	#define SW_TWSI_ADDR_SHIFT 40
	17	#define SW_TWSI_IA_SHIFT 32 /* Internal address */
	18
	19	/* Controller opcode word (bits 60:57) */
	20	#define SW_TWSI_OP_SHIFT 57
	21	#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
	22	#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
	23	#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
	24	#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
	25	#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
	26	#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
	27
	28	/* Controller extended opcode word (bits 34:32) */
	29	#define SW_TWSI_EOP_SHIFT 32
	30	#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP \| 1ULL << SW_TWSI_EOP_SHIFT)
	31	#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP \| 2ULL << SW_TWSI_EOP_SHIFT)
	32	#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	33	#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	34	#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP \| 7ULL << SW_TWSI_EOP_SHIFT)
	35
	36	/* Controller command and status bits */
	37	#define TWSI_CTL_CE 0x80 /* High level controller enable */
	38	#define TWSI_CTL_ENAB 0x40 /* Bus enable */
	39	#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
	40	#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
	41	#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
	42	#define TWSI_CTL_AAK 0x04 /* Assert ACK */
	43
	44	/* Status values */
	45	#define STAT_ERROR 0x00
	46	#define STAT_START 0x08
	47	#define STAT_REP_START 0x10
	48	#define STAT_TXADDR_ACK 0x18
	49	#define STAT_TXADDR_NAK 0x20
	50	#define STAT_TXDATA_ACK 0x28
	51	#define STAT_TXDATA_NAK 0x30
	52	#define STAT_LOST_ARB_38 0x38
	53	#define STAT_RXADDR_ACK 0x40
	54	#define STAT_RXADDR_NAK 0x48
	55	#define STAT_RXDATA_ACK 0x50
	56	#define STAT_RXDATA_NAK 0x58
	57	#define STAT_SLAVE_60 0x60
	58	#define STAT_LOST_ARB_68 0x68
	59	#define STAT_SLAVE_70 0x70
	60	#define STAT_LOST_ARB_78 0x78
	61	#define STAT_SLAVE_80 0x80
	62	#define STAT_SLAVE_88 0x88
	63	#define STAT_GENDATA_ACK 0x90
	64	#define STAT_GENDATA_NAK 0x98
	65	#define STAT_SLAVE_A0 0xA0
	66	#define STAT_SLAVE_A8 0xA8
	67	#define STAT_LOST_ARB_B0 0xB0
	68	#define STAT_SLAVE_LOST 0xB8
	69	#define STAT_SLAVE_NAK 0xC0
	70	#define STAT_SLAVE_ACK 0xC8
	71	#define STAT_AD2W_ACK 0xD0
	72	#define STAT_AD2W_NAK 0xD8
	73	#define STAT_IDLE 0xF8
74
75	/* TWSI_INT values */
76	#define TWSI_INT_ST_INT BIT_ULL(0)
77	#define TWSI_INT_TS_INT BIT_ULL(1)
78	#define TWSI_INT_CORE_INT BIT_ULL(2)
79	#define TWSI_INT_ST_EN BIT_ULL(4)
80	#define TWSI_INT_TS_EN BIT_ULL(5)
81	#define TWSI_INT_CORE_EN BIT_ULL(6)
82	#define TWSI_INT_SDA_OVR BIT_ULL(8)
83	#define TWSI_INT_SCL_OVR BIT_ULL(9)
84	#define TWSI_INT_SDA BIT_ULL(10)
85	#define TWSI_INT_SCL BIT_ULL(11)
86
87	#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
88
97d97004 JG	89	/* Register offsets */
	90	struct octeon_i2c_reg_offset {
	91	unsigned int sw_twsi;
	92	unsigned int twsi_int;
	93	unsigned int sw_twsi_ext;
	94	};
	95
	96	#define SW_TWSI(x) (x->roff.sw_twsi)
	97	#define TWSI_INT(x) (x->roff.twsi_int)
	98	#define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext)
	99
ad83665b JG	100	struct octeon_i2c {
	101	wait_queue_head_t queue;
	102	struct i2c_adapter adap;
97d97004	103	struct octeon_i2c_reg_offset roff;
22d40209	104	struct clk *clk;
ad83665b JG	105	int irq;
	106	int hlc_irq; /* For cn7890 only */
	107	u32 twsi_freq;
	108	int sys_freq;
	109	void __iomem *twsi_base;
	110	struct device *dev;
	111	bool hlc_enabled;
	112	bool broken_irq_mode;
	113	bool broken_irq_check;
	114	void (int_enable)(struct octeon_i2c );
	115	void (int_disable)(struct octeon_i2c );
	116	void (hlc_int_enable)(struct octeon_i2c );
	117	void (hlc_int_disable)(struct octeon_i2c );
	118	atomic_t int_enable_cnt;
	119	atomic_t hlc_int_enable_cnt;
1e586671 JG	120	struct i2c_smbus_alert_setup alert_data;
1e586671 JG	121	struct i2c_client *ara;
ad83665b JG	122	};
	123
	124	static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
	125	{
	126	__raw_writeq(val, addr);
	127	__raw_readq(addr); /* wait for write to land */
	128	}
	129
	130	/**
	131	* octeon_i2c_reg_write - write an I2C core register
	132	* @i2c: The struct octeon_i2c
	133	* @eop_reg: Register selector
	134	* @data: Value to be written
	135	*
	136	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	137	*/
	138	static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
	139	{
493ff7e2	140	int tries = 1000;
ad83665b JG	141	u64 tmp;
ad83665b JG	142
97d97004	143	__raw_writeq(SW_TWSI_V \| eop_reg \| data, i2c->twsi_base + SW_TWSI(i2c));
dfa2ccc3 JG	144	do {
dfa2ccc3 JG	145	tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
493ff7e2 JG	146	if (--tries < 0)
493ff7e2 JG	147	return;
dfa2ccc3	148	} while ((tmp & SW_TWSI_V) != 0);
ad83665b JG	149	}
	150
	151	#define octeon_i2c_ctl_write(i2c, val) \
	152	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
	153	#define octeon_i2c_data_write(i2c, val) \
	154	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
	155
	156	/**
	157	* octeon_i2c_reg_read - read lower bits of an I2C core register
	158	* @i2c: The struct octeon_i2c
	159	* @eop_reg: Register selector
	160	*
	161	* Returns the data.
	162	*
	163	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	164	*/
493ff7e2 JG	165	static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
493ff7e2 JG	166	int *error)
ad83665b	167	{
493ff7e2	168	int tries = 1000;
ad83665b JG	169	u64 tmp;
ad83665b JG	170
97d97004	171	__raw_writeq(SW_TWSI_V \| eop_reg \| SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));
dfa2ccc3 JG	172	do {
dfa2ccc3 JG	173	tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
493ff7e2 JG	174	if (--tries < 0) {
	175	/* signal that the returned data is invalid */
	176	if (error)
	177	*error = -EIO;
	178	return 0;
	179	}
dfa2ccc3	180	} while ((tmp & SW_TWSI_V) != 0);
ad83665b JG	181
	182	return tmp & 0xFF;
	183	}
	184
	185	#define octeon_i2c_ctl_read(i2c) \
493ff7e2 JG	186	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
	187	#define octeon_i2c_data_read(i2c, error) \
	188	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
ad83665b	189	#define octeon_i2c_stat_read(i2c) \
493ff7e2	190	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
ad83665b JG	191
	192	/**
	193	* octeon_i2c_read_int - read the TWSI_INT register
	194	* @i2c: The struct octeon_i2c
	195	*
	196	* Returns the value of the register.
	197	*/
	198	static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
	199	{
97d97004	200	return __raw_readq(i2c->twsi_base + TWSI_INT(i2c));
ad83665b JG	201	}
	202
	203	/**
	204	* octeon_i2c_write_int - write the TWSI_INT register
	205	* @i2c: The struct octeon_i2c
	206	* @data: Value to be written
	207	*/
	208	static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
	209	{
97d97004	210	octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));
ad83665b JG	211	}
	212
	213	/* Prototypes */
	214	irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
	215	int octeon_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num);
	216	int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
	217	void octeon_i2c_set_clock(struct octeon_i2c *i2c);
	218	extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;