[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-octeon-platdrv.c

/*
 * (C) Copyright 2009-2010
 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
 *
 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
 *
 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/atomic.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/slab.h>

#include <asm/octeon/octeon.h>
#include "i2c-octeon-core.h"

#define DRV_NAME "i2c-octeon"

/**
 * octeon_i2c_int_enable - enable the CORE interrupt
 * @i2c: The struct octeon_i2c
 *
 * The interrupt will be asserted when there is non-STAT_IDLE state in
 * the SW_TWSI_EOP_TWSI_STAT register.
 */
static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
{
	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
}

/* disable the CORE interrupt */
static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
{
	/* clear TS/ST/IFLG events */
	octeon_i2c_write_int(i2c, 0);
}

/**
 * octeon_i2c_int_enable78 - enable the CORE interrupt
 * @i2c: The struct octeon_i2c
 *
 * The interrupt will be asserted when there is non-STAT_IDLE state in the
 * SW_TWSI_EOP_TWSI_STAT register.
 */
static void octeon_i2c_int_enable78(struct octeon_i2c *i2c)
{
	atomic_inc_return(&i2c->int_enable_cnt);
	enable_irq(i2c->irq);
}

static void __octeon_i2c_irq_disable(atomic_t *cnt, int irq)
{
	int count;

	/*
	 * The interrupt can be disabled in two places, but we only
	 * want to make the disable_irq_nosync() call once, so keep
	 * track with the atomic variable.
	 */
	count = atomic_dec_if_positive(cnt);
	if (count >= 0)
		disable_irq_nosync(irq);
}

/* disable the CORE interrupt */
static void octeon_i2c_int_disable78(struct octeon_i2c *i2c)
{
	__octeon_i2c_irq_disable(&i2c->int_enable_cnt, i2c->irq);
}

/**
 * octeon_i2c_hlc_int_enable78 - enable the ST interrupt
 * @i2c: The struct octeon_i2c
 *
 * The interrupt will be asserted when there is non-STAT_IDLE state in
 * the SW_TWSI_EOP_TWSI_STAT register.
 */
static void octeon_i2c_hlc_int_enable78(struct octeon_i2c *i2c)
{
	atomic_inc_return(&i2c->hlc_int_enable_cnt);
	enable_irq(i2c->hlc_irq);
}

/* disable the ST interrupt */
static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
{
	__octeon_i2c_irq_disable(&i2c->hlc_int_enable_cnt, i2c->hlc_irq);
}

/* HLC interrupt service routine */
static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
{
	struct octeon_i2c *i2c = dev_id;

	i2c->hlc_int_disable(i2c);
	wake_up(&i2c->queue);

	return IRQ_HANDLED;
}

static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
{
	octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
}

static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
	       I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
}

static const struct i2c_algorithm octeon_i2c_algo = {
	.master_xfer = octeon_i2c_xfer,
	.functionality = octeon_i2c_functionality,
};

static struct i2c_adapter octeon_i2c_ops = {
	.owner = THIS_MODULE,
	.name = "OCTEON adapter",
	.algo = &octeon_i2c_algo,
};

static int octeon_i2c_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	int irq, result = 0, hlc_irq = 0;
	struct resource *res_mem;
	struct octeon_i2c *i2c;
	bool cn78xx_style;

	cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-twsi");
	if (cn78xx_style) {
		hlc_irq = platform_get_irq(pdev, 0);
		if (hlc_irq < 0)
			return hlc_irq;

		irq = platform_get_irq(pdev, 2);
		if (irq < 0)
			return irq;
	} else {
		/* All adaptors have an irq.  */
		irq = platform_get_irq(pdev, 0);
		if (irq < 0)
			return irq;
	}

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c) {
		result = -ENOMEM;
		goto out;
	}
	i2c->dev = &pdev->dev;

	i2c->roff.sw_twsi = 0x00;
	i2c->roff.twsi_int = 0x10;
	i2c->roff.sw_twsi_ext = 0x18;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
	if (IS_ERR(i2c->twsi_base)) {
		result = PTR_ERR(i2c->twsi_base);
		goto out;
	}

	/*
	 * "clock-rate" is a legacy binding, the official binding is
	 * "clock-frequency".  Try the official one first and then
	 * fall back if it doesn't exist.
	 */
	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
	    of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
		dev_err(i2c->dev,
			"no I2C 'clock-rate' or 'clock-frequency' property\n");
		result = -ENXIO;
		goto out;
	}

	i2c->sys_freq = octeon_get_io_clock_rate();

	init_waitqueue_head(&i2c->queue);

	i2c->irq = irq;

	if (cn78xx_style) {
		i2c->hlc_irq = hlc_irq;

		i2c->int_enable = octeon_i2c_int_enable78;
		i2c->int_disable = octeon_i2c_int_disable78;
		i2c->hlc_int_enable = octeon_i2c_hlc_int_enable78;
		i2c->hlc_int_disable = octeon_i2c_hlc_int_disable78;

		irq_set_status_flags(i2c->irq, IRQ_NOAUTOEN);
		irq_set_status_flags(i2c->hlc_irq, IRQ_NOAUTOEN);

		result = devm_request_irq(&pdev->dev, i2c->hlc_irq,
					  octeon_i2c_hlc_isr78, 0,
					  DRV_NAME, i2c);
		if (result < 0) {
			dev_err(i2c->dev, "failed to attach interrupt\n");
			goto out;
		}
	} else {
		i2c->int_enable = octeon_i2c_int_enable;
		i2c->int_disable = octeon_i2c_int_disable;
		i2c->hlc_int_enable = octeon_i2c_hlc_int_enable;
		i2c->hlc_int_disable = octeon_i2c_int_disable;
	}

	result = devm_request_irq(&pdev->dev, i2c->irq,
				  octeon_i2c_isr, 0, DRV_NAME, i2c);
	if (result < 0) {
		dev_err(i2c->dev, "failed to attach interrupt\n");
		goto out;
	}

	if (OCTEON_IS_MODEL(OCTEON_CN38XX))
		i2c->broken_irq_check = true;

	result = octeon_i2c_init_lowlevel(i2c);
	if (result) {
		dev_err(i2c->dev, "init low level failed\n");
		goto  out;
	}

	octeon_i2c_set_clock(i2c);

	i2c->adap = octeon_i2c_ops;
	i2c->adap.timeout = msecs_to_jiffies(2);
	i2c->adap.retries = 5;
	i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = node;
	i2c_set_adapdata(&i2c->adap, i2c);
	platform_set_drvdata(pdev, i2c);

	result = i2c_add_adapter(&i2c->adap);
	if (result < 0)
		goto out;
	dev_info(i2c->dev, "probed\n");
	return 0;

out:
	return result;
};

static int octeon_i2c_remove(struct platform_device *pdev)
{
	struct octeon_i2c *i2c = platform_get_drvdata(pdev);

	i2c_del_adapter(&i2c->adap);
	return 0;
};

static const struct of_device_id octeon_i2c_match[] = {
	{ .compatible = "cavium,octeon-3860-twsi", },
	{ .compatible = "cavium,octeon-7890-twsi", },
	{},
};
MODULE_DEVICE_TABLE(of, octeon_i2c_match);

static struct platform_driver octeon_i2c_driver = {
	.probe		= octeon_i2c_probe,
	.remove		= octeon_i2c_remove,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = octeon_i2c_match,
	},
};

module_platform_driver(octeon_i2c_driver);

MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
MODULE_LICENSE("GPL");
Commit	Line	Data
85660f43 RB	1	/*
	2	* (C) Copyright 2009-2010
	3	* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
	4	*
dfcd8212	5	* Portions Copyright (C) 2010 - 2016 Cavium, Inc.
85660f43 RB	6	*
	7	* This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
4729cbe0	14	#include <linux/atomic.h>
caa505f2 JG	15	#include <linux/delay.h>
caa505f2 JG	16	#include <linux/i2c.h>
f353a218	17	#include <linux/interrupt.h>
caa505f2	18	#include <linux/io.h>
85660f43 RB	19	#include <linux/kernel.h>
85660f43 RB	20	#include <linux/module.h>
caa505f2 JG	21	#include <linux/of.h>
caa505f2 JG	22	#include <linux/platform_device.h>
85660f43	23	#include <linux/sched.h>
5a0e3ad6	24	#include <linux/slab.h>
85660f43 RB	25
85660f43 RB	26	#include <asm/octeon/octeon.h>
ad83665b	27	#include "i2c-octeon-core.h"
85660f43 RB	28
	29	#define DRV_NAME "i2c-octeon"
	30
85660f43	31	/**
bd7784c2 JG	32	* octeon_i2c_int_enable - enable the CORE interrupt
bd7784c2 JG	33	* @i2c: The struct octeon_i2c
85660f43 RB	34	*
	35	* The interrupt will be asserted when there is non-STAT_IDLE state in
	36	* the SW_TWSI_EOP_TWSI_STAT register.
	37	*/
	38	static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
	39	{
dfcd8212	40	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
85660f43 RB	41	}
85660f43 RB	42
bd7784c2	43	/* disable the CORE interrupt */
85660f43 RB	44	static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
85660f43 RB	45	{
dfcd8212	46	/* clear TS/ST/IFLG events */
85660f43 RB	47	octeon_i2c_write_int(i2c, 0);
	48	}
	49
4729cbe0 JG	50	/**
	51	* octeon_i2c_int_enable78 - enable the CORE interrupt
	52	* @i2c: The struct octeon_i2c
	53	*
	54	* The interrupt will be asserted when there is non-STAT_IDLE state in the
	55	* SW_TWSI_EOP_TWSI_STAT register.
	56	*/
	57	static void octeon_i2c_int_enable78(struct octeon_i2c *i2c)
	58	{
	59	atomic_inc_return(&i2c->int_enable_cnt);
	60	enable_irq(i2c->irq);
	61	}
	62
	63	static void __octeon_i2c_irq_disable(atomic_t *cnt, int irq)
	64	{
	65	int count;
	66
	67	/*
	68	* The interrupt can be disabled in two places, but we only
	69	* want to make the disable_irq_nosync() call once, so keep
	70	* track with the atomic variable.
	71	*/
	72	count = atomic_dec_if_positive(cnt);
	73	if (count >= 0)
	74	disable_irq_nosync(irq);
	75	}
	76
	77	/* disable the CORE interrupt */
	78	static void octeon_i2c_int_disable78(struct octeon_i2c *i2c)
	79	{
	80	__octeon_i2c_irq_disable(&i2c->int_enable_cnt, i2c->irq);
	81	}
	82
	83	/**
	84	* octeon_i2c_hlc_int_enable78 - enable the ST interrupt
	85	* @i2c: The struct octeon_i2c
	86	*
	87	* The interrupt will be asserted when there is non-STAT_IDLE state in
	88	* the SW_TWSI_EOP_TWSI_STAT register.
	89	*/
	90	static void octeon_i2c_hlc_int_enable78(struct octeon_i2c *i2c)
	91	{
	92	atomic_inc_return(&i2c->hlc_int_enable_cnt);
	93	enable_irq(i2c->hlc_irq);
	94	}
	95
	96	/* disable the ST interrupt */
	97	static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
	98	{
	99	__octeon_i2c_irq_disable(&i2c->hlc_int_enable_cnt, i2c->hlc_irq);
	100	}
	101
4729cbe0 JG	102	/* HLC interrupt service routine */
	103	static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
	104	{
	105	struct octeon_i2c *i2c = dev_id;
	106
	107	i2c->hlc_int_disable(i2c);
2637e5fd	108	wake_up(&i2c->queue);
85660f43 RB	109
	110	return IRQ_HANDLED;
	111	}
	112
d1fbff89 DD	113	static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
	114	{
	115	octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
	116	}
	117
85660f43 RB	118	static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
85660f43 RB	119	{
392d01de	120	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) \|
886f6f83	121	I2C_FUNC_SMBUS_READ_BLOCK_DATA \| I2C_SMBUS_BLOCK_PROC_CALL;
85660f43 RB	122	}
	123
	124	static const struct i2c_algorithm octeon_i2c_algo = {
	125	.master_xfer = octeon_i2c_xfer,
	126	.functionality = octeon_i2c_functionality,
	127	};
	128
	129	static struct i2c_adapter octeon_i2c_ops = {
	130	.owner = THIS_MODULE,
	131	.name = "OCTEON adapter",
	132	.algo = &octeon_i2c_algo,
85660f43 RB	133	};
85660f43 RB	134
0b255e92	135	static int octeon_i2c_probe(struct platform_device *pdev)
85660f43	136	{
dfcd8212	137	struct device_node *node = pdev->dev.of_node;
4729cbe0	138	int irq, result = 0, hlc_irq = 0;
85660f43	139	struct resource *res_mem;
dfcd8212	140	struct octeon_i2c *i2c;
4729cbe0 JG	141	bool cn78xx_style;
	142
	143	cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-twsi");
	144	if (cn78xx_style) {
	145	hlc_irq = platform_get_irq(pdev, 0);
	146	if (hlc_irq < 0)
	147	return hlc_irq;
85660f43	148
4729cbe0 JG	149	irq = platform_get_irq(pdev, 2);
	150	if (irq < 0)
	151	return irq;
	152	} else {
	153	/* All adaptors have an irq. */
	154	irq = platform_get_irq(pdev, 0);
	155	if (irq < 0)
	156	return irq;
	157	}
85660f43	158
f353a218	159	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
85660f43	160	if (!i2c) {
85660f43 RB	161	result = -ENOMEM;
	162	goto out;
	163	}
	164	i2c->dev = &pdev->dev;
85660f43	165
97d97004 JG	166	i2c->roff.sw_twsi = 0x00;
	167	i2c->roff.twsi_int = 0x10;
	168	i2c->roff.sw_twsi_ext = 0x18;
	169
85660f43	170	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
54108e56 JG	171	i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
	172	if (IS_ERR(i2c->twsi_base)) {
	173	result = PTR_ERR(i2c->twsi_base);
f353a218	174	goto out;
85660f43 RB	175	}
85660f43 RB	176
f353a218 DD	177	/*
	178	* "clock-rate" is a legacy binding, the official binding is
	179	* "clock-frequency". Try the official one first and then
	180	* fall back if it doesn't exist.
	181	*/
dfcd8212 JG	182	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
dfcd8212 JG	183	of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
f353a218 DD	184	dev_err(i2c->dev,
f353a218 DD	185	"no I2C 'clock-rate' or 'clock-frequency' property\n");
85660f43	186	result = -ENXIO;
f353a218	187	goto out;
85660f43 RB	188	}
85660f43 RB	189
f353a218	190	i2c->sys_freq = octeon_get_io_clock_rate();
85660f43	191
85660f43 RB	192	init_waitqueue_head(&i2c->queue);
	193
	194	i2c->irq = irq;
	195
4729cbe0 JG	196	if (cn78xx_style) {
	197	i2c->hlc_irq = hlc_irq;
	198
	199	i2c->int_enable = octeon_i2c_int_enable78;
	200	i2c->int_disable = octeon_i2c_int_disable78;
	201	i2c->hlc_int_enable = octeon_i2c_hlc_int_enable78;
	202	i2c->hlc_int_disable = octeon_i2c_hlc_int_disable78;
	203
	204	irq_set_status_flags(i2c->irq, IRQ_NOAUTOEN);
	205	irq_set_status_flags(i2c->hlc_irq, IRQ_NOAUTOEN);
	206
	207	result = devm_request_irq(&pdev->dev, i2c->hlc_irq,
	208	octeon_i2c_hlc_isr78, 0,
	209	DRV_NAME, i2c);
	210	if (result < 0) {
	211	dev_err(i2c->dev, "failed to attach interrupt\n");
	212	goto out;
	213	}
	214	} else {
	215	i2c->int_enable = octeon_i2c_int_enable;
	216	i2c->int_disable = octeon_i2c_int_disable;
	217	i2c->hlc_int_enable = octeon_i2c_hlc_int_enable;
	218	i2c->hlc_int_disable = octeon_i2c_int_disable;
	219	}
	220
f353a218 DD	221	result = devm_request_irq(&pdev->dev, i2c->irq,
f353a218 DD	222	octeon_i2c_isr, 0, DRV_NAME, i2c);
85660f43 RB	223	if (result < 0) {
85660f43 RB	224	dev_err(i2c->dev, "failed to attach interrupt\n");
f353a218	225	goto out;
85660f43 RB	226	}
85660f43 RB	227
fe600cf6 DD	228	if (OCTEON_IS_MODEL(OCTEON_CN38XX))
	229	i2c->broken_irq_check = true;
	230
dfcd8212	231	result = octeon_i2c_init_lowlevel(i2c);
85660f43 RB	232	if (result) {
85660f43 RB	233	dev_err(i2c->dev, "init low level failed\n");
f353a218	234	goto out;
85660f43 RB	235	}
85660f43 RB	236
dfcd8212	237	octeon_i2c_set_clock(i2c);
85660f43 RB	238
85660f43 RB	239	i2c->adap = octeon_i2c_ops;
a035d71b JG	240	i2c->adap.timeout = msecs_to_jiffies(2);
a035d71b JG	241	i2c->adap.retries = 5;
c981e34e	242	i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
85660f43	243	i2c->adap.dev.parent = &pdev->dev;
dfcd8212	244	i2c->adap.dev.of_node = node;
85660f43 RB	245	i2c_set_adapdata(&i2c->adap, i2c);
	246	platform_set_drvdata(pdev, i2c);
	247
f353a218	248	result = i2c_add_adapter(&i2c->adap);
ea734404	249	if (result < 0)
55827f4a	250	goto out;
dfcd8212	251	dev_info(i2c->dev, "probed\n");
f353a218	252	return 0;
85660f43	253
85660f43 RB	254	out:
	255	return result;
	256	};
	257
0b255e92	258	static int octeon_i2c_remove(struct platform_device *pdev)
85660f43 RB	259	{
	260	struct octeon_i2c *i2c = platform_get_drvdata(pdev);
	261
	262	i2c_del_adapter(&i2c->adap);
85660f43 RB	263	return 0;
	264	};
	265
dfcd8212 JG	266	static const struct of_device_id octeon_i2c_match[] = {
dfcd8212 JG	267	{ .compatible = "cavium,octeon-3860-twsi", },
4729cbe0	268	{ .compatible = "cavium,octeon-7890-twsi", },
f353a218 DD	269	{},
	270	};
	271	MODULE_DEVICE_TABLE(of, octeon_i2c_match);
	272
85660f43 RB	273	static struct platform_driver octeon_i2c_driver = {
85660f43 RB	274	.probe = octeon_i2c_probe,
0b255e92	275	.remove = octeon_i2c_remove,
85660f43	276	.driver = {
85660f43	277	.name = DRV_NAME,
f353a218	278	.of_match_table = octeon_i2c_match,
85660f43 RB	279	},
	280	};
	281
a3664b51	282	module_platform_driver(octeon_i2c_driver);
85660f43 RB	283
	284	MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
	285	MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
	286	MODULE_LICENSE("GPL");