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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
010d442c KS |
25 | */ |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/completion.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/clk.h> | |
c1a473bd | 35 | #include <linux/io.h> |
6145197b | 36 | #include <linux/of.h> |
6145197b | 37 | #include <linux/of_device.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
79fc540f | 39 | #include <linux/platform_data/i2c-omap.h> |
27b1fec2 | 40 | #include <linux/pm_runtime.h> |
096ea30c | 41 | #include <linux/pinctrl/consumer.h> |
010d442c | 42 | |
9c76b878 | 43 | /* I2C controller revisions */ |
4e80f727 | 44 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
45 | |
46 | /* I2C controller revisions present on specific hardware */ | |
47dcd016 S |
47 | #define OMAP_I2C_REV_ON_2430 0x00000036 |
48 | #define OMAP_I2C_REV_ON_3430_3530 0x0000003C | |
49 | #define OMAP_I2C_REV_ON_3630 0x00000040 | |
50 | #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 | |
9c76b878 | 51 | |
010d442c KS |
52 | /* timeout waiting for the controller to respond */ |
53 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
54 | ||
6d8451d5 FB |
55 | /* timeout for pm runtime autosuspend */ |
56 | #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ | |
57 | ||
0f5768bf AK |
58 | /* timeout for making decision on bus free status */ |
59 | #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10)) | |
60 | ||
5043e9e7 | 61 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
62 | enum { |
63 | OMAP_I2C_REV_REG = 0, | |
64 | OMAP_I2C_IE_REG, | |
65 | OMAP_I2C_STAT_REG, | |
66 | OMAP_I2C_IV_REG, | |
67 | OMAP_I2C_WE_REG, | |
68 | OMAP_I2C_SYSS_REG, | |
69 | OMAP_I2C_BUF_REG, | |
70 | OMAP_I2C_CNT_REG, | |
71 | OMAP_I2C_DATA_REG, | |
72 | OMAP_I2C_SYSC_REG, | |
73 | OMAP_I2C_CON_REG, | |
74 | OMAP_I2C_OA_REG, | |
75 | OMAP_I2C_SA_REG, | |
76 | OMAP_I2C_PSC_REG, | |
77 | OMAP_I2C_SCLL_REG, | |
78 | OMAP_I2C_SCLH_REG, | |
79 | OMAP_I2C_SYSTEST_REG, | |
80 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
81 | /* only on OMAP4430 */ |
82 | OMAP_I2C_IP_V2_REVNB_LO, | |
83 | OMAP_I2C_IP_V2_REVNB_HI, | |
84 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
85 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
86 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 87 | }; |
010d442c KS |
88 | |
89 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
90 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
91 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
92 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
93 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
94 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
95 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
96 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
97 | ||
98 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
99 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
100 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
101 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
102 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
103 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
104 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
9fd6ada8 | 105 | #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */ |
010d442c KS |
106 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
107 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
108 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
109 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
110 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
111 | ||
5043e9e7 KJ |
112 | /* I2C WE wakeup enable register */ |
113 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
114 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
115 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
116 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
117 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
118 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
119 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
120 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
121 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
122 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
123 | ||
124 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
125 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
126 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
127 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
128 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
129 | ||
010d442c KS |
130 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
131 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 132 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 133 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 134 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
135 | |
136 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
137 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
138 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 139 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
140 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
141 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
142 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
143 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
144 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
145 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
146 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
147 | ||
4574eb68 SMK |
148 | /* I2C SCL time value when Master */ |
149 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
150 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
151 | ||
010d442c | 152 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
010d442c KS |
153 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ |
154 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
155 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
156 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
9fd6ada8 AK |
157 | /* Functional mode */ |
158 | #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */ | |
159 | #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */ | |
160 | #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */ | |
161 | #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */ | |
162 | /* SDA/SCL IO mode */ | |
010d442c KS |
163 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ |
164 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
165 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
166 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
010d442c | 167 | |
fdd07fe6 PW |
168 | /* OCP_SYSSTATUS bit definitions */ |
169 | #define SYSS_RESETDONE_MASK (1 << 0) | |
170 | ||
171 | /* OCP_SYSCONFIG bit definitions */ | |
172 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
173 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
174 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
175 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
176 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
177 | ||
178 | #define SYSC_IDLEMODE_SMART 0x2 | |
179 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 180 | |
f3083d92 | 181 | /* Errata definitions */ |
182 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
c8db38f0 | 183 | #define I2C_OMAP_ERRATA_I462 (1 << 1) |
010d442c | 184 | |
4368de19 OD |
185 | #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF |
186 | ||
010d442c KS |
187 | struct omap_i2c_dev { |
188 | struct device *dev; | |
189 | void __iomem *base; /* virtual */ | |
190 | int irq; | |
d84d3ea3 | 191 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
192 | struct completion cmd_complete; |
193 | struct resource *ioarea; | |
49839dc9 PW |
194 | u32 latency; /* maximum mpu wkup latency */ |
195 | void (*set_mpu_wkup_lat)(struct device *dev, | |
196 | long latency); | |
6145197b | 197 | u32 speed; /* Speed of bus in kHz */ |
6145197b | 198 | u32 flags; |
4368de19 | 199 | u16 scheme; |
010d442c KS |
200 | u16 cmd_err; |
201 | u8 *buf; | |
f38e66e0 | 202 | u8 *regs; |
010d442c KS |
203 | size_t buf_len; |
204 | struct i2c_adapter adapter; | |
dd74548d | 205 | u8 threshold; |
b6ee52c3 NM |
206 | u8 fifo_size; /* use as flag and value |
207 | * fifo_size==0 implies no fifo | |
208 | * if set, should be trsh+1 | |
209 | */ | |
47dcd016 | 210 | u32 rev; |
b6ee52c3 | 211 | unsigned b_hw:1; /* bad h/w fixes */ |
0f5768bf AK |
212 | unsigned bb_valid:1; /* true when BB-bit reflects |
213 | * the I2C bus state | |
214 | */ | |
079d8af2 | 215 | unsigned receiver:1; /* true when we're in receiver mode */ |
f08ac4e7 | 216 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
217 | u16 pscstate; |
218 | u16 scllstate; | |
219 | u16 sclhstate; | |
ef871432 RN |
220 | u16 syscstate; |
221 | u16 westate; | |
f3083d92 | 222 | u16 errata; |
010d442c KS |
223 | }; |
224 | ||
a1295577 | 225 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
226 | [OMAP_I2C_REV_REG] = 0x00, |
227 | [OMAP_I2C_IE_REG] = 0x01, | |
228 | [OMAP_I2C_STAT_REG] = 0x02, | |
229 | [OMAP_I2C_IV_REG] = 0x03, | |
230 | [OMAP_I2C_WE_REG] = 0x03, | |
231 | [OMAP_I2C_SYSS_REG] = 0x04, | |
232 | [OMAP_I2C_BUF_REG] = 0x05, | |
233 | [OMAP_I2C_CNT_REG] = 0x06, | |
234 | [OMAP_I2C_DATA_REG] = 0x07, | |
235 | [OMAP_I2C_SYSC_REG] = 0x08, | |
236 | [OMAP_I2C_CON_REG] = 0x09, | |
237 | [OMAP_I2C_OA_REG] = 0x0a, | |
238 | [OMAP_I2C_SA_REG] = 0x0b, | |
239 | [OMAP_I2C_PSC_REG] = 0x0c, | |
240 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
241 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
242 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
243 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
244 | }; | |
245 | ||
a1295577 | 246 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
247 | [OMAP_I2C_REV_REG] = 0x04, |
248 | [OMAP_I2C_IE_REG] = 0x2c, | |
249 | [OMAP_I2C_STAT_REG] = 0x28, | |
250 | [OMAP_I2C_IV_REG] = 0x34, | |
251 | [OMAP_I2C_WE_REG] = 0x34, | |
252 | [OMAP_I2C_SYSS_REG] = 0x90, | |
253 | [OMAP_I2C_BUF_REG] = 0x94, | |
254 | [OMAP_I2C_CNT_REG] = 0x98, | |
255 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 256 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
257 | [OMAP_I2C_CON_REG] = 0xa4, |
258 | [OMAP_I2C_OA_REG] = 0xa8, | |
259 | [OMAP_I2C_SA_REG] = 0xac, | |
260 | [OMAP_I2C_PSC_REG] = 0xb0, | |
261 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
262 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
263 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
264 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
265 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
266 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
267 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
268 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
269 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
270 | }; |
271 | ||
63f8f856 | 272 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap, |
010d442c KS |
273 | int reg, u16 val) |
274 | { | |
63f8f856 FB |
275 | writew_relaxed(val, omap->base + |
276 | (omap->regs[reg] << omap->reg_shift)); | |
010d442c KS |
277 | } |
278 | ||
63f8f856 | 279 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg) |
010d442c | 280 | { |
63f8f856 FB |
281 | return readw_relaxed(omap->base + |
282 | (omap->regs[reg] << omap->reg_shift)); | |
010d442c KS |
283 | } |
284 | ||
63f8f856 | 285 | static void __omap_i2c_init(struct omap_i2c_dev *omap) |
95dd3032 S |
286 | { |
287 | ||
63f8f856 | 288 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); |
95dd3032 S |
289 | |
290 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ | |
63f8f856 | 291 | omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate); |
95dd3032 S |
292 | |
293 | /* SCL low and high time values */ | |
63f8f856 FB |
294 | omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate); |
295 | omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate); | |
296 | if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) | |
297 | omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate); | |
95dd3032 S |
298 | |
299 | /* Take the I2C module out of reset: */ | |
63f8f856 | 300 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); |
95dd3032 | 301 | |
4f734a3a AK |
302 | /* |
303 | * NOTE: right after setting CON_EN, STAT_BB could be 0 while the | |
304 | * bus is busy. It will be changed to 1 on the next IP FCLK clock. | |
305 | * udelay(1) will be enough to fix that. | |
306 | */ | |
307 | ||
95dd3032 S |
308 | /* |
309 | * Don't write to this register if the IE state is 0 as it can | |
310 | * cause deadlock. | |
311 | */ | |
63f8f856 FB |
312 | if (omap->iestate) |
313 | omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate); | |
95dd3032 S |
314 | } |
315 | ||
63f8f856 | 316 | static int omap_i2c_reset(struct omap_i2c_dev *omap) |
010d442c | 317 | { |
010d442c | 318 | unsigned long timeout; |
ca85e248 S |
319 | u16 sysc; |
320 | ||
63f8f856 FB |
321 | if (omap->rev >= OMAP_I2C_OMAP1_REV_2) { |
322 | sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG); | |
ca85e248 | 323 | |
57eb81b1 | 324 | /* Disable I2C controller before soft reset */ |
63f8f856 FB |
325 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, |
326 | omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) & | |
57eb81b1 MG |
327 | ~(OMAP_I2C_CON_EN)); |
328 | ||
63f8f856 | 329 | omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
330 | /* For some reason we need to set the EN bit before the |
331 | * reset done bit gets set. */ | |
332 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
63f8f856 FB |
333 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); |
334 | while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 335 | SYSS_RESETDONE_MASK)) { |
010d442c | 336 | if (time_after(jiffies, timeout)) { |
63f8f856 | 337 | dev_warn(omap->dev, "timeout waiting " |
010d442c KS |
338 | "for controller reset\n"); |
339 | return -ETIMEDOUT; | |
340 | } | |
341 | msleep(1); | |
342 | } | |
fdd07fe6 PW |
343 | |
344 | /* SYSC register is cleared by the reset; rewrite it */ | |
63f8f856 | 345 | omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc); |
fdd07fe6 | 346 | |
63f8f856 | 347 | if (omap->rev > OMAP_I2C_REV_ON_3430_3530) { |
23173eae | 348 | /* Schedule I2C-bus monitoring on the next transfer */ |
63f8f856 | 349 | omap->bb_valid = 0; |
23173eae | 350 | } |
010d442c | 351 | } |
0f5768bf | 352 | |
d6c842ad S |
353 | return 0; |
354 | } | |
355 | ||
63f8f856 | 356 | static int omap_i2c_init(struct omap_i2c_dev *omap) |
d6c842ad S |
357 | { |
358 | u16 psc = 0, scll = 0, sclh = 0; | |
359 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; | |
360 | unsigned long fclk_rate = 12000000; | |
361 | unsigned long internal_clk = 0; | |
362 | struct clk *fclk; | |
883b3b65 | 363 | int error; |
d6c842ad | 364 | |
63f8f856 | 365 | if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) { |
d6c842ad S |
366 | /* |
367 | * Enabling all wakup sources to stop I2C freezing on | |
368 | * WFI instruction. | |
369 | * REVISIT: Some wkup sources might not be needed. | |
370 | */ | |
63f8f856 | 371 | omap->westate = OMAP_I2C_WE_ALL; |
d6c842ad | 372 | } |
010d442c | 373 | |
63f8f856 | 374 | if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
375 | /* |
376 | * The I2C functional clock is the armxor_ck, so there's | |
377 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
378 | * always returns 12MHz for the functional clock, we can | |
379 | * do this bit unconditionally. | |
380 | */ | |
63f8f856 | 381 | fclk = clk_get(omap->dev, "fck"); |
883b3b65 TL |
382 | if (IS_ERR(fclk)) { |
383 | error = PTR_ERR(fclk); | |
384 | dev_err(omap->dev, "could not get fck: %i\n", error); | |
385 | ||
386 | return error; | |
387 | } | |
388 | ||
27b1fec2 RN |
389 | fclk_rate = clk_get_rate(fclk); |
390 | clk_put(fclk); | |
0e9ae109 | 391 | |
010d442c KS |
392 | /* TRM for 5912 says the I2C clock must be prescaled to be |
393 | * between 7 - 12 MHz. The XOR input clock is typically | |
394 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
395 | * | |
396 | * XOR MHz Divider Prescaler | |
397 | * 12 1 0 | |
398 | * 13 2 1 | |
399 | * 19.2 2 1 | |
400 | */ | |
d7aef138 JD |
401 | if (fclk_rate > 12000000) |
402 | psc = fclk_rate / 12000000; | |
010d442c KS |
403 | } |
404 | ||
63f8f856 | 405 | if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 406 | |
84bf2c86 AK |
407 | /* |
408 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
409 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
410 | * to get longer filter period for better noise suppression. | |
411 | * The filter is iclk (fclk for HS) period. | |
412 | */ | |
63f8f856 FB |
413 | if (omap->speed > 400 || |
414 | omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) | |
84bf2c86 | 415 | internal_clk = 19200; |
63f8f856 | 416 | else if (omap->speed > 100) |
84bf2c86 AK |
417 | internal_clk = 9600; |
418 | else | |
419 | internal_clk = 4000; | |
63f8f856 | 420 | fclk = clk_get(omap->dev, "fck"); |
883b3b65 TL |
421 | if (IS_ERR(fclk)) { |
422 | error = PTR_ERR(fclk); | |
423 | dev_err(omap->dev, "could not get fck: %i\n", error); | |
424 | ||
425 | return error; | |
426 | } | |
27b1fec2 RN |
427 | fclk_rate = clk_get_rate(fclk) / 1000; |
428 | clk_put(fclk); | |
4574eb68 SMK |
429 | |
430 | /* Compute prescaler divisor */ | |
431 | psc = fclk_rate / internal_clk; | |
432 | psc = psc - 1; | |
433 | ||
434 | /* If configured for High Speed */ | |
63f8f856 | 435 | if (omap->speed > 400) { |
baf46b4e AK |
436 | unsigned long scl; |
437 | ||
4574eb68 | 438 | /* For first phase of HS mode */ |
baf46b4e AK |
439 | scl = internal_clk / 400; |
440 | fsscll = scl - (scl / 3) - 7; | |
441 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
442 | |
443 | /* For second phase of HS mode */ | |
63f8f856 | 444 | scl = fclk_rate / omap->speed; |
baf46b4e AK |
445 | hsscll = scl - (scl / 3) - 7; |
446 | hssclh = (scl / 3) - 5; | |
63f8f856 | 447 | } else if (omap->speed > 100) { |
baf46b4e AK |
448 | unsigned long scl; |
449 | ||
450 | /* Fast mode */ | |
63f8f856 | 451 | scl = internal_clk / omap->speed; |
baf46b4e AK |
452 | fsscll = scl - (scl / 3) - 7; |
453 | fssclh = (scl / 3) - 5; | |
4574eb68 | 454 | } else { |
baf46b4e | 455 | /* Standard mode */ |
63f8f856 FB |
456 | fsscll = internal_clk / (omap->speed * 2) - 7; |
457 | fssclh = internal_clk / (omap->speed * 2) - 5; | |
4574eb68 SMK |
458 | } |
459 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
460 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
461 | } else { | |
462 | /* Program desired operating rate */ | |
463 | fclk_rate /= (psc + 1) * 1000; | |
464 | if (psc > 2) | |
465 | psc = 2; | |
63f8f856 FB |
466 | scll = fclk_rate / (omap->speed * 2) - 7 + psc; |
467 | sclh = fclk_rate / (omap->speed * 2) - 7 + psc; | |
4574eb68 SMK |
468 | } |
469 | ||
63f8f856 | 470 | omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd | 471 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
63f8f856 | 472 | OMAP_I2C_IE_AL) | ((omap->fifo_size) ? |
ef871432 | 473 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
95dd3032 | 474 | |
63f8f856 FB |
475 | omap->pscstate = psc; |
476 | omap->scllstate = scll; | |
477 | omap->sclhstate = sclh; | |
95dd3032 | 478 | |
63f8f856 | 479 | if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) { |
0f5768bf | 480 | /* Not implemented */ |
63f8f856 | 481 | omap->bb_valid = 1; |
0f5768bf AK |
482 | } |
483 | ||
63f8f856 | 484 | __omap_i2c_init(omap); |
95dd3032 | 485 | |
010d442c KS |
486 | return 0; |
487 | } | |
488 | ||
93367bfc CF |
489 | /* |
490 | * Try bus recovery, but only if SDA is actually low. | |
491 | */ | |
492 | static int omap_i2c_recover_bus(struct omap_i2c_dev *omap) | |
493 | { | |
494 | u16 systest; | |
495 | ||
496 | systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG); | |
497 | if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && | |
498 | (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) | |
499 | return 0; /* bus seems to already be fine */ | |
500 | if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC)) | |
501 | return -EBUSY; /* recovery would not fix SCL */ | |
502 | return i2c_recover_bus(&omap->adapter); | |
503 | } | |
504 | ||
010d442c KS |
505 | /* |
506 | * Waiting on Bus Busy | |
507 | */ | |
63f8f856 | 508 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap) |
010d442c KS |
509 | { |
510 | unsigned long timeout; | |
511 | ||
512 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
63f8f856 | 513 | while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { |
9dcb0e7b | 514 | if (time_after(jiffies, timeout)) |
93367bfc | 515 | return omap_i2c_recover_bus(omap); |
010d442c KS |
516 | msleep(1); |
517 | } | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
0f5768bf AK |
522 | /* |
523 | * Wait while BB-bit doesn't reflect the I2C bus state | |
524 | * | |
525 | * In a multimaster environment, after IP software reset, BB-bit value doesn't | |
526 | * correspond to the current bus state. It may happen what BB-bit will be 0, | |
527 | * while the bus is busy due to another I2C master activity. | |
528 | * Here are BB-bit values after reset: | |
529 | * SDA SCL BB NOTES | |
530 | * 0 0 0 1, 2 | |
531 | * 1 0 0 1, 2 | |
532 | * 0 1 1 | |
533 | * 1 1 0 3 | |
534 | * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START) | |
535 | * combinations on the bus, it set BB-bit to 1. | |
536 | * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus, | |
537 | * it set BB-bit to 0 and BF to 1. | |
538 | * BB and BF bits correctly tracks the bus state while IP is suspended | |
539 | * BB bit became valid on the next FCLK clock after CON_EN bit set | |
540 | * | |
541 | * NOTES: | |
542 | * 1. Any transfer started when BB=0 and bus is busy wouldn't be | |
543 | * completed by IP and results in controller timeout. | |
544 | * 2. Any transfer started when BB=0 and SCL=0 results in IP | |
545 | * starting to drive SDA low. In that case IP corrupt data | |
546 | * on the bus. | |
547 | * 3. Any transfer started in the middle of another master's transfer | |
548 | * results in unpredictable results and data corruption | |
549 | */ | |
63f8f856 | 550 | static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap) |
0f5768bf AK |
551 | { |
552 | unsigned long bus_free_timeout = 0; | |
553 | unsigned long timeout; | |
554 | int bus_free = 0; | |
555 | u16 stat, systest; | |
556 | ||
63f8f856 | 557 | if (omap->bb_valid) |
0f5768bf AK |
558 | return 0; |
559 | ||
560 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
561 | while (1) { | |
63f8f856 | 562 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
0f5768bf AK |
563 | /* |
564 | * We will see BB or BF event in a case IP had detected any | |
565 | * activity on the I2C bus. Now IP correctly tracks the bus | |
566 | * state. BB-bit value is valid. | |
567 | */ | |
568 | if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF)) | |
569 | break; | |
570 | ||
571 | /* | |
572 | * Otherwise, we must look signals on the bus to make | |
573 | * the right decision. | |
574 | */ | |
63f8f856 | 575 | systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG); |
0f5768bf AK |
576 | if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) && |
577 | (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) { | |
578 | if (!bus_free) { | |
579 | bus_free_timeout = jiffies + | |
580 | OMAP_I2C_BUS_FREE_TIMEOUT; | |
581 | bus_free = 1; | |
582 | } | |
583 | ||
584 | /* | |
585 | * SDA and SCL lines was high for 10 ms without bus | |
586 | * activity detected. The bus is free. Consider | |
587 | * BB-bit value is valid. | |
588 | */ | |
589 | if (time_after(jiffies, bus_free_timeout)) | |
590 | break; | |
591 | } else { | |
592 | bus_free = 0; | |
593 | } | |
594 | ||
595 | if (time_after(jiffies, timeout)) { | |
93367bfc CF |
596 | /* |
597 | * SDA or SCL were low for the entire timeout without | |
598 | * any activity detected. Most likely, a slave is | |
599 | * locking up the bus with no master driving the clock. | |
600 | */ | |
63f8f856 | 601 | dev_warn(omap->dev, "timeout waiting for bus ready\n"); |
93367bfc | 602 | return omap_i2c_recover_bus(omap); |
0f5768bf AK |
603 | } |
604 | ||
605 | msleep(1); | |
606 | } | |
607 | ||
63f8f856 | 608 | omap->bb_valid = 1; |
0f5768bf AK |
609 | return 0; |
610 | } | |
611 | ||
63f8f856 | 612 | static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx) |
dd74548d FB |
613 | { |
614 | u16 buf; | |
615 | ||
63f8f856 | 616 | if (omap->flags & OMAP_I2C_FLAG_NO_FIFO) |
dd74548d FB |
617 | return; |
618 | ||
619 | /* | |
620 | * Set up notification threshold based on message size. We're doing | |
621 | * this to try and avoid draining feature as much as possible. Whenever | |
622 | * we have big messages to transfer (bigger than our total fifo size) | |
623 | * then we might use draining feature to transfer the remaining bytes. | |
624 | */ | |
625 | ||
63f8f856 | 626 | omap->threshold = clamp(size, (u8) 1, omap->fifo_size); |
dd74548d | 627 | |
63f8f856 | 628 | buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG); |
dd74548d FB |
629 | |
630 | if (is_rx) { | |
631 | /* Clear RX Threshold */ | |
632 | buf &= ~(0x3f << 8); | |
63f8f856 | 633 | buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; |
dd74548d FB |
634 | } else { |
635 | /* Clear TX Threshold */ | |
636 | buf &= ~0x3f; | |
63f8f856 | 637 | buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; |
dd74548d FB |
638 | } |
639 | ||
63f8f856 | 640 | omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf); |
dd74548d | 641 | |
63f8f856 FB |
642 | if (omap->rev < OMAP_I2C_REV_ON_3630) |
643 | omap->b_hw = 1; /* Enable hardware fixes */ | |
dd74548d FB |
644 | |
645 | /* calculate wakeup latency constraint for MPU */ | |
63f8f856 FB |
646 | if (omap->set_mpu_wkup_lat != NULL) |
647 | omap->latency = (1000000 * omap->threshold) / | |
648 | (1000 * omap->speed / 8); | |
dd74548d FB |
649 | } |
650 | ||
010d442c KS |
651 | /* |
652 | * Low level master read/write transaction. | |
653 | */ | |
654 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
655 | struct i2c_msg *msg, int stop) | |
656 | { | |
63f8f856 | 657 | struct omap_i2c_dev *omap = i2c_get_adapdata(adap); |
33d54985 | 658 | unsigned long timeout; |
010d442c KS |
659 | u16 w; |
660 | ||
63f8f856 | 661 | dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", |
010d442c KS |
662 | msg->addr, msg->len, msg->flags, stop); |
663 | ||
664 | if (msg->len == 0) | |
665 | return -EINVAL; | |
666 | ||
63f8f856 FB |
667 | omap->receiver = !!(msg->flags & I2C_M_RD); |
668 | omap_i2c_resize_fifo(omap, msg->len, omap->receiver); | |
dd74548d | 669 | |
63f8f856 | 670 | omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr); |
010d442c KS |
671 | |
672 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
63f8f856 FB |
673 | omap->buf = msg->buf; |
674 | omap->buf_len = msg->len; | |
010d442c | 675 | |
63f8f856 | 676 | /* make sure writes to omap->buf_len are ordered */ |
d60ece5f FB |
677 | barrier(); |
678 | ||
63f8f856 | 679 | omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len); |
010d442c | 680 | |
b6ee52c3 | 681 | /* Clear the FIFO Buffers */ |
63f8f856 | 682 | w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG); |
b6ee52c3 | 683 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; |
63f8f856 | 684 | omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w); |
b6ee52c3 | 685 | |
63f8f856 FB |
686 | reinit_completion(&omap->cmd_complete); |
687 | omap->cmd_err = 0; | |
010d442c KS |
688 | |
689 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
690 | |
691 | /* High speed configuration */ | |
63f8f856 | 692 | if (omap->speed > 400) |
b6ee52c3 | 693 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 694 | |
fb604a3d LP |
695 | if (msg->flags & I2C_M_STOP) |
696 | stop = 1; | |
010d442c KS |
697 | if (msg->flags & I2C_M_TEN) |
698 | w |= OMAP_I2C_CON_XA; | |
699 | if (!(msg->flags & I2C_M_RD)) | |
700 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 701 | |
63f8f856 | 702 | if (!omap->b_hw && stop) |
010d442c | 703 | w |= OMAP_I2C_CON_STP; |
4f734a3a AK |
704 | /* |
705 | * NOTE: STAT_BB bit could became 1 here if another master occupy | |
706 | * the bus. IP successfully complete transfer when the bus will be | |
707 | * free again (BB reset to 0). | |
708 | */ | |
63f8f856 | 709 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); |
010d442c | 710 | |
b6ee52c3 NM |
711 | /* |
712 | * Don't write stt and stp together on some hardware. | |
713 | */ | |
63f8f856 | 714 | if (omap->b_hw && stop) { |
b6ee52c3 | 715 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; |
63f8f856 | 716 | u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); |
b6ee52c3 | 717 | while (con & OMAP_I2C_CON_STT) { |
63f8f856 | 718 | con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); |
b6ee52c3 NM |
719 | |
720 | /* Let the user know if i2c is in a bad state */ | |
721 | if (time_after(jiffies, delay)) { | |
63f8f856 | 722 | dev_err(omap->dev, "controller timed out " |
b6ee52c3 NM |
723 | "waiting for start condition to finish\n"); |
724 | return -ETIMEDOUT; | |
725 | } | |
726 | cpu_relax(); | |
727 | } | |
728 | ||
729 | w |= OMAP_I2C_CON_STP; | |
730 | w &= ~OMAP_I2C_CON_STT; | |
63f8f856 | 731 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); |
b6ee52c3 NM |
732 | } |
733 | ||
b7af349b JN |
734 | /* |
735 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
736 | * into arbitration and we're currently unable to recover from it. | |
737 | */ | |
63f8f856 | 738 | timeout = wait_for_completion_timeout(&omap->cmd_complete, |
33d54985 | 739 | OMAP_I2C_TIMEOUT); |
33d54985 | 740 | if (timeout == 0) { |
63f8f856 FB |
741 | dev_err(omap->dev, "controller timed out\n"); |
742 | omap_i2c_reset(omap); | |
743 | __omap_i2c_init(omap); | |
010d442c KS |
744 | return -ETIMEDOUT; |
745 | } | |
746 | ||
63f8f856 | 747 | if (likely(!omap->cmd_err)) |
010d442c KS |
748 | return 0; |
749 | ||
750 | /* We have an error */ | |
63f8f856 FB |
751 | if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) { |
752 | omap_i2c_reset(omap); | |
753 | __omap_i2c_init(omap); | |
010d442c KS |
754 | return -EIO; |
755 | } | |
756 | ||
63f8f856 | 757 | if (omap->cmd_err & OMAP_I2C_STAT_AL) |
b76911d2 AK |
758 | return -EAGAIN; |
759 | ||
63f8f856 | 760 | if (omap->cmd_err & OMAP_I2C_STAT_NACK) { |
010d442c KS |
761 | if (msg->flags & I2C_M_IGNORE_NAK) |
762 | return 0; | |
cda2109a | 763 | |
63f8f856 | 764 | w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG); |
cda2109a | 765 | w |= OMAP_I2C_CON_STP; |
63f8f856 | 766 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w); |
010d442c KS |
767 | return -EREMOTEIO; |
768 | } | |
769 | return -EIO; | |
770 | } | |
771 | ||
772 | ||
773 | /* | |
774 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
775 | * to do the work during IRQ processing. | |
776 | */ | |
777 | static int | |
778 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
779 | { | |
63f8f856 | 780 | struct omap_i2c_dev *omap = i2c_get_adapdata(adap); |
010d442c KS |
781 | int i; |
782 | int r; | |
783 | ||
63f8f856 | 784 | r = pm_runtime_get_sync(omap->dev); |
ff370257 | 785 | if (r < 0) |
33ec5e81 | 786 | goto out; |
010d442c | 787 | |
63f8f856 | 788 | r = omap_i2c_wait_for_bb_valid(omap); |
0f5768bf AK |
789 | if (r < 0) |
790 | goto out; | |
791 | ||
63f8f856 | 792 | r = omap_i2c_wait_for_bb(omap); |
c1a473bd | 793 | if (r < 0) |
010d442c KS |
794 | goto out; |
795 | ||
63f8f856 FB |
796 | if (omap->set_mpu_wkup_lat != NULL) |
797 | omap->set_mpu_wkup_lat(omap->dev, omap->latency); | |
6a91b558 | 798 | |
010d442c KS |
799 | for (i = 0; i < num; i++) { |
800 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
801 | if (r != 0) | |
802 | break; | |
803 | } | |
804 | ||
805 | if (r == 0) | |
806 | r = num; | |
5c64eb26 | 807 | |
63f8f856 | 808 | omap_i2c_wait_for_bb(omap); |
1ab36045 | 809 | |
63f8f856 FB |
810 | if (omap->set_mpu_wkup_lat != NULL) |
811 | omap->set_mpu_wkup_lat(omap->dev, -1); | |
1ab36045 | 812 | |
010d442c | 813 | out: |
63f8f856 FB |
814 | pm_runtime_mark_last_busy(omap->dev); |
815 | pm_runtime_put_autosuspend(omap->dev); | |
010d442c KS |
816 | return r; |
817 | } | |
818 | ||
819 | static u32 | |
820 | omap_i2c_func(struct i2c_adapter *adap) | |
821 | { | |
fb604a3d LP |
822 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
823 | I2C_FUNC_PROTOCOL_MANGLING; | |
010d442c KS |
824 | } |
825 | ||
826 | static inline void | |
63f8f856 | 827 | omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err) |
010d442c | 828 | { |
63f8f856 FB |
829 | omap->cmd_err |= err; |
830 | complete(&omap->cmd_complete); | |
010d442c KS |
831 | } |
832 | ||
833 | static inline void | |
63f8f856 | 834 | omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat) |
010d442c | 835 | { |
63f8f856 | 836 | omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat); |
010d442c KS |
837 | } |
838 | ||
63f8f856 | 839 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat) |
f3083d92 | 840 | { |
841 | /* | |
842 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
843 | * Not applicable for OMAP4. | |
844 | * Under certain rare conditions, RDR could be set again | |
845 | * when the bus is busy, then ignore the interrupt and | |
846 | * clear the interrupt. | |
847 | */ | |
848 | if (stat & OMAP_I2C_STAT_RDR) { | |
849 | /* Step 1: If RDR is set, clear it */ | |
63f8f856 | 850 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); |
f3083d92 | 851 | |
852 | /* Step 2: */ | |
63f8f856 | 853 | if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) |
f3083d92 | 854 | & OMAP_I2C_STAT_BB)) { |
855 | ||
856 | /* Step 3: */ | |
63f8f856 | 857 | if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) |
f3083d92 | 858 | & OMAP_I2C_STAT_RDR) { |
63f8f856 FB |
859 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); |
860 | dev_dbg(omap->dev, "RDR when bus is busy.\n"); | |
f3083d92 | 861 | } |
862 | ||
863 | } | |
864 | } | |
865 | } | |
866 | ||
43469d8e PW |
867 | /* rev1 devices are apparently only on some 15xx */ |
868 | #ifdef CONFIG_ARCH_OMAP15XX | |
869 | ||
010d442c | 870 | static irqreturn_t |
4e80f727 | 871 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c | 872 | { |
63f8f856 | 873 | struct omap_i2c_dev *omap = dev_id; |
010d442c KS |
874 | u16 iv, w; |
875 | ||
63f8f856 | 876 | if (pm_runtime_suspended(omap->dev)) |
f08ac4e7 TL |
877 | return IRQ_NONE; |
878 | ||
63f8f856 | 879 | iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); |
010d442c KS |
880 | switch (iv) { |
881 | case 0x00: /* None */ | |
882 | break; | |
883 | case 0x01: /* Arbitration lost */ | |
63f8f856 FB |
884 | dev_err(omap->dev, "Arbitration lost\n"); |
885 | omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL); | |
010d442c KS |
886 | break; |
887 | case 0x02: /* No acknowledgement */ | |
63f8f856 FB |
888 | omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK); |
889 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
010d442c KS |
890 | break; |
891 | case 0x03: /* Register access ready */ | |
63f8f856 | 892 | omap_i2c_complete_cmd(omap, 0); |
010d442c KS |
893 | break; |
894 | case 0x04: /* Receive data ready */ | |
63f8f856 FB |
895 | if (omap->buf_len) { |
896 | w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG); | |
897 | *omap->buf++ = w; | |
898 | omap->buf_len--; | |
899 | if (omap->buf_len) { | |
900 | *omap->buf++ = w >> 8; | |
901 | omap->buf_len--; | |
010d442c KS |
902 | } |
903 | } else | |
63f8f856 | 904 | dev_err(omap->dev, "RRDY IRQ while no data requested\n"); |
010d442c KS |
905 | break; |
906 | case 0x05: /* Transmit data ready */ | |
63f8f856 FB |
907 | if (omap->buf_len) { |
908 | w = *omap->buf++; | |
909 | omap->buf_len--; | |
910 | if (omap->buf_len) { | |
911 | w |= *omap->buf++ << 8; | |
912 | omap->buf_len--; | |
010d442c | 913 | } |
63f8f856 | 914 | omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w); |
010d442c | 915 | } else |
63f8f856 | 916 | dev_err(omap->dev, "XRDY IRQ while no data to send\n"); |
010d442c KS |
917 | break; |
918 | default: | |
919 | return IRQ_NONE; | |
920 | } | |
921 | ||
922 | return IRQ_HANDLED; | |
923 | } | |
43469d8e | 924 | #else |
4e80f727 | 925 | #define omap_i2c_omap1_isr NULL |
43469d8e | 926 | #endif |
010d442c | 927 | |
2dd151ab | 928 | /* |
c8db38f0 | 929 | * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing |
2dd151ab AS |
930 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring |
931 | * them from the memory to the I2C interface. | |
932 | */ | |
63f8f856 | 933 | static int errata_omap3_i462(struct omap_i2c_dev *omap) |
2dd151ab | 934 | { |
e9f59b9c | 935 | unsigned long timeout = 10000; |
4151e741 | 936 | u16 stat; |
e9f59b9c | 937 | |
4151e741 | 938 | do { |
63f8f856 | 939 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
4151e741 FB |
940 | if (stat & OMAP_I2C_STAT_XUDF) |
941 | break; | |
942 | ||
943 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
63f8f856 | 944 | omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY | |
2dd151ab | 945 | OMAP_I2C_STAT_XDR)); |
b07be0f3 | 946 | if (stat & OMAP_I2C_STAT_NACK) { |
63f8f856 FB |
947 | omap->cmd_err |= OMAP_I2C_STAT_NACK; |
948 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK); | |
b07be0f3 FB |
949 | } |
950 | ||
951 | if (stat & OMAP_I2C_STAT_AL) { | |
63f8f856 FB |
952 | dev_err(omap->dev, "Arbitration lost\n"); |
953 | omap->cmd_err |= OMAP_I2C_STAT_AL; | |
954 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL); | |
b07be0f3 FB |
955 | } |
956 | ||
4151e741 | 957 | return -EIO; |
2dd151ab | 958 | } |
e9f59b9c | 959 | |
2dd151ab | 960 | cpu_relax(); |
4151e741 | 961 | } while (--timeout); |
2dd151ab | 962 | |
e9f59b9c | 963 | if (!timeout) { |
63f8f856 | 964 | dev_err(omap->dev, "timeout waiting on XUDF bit\n"); |
e9f59b9c AS |
965 | return 0; |
966 | } | |
967 | ||
2dd151ab AS |
968 | return 0; |
969 | } | |
970 | ||
63f8f856 | 971 | static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes, |
3312d25e FB |
972 | bool is_rdr) |
973 | { | |
974 | u16 w; | |
975 | ||
976 | while (num_bytes--) { | |
63f8f856 FB |
977 | w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG); |
978 | *omap->buf++ = w; | |
979 | omap->buf_len--; | |
3312d25e FB |
980 | |
981 | /* | |
982 | * Data reg in 2430, omap3 and | |
983 | * omap4 is 8 bit wide | |
984 | */ | |
63f8f856 FB |
985 | if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { |
986 | *omap->buf++ = w >> 8; | |
987 | omap->buf_len--; | |
3312d25e FB |
988 | } |
989 | } | |
990 | } | |
991 | ||
63f8f856 | 992 | static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes, |
3312d25e FB |
993 | bool is_xdr) |
994 | { | |
995 | u16 w; | |
996 | ||
997 | while (num_bytes--) { | |
63f8f856 FB |
998 | w = *omap->buf++; |
999 | omap->buf_len--; | |
3312d25e FB |
1000 | |
1001 | /* | |
1002 | * Data reg in 2430, omap3 and | |
1003 | * omap4 is 8 bit wide | |
1004 | */ | |
63f8f856 FB |
1005 | if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { |
1006 | w |= *omap->buf++ << 8; | |
1007 | omap->buf_len--; | |
3312d25e FB |
1008 | } |
1009 | ||
63f8f856 | 1010 | if (omap->errata & I2C_OMAP_ERRATA_I462) { |
3312d25e FB |
1011 | int ret; |
1012 | ||
63f8f856 | 1013 | ret = errata_omap3_i462(omap); |
3312d25e FB |
1014 | if (ret < 0) |
1015 | return ret; | |
1016 | } | |
1017 | ||
63f8f856 | 1018 | omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w); |
3312d25e FB |
1019 | } |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
010d442c | 1024 | static irqreturn_t |
3b2f8f82 | 1025 | omap_i2c_isr(int irq, void *dev_id) |
010d442c | 1026 | { |
63f8f856 | 1027 | struct omap_i2c_dev *omap = dev_id; |
3b2f8f82 FB |
1028 | irqreturn_t ret = IRQ_HANDLED; |
1029 | u16 mask; | |
1030 | u16 stat; | |
1031 | ||
63f8f856 | 1032 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
126a66ca | 1033 | mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); |
3b2f8f82 FB |
1034 | |
1035 | if (stat & mask) | |
1036 | ret = IRQ_WAKE_THREAD; | |
1037 | ||
3b2f8f82 FB |
1038 | return ret; |
1039 | } | |
1040 | ||
010d442c | 1041 | static irqreturn_t |
3b2f8f82 | 1042 | omap_i2c_isr_thread(int this_irq, void *dev_id) |
010d442c | 1043 | { |
63f8f856 | 1044 | struct omap_i2c_dev *omap = dev_id; |
010d442c | 1045 | u16 bits; |
3312d25e | 1046 | u16 stat; |
66b92988 | 1047 | int err = 0, count = 0; |
010d442c | 1048 | |
66b92988 | 1049 | do { |
63f8f856 FB |
1050 | bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); |
1051 | stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); | |
66b92988 FB |
1052 | stat &= bits; |
1053 | ||
079d8af2 | 1054 | /* If we're in receiver mode, ignore XDR/XRDY */ |
63f8f856 | 1055 | if (omap->receiver) |
079d8af2 FB |
1056 | stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); |
1057 | else | |
1058 | stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); | |
010d442c | 1059 | |
66b92988 FB |
1060 | if (!stat) { |
1061 | /* my work here is done */ | |
0bdfe0cb | 1062 | goto out; |
66b92988 | 1063 | } |
f08ac4e7 | 1064 | |
63f8f856 | 1065 | dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat); |
010d442c | 1066 | if (count++ == 100) { |
63f8f856 | 1067 | dev_warn(omap->dev, "Too much work in one IRQ\n"); |
010d442c KS |
1068 | break; |
1069 | } | |
1070 | ||
1d7afc95 | 1071 | if (stat & OMAP_I2C_STAT_NACK) { |
b6ee52c3 | 1072 | err |= OMAP_I2C_STAT_NACK; |
63f8f856 | 1073 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK); |
1d7afc95 | 1074 | } |
78e1cf42 | 1075 | |
b6ee52c3 | 1076 | if (stat & OMAP_I2C_STAT_AL) { |
63f8f856 | 1077 | dev_err(omap->dev, "Arbitration lost\n"); |
b6ee52c3 | 1078 | err |= OMAP_I2C_STAT_AL; |
63f8f856 | 1079 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL); |
b6ee52c3 | 1080 | } |
c55edb99 | 1081 | |
a5a595cc | 1082 | /* |
cb527ede | 1083 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 1084 | */ |
4cdbf7d3 | 1085 | if (stat & OMAP_I2C_STAT_ARDY) |
63f8f856 | 1086 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY); |
4cdbf7d3 | 1087 | |
b6ee52c3 | 1088 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 1089 | OMAP_I2C_STAT_AL)) { |
63f8f856 | 1090 | omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY | |
540a4790 FB |
1091 | OMAP_I2C_STAT_RDR | |
1092 | OMAP_I2C_STAT_XRDY | | |
1093 | OMAP_I2C_STAT_XDR | | |
1094 | OMAP_I2C_STAT_ARDY)); | |
0bdfe0cb | 1095 | break; |
04c688dd | 1096 | } |
c55edb99 | 1097 | |
6d9939f6 | 1098 | if (stat & OMAP_I2C_STAT_RDR) { |
b6ee52c3 | 1099 | u8 num_bytes = 1; |
f3083d92 | 1100 | |
63f8f856 FB |
1101 | if (omap->fifo_size) |
1102 | num_bytes = omap->buf_len; | |
6d9939f6 | 1103 | |
63f8f856 FB |
1104 | if (omap->errata & I2C_OMAP_ERRATA_I207) { |
1105 | i2c_omap_errata_i207(omap, stat); | |
1106 | num_bytes = (omap_i2c_read_reg(omap, | |
ccfc8663 AK |
1107 | OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F; |
1108 | } | |
f3083d92 | 1109 | |
63f8f856 FB |
1110 | omap_i2c_receive_data(omap, num_bytes, true); |
1111 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR); | |
9eb13cf3 | 1112 | continue; |
6d9939f6 FB |
1113 | } |
1114 | ||
1115 | if (stat & OMAP_I2C_STAT_RRDY) { | |
1116 | u8 num_bytes = 1; | |
1117 | ||
63f8f856 FB |
1118 | if (omap->threshold) |
1119 | num_bytes = omap->threshold; | |
6d9939f6 | 1120 | |
63f8f856 FB |
1121 | omap_i2c_receive_data(omap, num_bytes, false); |
1122 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY); | |
010d442c KS |
1123 | continue; |
1124 | } | |
c55edb99 | 1125 | |
6d9939f6 | 1126 | if (stat & OMAP_I2C_STAT_XDR) { |
b6ee52c3 | 1127 | u8 num_bytes = 1; |
3312d25e | 1128 | int ret; |
6d9939f6 | 1129 | |
63f8f856 FB |
1130 | if (omap->fifo_size) |
1131 | num_bytes = omap->buf_len; | |
6d9939f6 | 1132 | |
63f8f856 | 1133 | ret = omap_i2c_transmit_data(omap, num_bytes, true); |
3312d25e | 1134 | if (ret < 0) |
0bdfe0cb | 1135 | break; |
6d9939f6 | 1136 | |
63f8f856 | 1137 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR); |
9eb13cf3 | 1138 | continue; |
6d9939f6 FB |
1139 | } |
1140 | ||
1141 | if (stat & OMAP_I2C_STAT_XRDY) { | |
1142 | u8 num_bytes = 1; | |
3312d25e | 1143 | int ret; |
6d9939f6 | 1144 | |
63f8f856 FB |
1145 | if (omap->threshold) |
1146 | num_bytes = omap->threshold; | |
6d9939f6 | 1147 | |
63f8f856 | 1148 | ret = omap_i2c_transmit_data(omap, num_bytes, false); |
3312d25e | 1149 | if (ret < 0) |
0bdfe0cb | 1150 | break; |
6d9939f6 | 1151 | |
63f8f856 | 1152 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY); |
010d442c KS |
1153 | continue; |
1154 | } | |
c55edb99 | 1155 | |
010d442c | 1156 | if (stat & OMAP_I2C_STAT_ROVR) { |
63f8f856 | 1157 | dev_err(omap->dev, "Receive overrun\n"); |
1d7afc95 | 1158 | err |= OMAP_I2C_STAT_ROVR; |
63f8f856 | 1159 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR); |
0bdfe0cb | 1160 | break; |
010d442c | 1161 | } |
c55edb99 | 1162 | |
010d442c | 1163 | if (stat & OMAP_I2C_STAT_XUDF) { |
63f8f856 | 1164 | dev_err(omap->dev, "Transmit underflow\n"); |
1d7afc95 | 1165 | err |= OMAP_I2C_STAT_XUDF; |
63f8f856 | 1166 | omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF); |
0bdfe0cb | 1167 | break; |
010d442c | 1168 | } |
66b92988 | 1169 | } while (stat); |
010d442c | 1170 | |
63f8f856 | 1171 | omap_i2c_complete_cmd(omap, err); |
0bdfe0cb FB |
1172 | |
1173 | out: | |
6a85ced2 | 1174 | return IRQ_HANDLED; |
010d442c KS |
1175 | } |
1176 | ||
8f9082c5 | 1177 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
1178 | .master_xfer = omap_i2c_xfer, |
1179 | .functionality = omap_i2c_func, | |
1180 | }; | |
1181 | ||
6145197b | 1182 | #ifdef CONFIG_OF |
4c624840 TL |
1183 | static struct omap_i2c_bus_platform_data omap2420_pdata = { |
1184 | .rev = OMAP_I2C_IP_VERSION_1, | |
1185 | .flags = OMAP_I2C_FLAG_NO_FIFO | | |
1186 | OMAP_I2C_FLAG_SIMPLE_CLOCK | | |
1187 | OMAP_I2C_FLAG_16BIT_DATA_REG | | |
1188 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
1189 | }; | |
1190 | ||
1191 | static struct omap_i2c_bus_platform_data omap2430_pdata = { | |
1192 | .rev = OMAP_I2C_IP_VERSION_1, | |
1193 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | | |
1194 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, | |
1195 | }; | |
1196 | ||
6145197b BC |
1197 | static struct omap_i2c_bus_platform_data omap3_pdata = { |
1198 | .rev = OMAP_I2C_IP_VERSION_1, | |
972deb4f | 1199 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
6145197b BC |
1200 | }; |
1201 | ||
1202 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
1203 | .rev = OMAP_I2C_IP_VERSION_2, | |
1204 | }; | |
1205 | ||
1206 | static const struct of_device_id omap_i2c_of_match[] = { | |
1207 | { | |
1208 | .compatible = "ti,omap4-i2c", | |
1209 | .data = &omap4_pdata, | |
1210 | }, | |
1211 | { | |
1212 | .compatible = "ti,omap3-i2c", | |
1213 | .data = &omap3_pdata, | |
1214 | }, | |
4c624840 TL |
1215 | { |
1216 | .compatible = "ti,omap2430-i2c", | |
1217 | .data = &omap2430_pdata, | |
1218 | }, | |
1219 | { | |
1220 | .compatible = "ti,omap2420-i2c", | |
1221 | .data = &omap2420_pdata, | |
1222 | }, | |
6145197b BC |
1223 | { }, |
1224 | }; | |
1225 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
1226 | #endif | |
1227 | ||
47dcd016 S |
1228 | #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) |
1229 | ||
1230 | #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) | |
1231 | #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) | |
1232 | ||
1233 | #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) | |
1234 | #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) | |
1235 | #define OMAP_I2C_SCHEME_0 0 | |
1236 | #define OMAP_I2C_SCHEME_1 1 | |
1237 | ||
9dcb0e7b FB |
1238 | static int omap_i2c_get_scl(struct i2c_adapter *adap) |
1239 | { | |
1240 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1241 | u32 reg; | |
1242 | ||
1243 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
1244 | ||
1245 | return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC; | |
1246 | } | |
1247 | ||
1248 | static int omap_i2c_get_sda(struct i2c_adapter *adap) | |
1249 | { | |
1250 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1251 | u32 reg; | |
1252 | ||
1253 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
1254 | ||
1255 | return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC; | |
1256 | } | |
1257 | ||
1258 | static void omap_i2c_set_scl(struct i2c_adapter *adap, int val) | |
1259 | { | |
1260 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1261 | u32 reg; | |
1262 | ||
1263 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
1264 | if (val) | |
1265 | reg |= OMAP_I2C_SYSTEST_SCL_O; | |
1266 | else | |
1267 | reg &= ~OMAP_I2C_SYSTEST_SCL_O; | |
1268 | omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); | |
1269 | } | |
1270 | ||
1271 | static void omap_i2c_prepare_recovery(struct i2c_adapter *adap) | |
1272 | { | |
1273 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1274 | u32 reg; | |
1275 | ||
1276 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
828e66c0 | 1277 | /* enable test mode */ |
9dcb0e7b | 1278 | reg |= OMAP_I2C_SYSTEST_ST_EN; |
828e66c0 JL |
1279 | /* select SDA/SCL IO mode */ |
1280 | reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT; | |
1281 | /* set SCL to high-impedance state (reset value is 0) */ | |
1282 | reg |= OMAP_I2C_SYSTEST_SCL_O; | |
1283 | /* set SDA to high-impedance state (reset value is 0) */ | |
1284 | reg |= OMAP_I2C_SYSTEST_SDA_O; | |
9dcb0e7b FB |
1285 | omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); |
1286 | } | |
1287 | ||
1288 | static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap) | |
1289 | { | |
1290 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
1291 | u32 reg; | |
1292 | ||
1293 | reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); | |
828e66c0 | 1294 | /* restore reset values */ |
9dcb0e7b | 1295 | reg &= ~OMAP_I2C_SYSTEST_ST_EN; |
828e66c0 JL |
1296 | reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK; |
1297 | reg &= ~OMAP_I2C_SYSTEST_SCL_O; | |
1298 | reg &= ~OMAP_I2C_SYSTEST_SDA_O; | |
9dcb0e7b FB |
1299 | omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); |
1300 | } | |
1301 | ||
1302 | static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = { | |
1303 | .get_scl = omap_i2c_get_scl, | |
1304 | .get_sda = omap_i2c_get_sda, | |
1305 | .set_scl = omap_i2c_set_scl, | |
1306 | .prepare_recovery = omap_i2c_prepare_recovery, | |
1307 | .unprepare_recovery = omap_i2c_unprepare_recovery, | |
1308 | .recover_bus = i2c_generic_scl_recovery, | |
1309 | }; | |
1310 | ||
0b255e92 | 1311 | static int |
010d442c KS |
1312 | omap_i2c_probe(struct platform_device *pdev) |
1313 | { | |
63f8f856 | 1314 | struct omap_i2c_dev *omap; |
010d442c | 1315 | struct i2c_adapter *adap; |
ac79e4b2 | 1316 | struct resource *mem; |
c4dba011 | 1317 | const struct omap_i2c_bus_platform_data *pdata = |
6d4028c6 | 1318 | dev_get_platdata(&pdev->dev); |
6145197b BC |
1319 | struct device_node *node = pdev->dev.of_node; |
1320 | const struct of_device_id *match; | |
ac79e4b2 | 1321 | int irq; |
010d442c | 1322 | int r; |
47dcd016 | 1323 | u32 rev; |
4368de19 | 1324 | u16 minor, major; |
010d442c | 1325 | |
ac79e4b2 FB |
1326 | irq = platform_get_irq(pdev, 0); |
1327 | if (irq < 0) { | |
010d442c | 1328 | dev_err(&pdev->dev, "no irq resource?\n"); |
ac79e4b2 | 1329 | return irq; |
010d442c KS |
1330 | } |
1331 | ||
63f8f856 FB |
1332 | omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1333 | if (!omap) | |
d9ebd04d | 1334 | return -ENOMEM; |
010d442c | 1335 | |
3cc2d009 | 1336 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
63f8f856 FB |
1337 | omap->base = devm_ioremap_resource(&pdev->dev, mem); |
1338 | if (IS_ERR(omap->base)) | |
1339 | return PTR_ERR(omap->base); | |
010d442c | 1340 | |
6c5aa407 | 1341 | match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); |
6145197b BC |
1342 | if (match) { |
1343 | u32 freq = 100000; /* default to 100000 Hz */ | |
1344 | ||
1345 | pdata = match->data; | |
63f8f856 | 1346 | omap->flags = pdata->flags; |
6145197b BC |
1347 | |
1348 | of_property_read_u32(node, "clock-frequency", &freq); | |
1349 | /* convert DT freq value in Hz into kHz for speed */ | |
63f8f856 | 1350 | omap->speed = freq / 1000; |
6145197b | 1351 | } else if (pdata != NULL) { |
63f8f856 FB |
1352 | omap->speed = pdata->clkrate; |
1353 | omap->flags = pdata->flags; | |
1354 | omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; | |
20c9d2c4 | 1355 | } |
4574eb68 | 1356 | |
63f8f856 FB |
1357 | omap->dev = &pdev->dev; |
1358 | omap->irq = irq; | |
55c381e4 | 1359 | |
63f8f856 FB |
1360 | platform_set_drvdata(pdev, omap); |
1361 | init_completion(&omap->cmd_complete); | |
010d442c | 1362 | |
63f8f856 | 1363 | omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1364 | |
63f8f856 FB |
1365 | pm_runtime_enable(omap->dev); |
1366 | pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT); | |
1367 | pm_runtime_use_autosuspend(omap->dev); | |
6d8451d5 | 1368 | |
63f8f856 | 1369 | r = pm_runtime_get_sync(omap->dev); |
77441ac0 | 1370 | if (r < 0) |
3b0fb97c | 1371 | goto err_free_mem; |
010d442c | 1372 | |
47dcd016 S |
1373 | /* |
1374 | * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. | |
1375 | * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. | |
1376 | * Also since the omap_i2c_read_reg uses reg_map_ip_* a | |
40b13ca8 | 1377 | * readw_relaxed is done. |
47dcd016 | 1378 | */ |
63f8f856 | 1379 | rev = readw_relaxed(omap->base + 0x04); |
47dcd016 | 1380 | |
63f8f856 FB |
1381 | omap->scheme = OMAP_I2C_SCHEME(rev); |
1382 | switch (omap->scheme) { | |
47dcd016 | 1383 | case OMAP_I2C_SCHEME_0: |
63f8f856 FB |
1384 | omap->regs = (u8 *)reg_map_ip_v1; |
1385 | omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG); | |
1386 | minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev); | |
1387 | major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev); | |
47dcd016 S |
1388 | break; |
1389 | case OMAP_I2C_SCHEME_1: | |
1390 | /* FALLTHROUGH */ | |
1391 | default: | |
63f8f856 | 1392 | omap->regs = (u8 *)reg_map_ip_v2; |
47dcd016 | 1393 | rev = (rev << 16) | |
63f8f856 | 1394 | omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO); |
47dcd016 S |
1395 | minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); |
1396 | major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); | |
63f8f856 | 1397 | omap->rev = rev; |
47dcd016 | 1398 | } |
010d442c | 1399 | |
63f8f856 | 1400 | omap->errata = 0; |
9aa8ec67 | 1401 | |
63f8f856 FB |
1402 | if (omap->rev >= OMAP_I2C_REV_ON_2430 && |
1403 | omap->rev < OMAP_I2C_REV_ON_4430_PLUS) | |
1404 | omap->errata |= I2C_OMAP_ERRATA_I207; | |
9aa8ec67 | 1405 | |
63f8f856 FB |
1406 | if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) |
1407 | omap->errata |= I2C_OMAP_ERRATA_I462; | |
8a9d97d3 | 1408 | |
63f8f856 | 1409 | if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1410 | u16 s; |
1411 | ||
1412 | /* Set up the fifo size - Get total size */ | |
63f8f856 FB |
1413 | s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; |
1414 | omap->fifo_size = 0x8 << s; | |
b6ee52c3 NM |
1415 | |
1416 | /* | |
1417 | * Set up notification threshold as half the total available | |
1418 | * size. This is to ensure that we can handle the status on int | |
1419 | * call back latencies. | |
1420 | */ | |
1d5a34fe | 1421 | |
63f8f856 | 1422 | omap->fifo_size = (omap->fifo_size / 2); |
1d5a34fe | 1423 | |
63f8f856 FB |
1424 | if (omap->rev < OMAP_I2C_REV_ON_3630) |
1425 | omap->b_hw = 1; /* Enable hardware fixes */ | |
1d5a34fe | 1426 | |
20c9d2c4 | 1427 | /* calculate wakeup latency constraint for MPU */ |
63f8f856 FB |
1428 | if (omap->set_mpu_wkup_lat != NULL) |
1429 | omap->latency = (1000000 * omap->fifo_size) / | |
1430 | (1000 * omap->speed / 8); | |
b6ee52c3 NM |
1431 | } |
1432 | ||
010d442c | 1433 | /* reset ASAP, clearing any IRQs */ |
63f8f856 | 1434 | omap_i2c_init(omap); |
010d442c | 1435 | |
63f8f856 FB |
1436 | if (omap->rev < OMAP_I2C_OMAP1_REV_2) |
1437 | r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr, | |
1438 | IRQF_NO_SUSPEND, pdev->name, omap); | |
3b2f8f82 | 1439 | else |
63f8f856 | 1440 | r = devm_request_threaded_irq(&pdev->dev, omap->irq, |
3b2f8f82 FB |
1441 | omap_i2c_isr, omap_i2c_isr_thread, |
1442 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
63f8f856 | 1443 | pdev->name, omap); |
010d442c KS |
1444 | |
1445 | if (r) { | |
63f8f856 | 1446 | dev_err(omap->dev, "failure requesting irq %i\n", omap->irq); |
010d442c KS |
1447 | goto err_unuse_clocks; |
1448 | } | |
9c76b878 | 1449 | |
63f8f856 FB |
1450 | adap = &omap->adapter; |
1451 | i2c_set_adapdata(adap, omap); | |
010d442c | 1452 | adap->owner = THIS_MODULE; |
cfac71d9 | 1453 | adap->class = I2C_CLASS_DEPRECATED; |
783fd6fa | 1454 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1455 | adap->algo = &omap_i2c_algo; |
1456 | adap->dev.parent = &pdev->dev; | |
6145197b | 1457 | adap->dev.of_node = pdev->dev.of_node; |
9dcb0e7b | 1458 | adap->bus_recovery_info = &omap_i2c_bus_recovery_info; |
010d442c KS |
1459 | |
1460 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1461 | adap->nr = pdev->id; |
1462 | r = i2c_add_numbered_adapter(adap); | |
ea734404 | 1463 | if (r) |
d9ebd04d | 1464 | goto err_unuse_clocks; |
010d442c | 1465 | |
63f8f856 FB |
1466 | dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, |
1467 | major, minor, omap->speed); | |
c5d3cd6d | 1468 | |
63f8f856 FB |
1469 | pm_runtime_mark_last_busy(omap->dev); |
1470 | pm_runtime_put_autosuspend(omap->dev); | |
62ff2c2b | 1471 | |
010d442c KS |
1472 | return 0; |
1473 | ||
010d442c | 1474 | err_unuse_clocks: |
63f8f856 | 1475 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); |
e6244dee TL |
1476 | pm_runtime_dont_use_autosuspend(omap->dev); |
1477 | pm_runtime_put_sync(omap->dev); | |
24740516 | 1478 | pm_runtime_disable(&pdev->dev); |
010d442c | 1479 | err_free_mem: |
010d442c KS |
1480 | |
1481 | return r; | |
1482 | } | |
1483 | ||
0b255e92 | 1484 | static int omap_i2c_remove(struct platform_device *pdev) |
010d442c | 1485 | { |
63f8f856 | 1486 | struct omap_i2c_dev *omap = platform_get_drvdata(pdev); |
3b0fb97c | 1487 | int ret; |
010d442c | 1488 | |
63f8f856 | 1489 | i2c_del_adapter(&omap->adapter); |
3b0fb97c | 1490 | ret = pm_runtime_get_sync(&pdev->dev); |
ff370257 | 1491 | if (ret < 0) |
3b0fb97c S |
1492 | return ret; |
1493 | ||
63f8f856 | 1494 | omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0); |
e6244dee | 1495 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1c4828f9 | 1496 | pm_runtime_put_sync(&pdev->dev); |
24740516 | 1497 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1498 | return 0; |
1499 | } | |
1500 | ||
5692d2a2 | 1501 | #ifdef CONFIG_PM |
fab67afb KH |
1502 | static int omap_i2c_runtime_suspend(struct device *dev) |
1503 | { | |
63f8f856 | 1504 | struct omap_i2c_dev *omap = dev_get_drvdata(dev); |
3dae3efb | 1505 | |
63f8f856 | 1506 | omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); |
bd16c82f | 1507 | |
63f8f856 FB |
1508 | if (omap->scheme == OMAP_I2C_SCHEME_0) |
1509 | omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0); | |
4368de19 | 1510 | else |
63f8f856 | 1511 | omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR, |
4368de19 | 1512 | OMAP_I2C_IP_V2_INTERRUPTS_MASK); |
fab67afb | 1513 | |
63f8f856 FB |
1514 | if (omap->rev < OMAP_I2C_OMAP1_REV_2) { |
1515 | omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */ | |
3dae3efb | 1516 | } else { |
63f8f856 | 1517 | omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate); |
fab67afb | 1518 | |
3dae3efb | 1519 | /* Flush posted write */ |
63f8f856 | 1520 | omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); |
3dae3efb | 1521 | } |
fab67afb | 1522 | |
096ea30c PH |
1523 | pinctrl_pm_select_sleep_state(dev); |
1524 | ||
fab67afb KH |
1525 | return 0; |
1526 | } | |
1527 | ||
1528 | static int omap_i2c_runtime_resume(struct device *dev) | |
1529 | { | |
63f8f856 | 1530 | struct omap_i2c_dev *omap = dev_get_drvdata(dev); |
096ea30c PH |
1531 | |
1532 | pinctrl_pm_select_default_state(dev); | |
fab67afb | 1533 | |
63f8f856 | 1534 | if (!omap->regs) |
47dcd016 S |
1535 | return 0; |
1536 | ||
63f8f856 | 1537 | __omap_i2c_init(omap); |
fab67afb KH |
1538 | |
1539 | return 0; | |
1540 | } | |
1541 | ||
50b918c5 | 1542 | static const struct dev_pm_ops omap_i2c_pm_ops = { |
5692d2a2 S |
1543 | SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, |
1544 | omap_i2c_runtime_resume, NULL) | |
fab67afb KH |
1545 | }; |
1546 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) | |
1547 | #else | |
1548 | #define OMAP_I2C_PM_OPS NULL | |
5692d2a2 | 1549 | #endif /* CONFIG_PM */ |
fab67afb | 1550 | |
010d442c KS |
1551 | static struct platform_driver omap_i2c_driver = { |
1552 | .probe = omap_i2c_probe, | |
0b255e92 | 1553 | .remove = omap_i2c_remove, |
010d442c | 1554 | .driver = { |
f7bb0d9a | 1555 | .name = "omap_i2c", |
fab67afb | 1556 | .pm = OMAP_I2C_PM_OPS, |
6145197b | 1557 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1558 | }, |
1559 | }; | |
1560 | ||
1561 | /* I2C may be needed to bring up other drivers */ | |
1562 | static int __init | |
1563 | omap_i2c_init_driver(void) | |
1564 | { | |
1565 | return platform_driver_register(&omap_i2c_driver); | |
1566 | } | |
1567 | subsys_initcall(omap_i2c_init_driver); | |
1568 | ||
1569 | static void __exit omap_i2c_exit_driver(void) | |
1570 | { | |
1571 | platform_driver_unregister(&omap_i2c_driver); | |
1572 | } | |
1573 | module_exit(omap_i2c_exit_driver); | |
1574 | ||
1575 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1576 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1577 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1578 | MODULE_ALIAS("platform:omap_i2c"); |