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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
6145197b BC |
40 | #include <linux/of.h> |
41 | #include <linux/of_i2c.h> | |
42 | #include <linux/of_device.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
20c9d2c4 | 44 | #include <linux/i2c-omap.h> |
27b1fec2 | 45 | #include <linux/pm_runtime.h> |
010d442c | 46 | |
9c76b878 | 47 | /* I2C controller revisions */ |
4e80f727 | 48 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
49 | |
50 | /* I2C controller revisions present on specific hardware */ | |
47dcd016 S |
51 | #define OMAP_I2C_REV_ON_2430 0x00000036 |
52 | #define OMAP_I2C_REV_ON_3430_3530 0x0000003C | |
53 | #define OMAP_I2C_REV_ON_3630 0x00000040 | |
54 | #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 | |
9c76b878 | 55 | |
010d442c KS |
56 | /* timeout waiting for the controller to respond */ |
57 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
58 | ||
6d8451d5 FB |
59 | /* timeout for pm runtime autosuspend */ |
60 | #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ | |
61 | ||
5043e9e7 | 62 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
63 | enum { |
64 | OMAP_I2C_REV_REG = 0, | |
65 | OMAP_I2C_IE_REG, | |
66 | OMAP_I2C_STAT_REG, | |
67 | OMAP_I2C_IV_REG, | |
68 | OMAP_I2C_WE_REG, | |
69 | OMAP_I2C_SYSS_REG, | |
70 | OMAP_I2C_BUF_REG, | |
71 | OMAP_I2C_CNT_REG, | |
72 | OMAP_I2C_DATA_REG, | |
73 | OMAP_I2C_SYSC_REG, | |
74 | OMAP_I2C_CON_REG, | |
75 | OMAP_I2C_OA_REG, | |
76 | OMAP_I2C_SA_REG, | |
77 | OMAP_I2C_PSC_REG, | |
78 | OMAP_I2C_SCLL_REG, | |
79 | OMAP_I2C_SCLH_REG, | |
80 | OMAP_I2C_SYSTEST_REG, | |
81 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
82 | /* only on OMAP4430 */ |
83 | OMAP_I2C_IP_V2_REVNB_LO, | |
84 | OMAP_I2C_IP_V2_REVNB_HI, | |
85 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
86 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
87 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 88 | }; |
010d442c KS |
89 | |
90 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
91 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
92 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
93 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
94 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
95 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
96 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
97 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
98 | ||
99 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
100 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
101 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
102 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
103 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
104 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
105 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
106 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
107 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
108 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
109 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
110 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
111 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
112 | ||
5043e9e7 KJ |
113 | /* I2C WE wakeup enable register */ |
114 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
115 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
116 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
117 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
118 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
119 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
120 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
121 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
122 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
123 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
124 | ||
125 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
126 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
127 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
128 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
129 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
130 | ||
010d442c KS |
131 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
132 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 133 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 134 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 135 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
136 | |
137 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
138 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
139 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 140 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
141 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
142 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
143 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
144 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
145 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
146 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
147 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
148 | ||
4574eb68 SMK |
149 | /* I2C SCL time value when Master */ |
150 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
151 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
152 | ||
010d442c KS |
153 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
154 | #ifdef DEBUG | |
155 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
156 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
157 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
158 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
159 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
160 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
161 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
162 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
163 | #endif | |
164 | ||
fdd07fe6 PW |
165 | /* OCP_SYSSTATUS bit definitions */ |
166 | #define SYSS_RESETDONE_MASK (1 << 0) | |
167 | ||
168 | /* OCP_SYSCONFIG bit definitions */ | |
169 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
170 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
171 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
172 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
173 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
174 | ||
175 | #define SYSC_IDLEMODE_SMART 0x2 | |
176 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 177 | |
f3083d92 | 178 | /* Errata definitions */ |
179 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
c8db38f0 | 180 | #define I2C_OMAP_ERRATA_I462 (1 << 1) |
010d442c | 181 | |
4368de19 OD |
182 | #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF |
183 | ||
010d442c | 184 | struct omap_i2c_dev { |
3b2f8f82 | 185 | spinlock_t lock; /* IRQ synchronization */ |
010d442c KS |
186 | struct device *dev; |
187 | void __iomem *base; /* virtual */ | |
188 | int irq; | |
d84d3ea3 | 189 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
190 | struct completion cmd_complete; |
191 | struct resource *ioarea; | |
49839dc9 PW |
192 | u32 latency; /* maximum mpu wkup latency */ |
193 | void (*set_mpu_wkup_lat)(struct device *dev, | |
194 | long latency); | |
6145197b | 195 | u32 speed; /* Speed of bus in kHz */ |
6145197b | 196 | u32 flags; |
4368de19 | 197 | u16 scheme; |
010d442c KS |
198 | u16 cmd_err; |
199 | u8 *buf; | |
f38e66e0 | 200 | u8 *regs; |
010d442c KS |
201 | size_t buf_len; |
202 | struct i2c_adapter adapter; | |
dd74548d | 203 | u8 threshold; |
b6ee52c3 NM |
204 | u8 fifo_size; /* use as flag and value |
205 | * fifo_size==0 implies no fifo | |
206 | * if set, should be trsh+1 | |
207 | */ | |
47dcd016 | 208 | u32 rev; |
b6ee52c3 | 209 | unsigned b_hw:1; /* bad h/w fixes */ |
079d8af2 | 210 | unsigned receiver:1; /* true when we're in receiver mode */ |
f08ac4e7 | 211 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
212 | u16 pscstate; |
213 | u16 scllstate; | |
214 | u16 sclhstate; | |
ef871432 RN |
215 | u16 syscstate; |
216 | u16 westate; | |
f3083d92 | 217 | u16 errata; |
010d442c KS |
218 | }; |
219 | ||
a1295577 | 220 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
221 | [OMAP_I2C_REV_REG] = 0x00, |
222 | [OMAP_I2C_IE_REG] = 0x01, | |
223 | [OMAP_I2C_STAT_REG] = 0x02, | |
224 | [OMAP_I2C_IV_REG] = 0x03, | |
225 | [OMAP_I2C_WE_REG] = 0x03, | |
226 | [OMAP_I2C_SYSS_REG] = 0x04, | |
227 | [OMAP_I2C_BUF_REG] = 0x05, | |
228 | [OMAP_I2C_CNT_REG] = 0x06, | |
229 | [OMAP_I2C_DATA_REG] = 0x07, | |
230 | [OMAP_I2C_SYSC_REG] = 0x08, | |
231 | [OMAP_I2C_CON_REG] = 0x09, | |
232 | [OMAP_I2C_OA_REG] = 0x0a, | |
233 | [OMAP_I2C_SA_REG] = 0x0b, | |
234 | [OMAP_I2C_PSC_REG] = 0x0c, | |
235 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
236 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
237 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
238 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
239 | }; | |
240 | ||
a1295577 | 241 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
242 | [OMAP_I2C_REV_REG] = 0x04, |
243 | [OMAP_I2C_IE_REG] = 0x2c, | |
244 | [OMAP_I2C_STAT_REG] = 0x28, | |
245 | [OMAP_I2C_IV_REG] = 0x34, | |
246 | [OMAP_I2C_WE_REG] = 0x34, | |
247 | [OMAP_I2C_SYSS_REG] = 0x90, | |
248 | [OMAP_I2C_BUF_REG] = 0x94, | |
249 | [OMAP_I2C_CNT_REG] = 0x98, | |
250 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 251 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
252 | [OMAP_I2C_CON_REG] = 0xa4, |
253 | [OMAP_I2C_OA_REG] = 0xa8, | |
254 | [OMAP_I2C_SA_REG] = 0xac, | |
255 | [OMAP_I2C_PSC_REG] = 0xb0, | |
256 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
257 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
258 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
259 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
260 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
261 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
262 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
263 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
264 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
265 | }; |
266 | ||
010d442c KS |
267 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
268 | int reg, u16 val) | |
269 | { | |
f38e66e0 SS |
270 | __raw_writew(val, i2c_dev->base + |
271 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
272 | } |
273 | ||
274 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
275 | { | |
f38e66e0 SS |
276 | return __raw_readw(i2c_dev->base + |
277 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
278 | } |
279 | ||
95dd3032 S |
280 | static void __omap_i2c_init(struct omap_i2c_dev *dev) |
281 | { | |
282 | ||
283 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
284 | ||
285 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ | |
286 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); | |
287 | ||
288 | /* SCL low and high time values */ | |
289 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); | |
290 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); | |
291 | if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) | |
292 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
293 | ||
294 | /* Take the I2C module out of reset: */ | |
295 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
296 | ||
297 | /* | |
298 | * Don't write to this register if the IE state is 0 as it can | |
299 | * cause deadlock. | |
300 | */ | |
301 | if (dev->iestate) | |
302 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
303 | } | |
304 | ||
d6c842ad | 305 | static int omap_i2c_reset(struct omap_i2c_dev *dev) |
010d442c | 306 | { |
010d442c | 307 | unsigned long timeout; |
ca85e248 S |
308 | u16 sysc; |
309 | ||
4e80f727 | 310 | if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { |
ca85e248 S |
311 | sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG); |
312 | ||
57eb81b1 MG |
313 | /* Disable I2C controller before soft reset */ |
314 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
315 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
316 | ~(OMAP_I2C_CON_EN)); | |
317 | ||
fdd07fe6 | 318 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
319 | /* For some reason we need to set the EN bit before the |
320 | * reset done bit gets set. */ | |
321 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
322 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
323 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 324 | SYSS_RESETDONE_MASK)) { |
010d442c | 325 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 326 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
327 | "for controller reset\n"); |
328 | return -ETIMEDOUT; | |
329 | } | |
330 | msleep(1); | |
331 | } | |
fdd07fe6 PW |
332 | |
333 | /* SYSC register is cleared by the reset; rewrite it */ | |
ca85e248 | 334 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc); |
fdd07fe6 | 335 | |
010d442c | 336 | } |
d6c842ad S |
337 | return 0; |
338 | } | |
339 | ||
340 | static int omap_i2c_init(struct omap_i2c_dev *dev) | |
341 | { | |
342 | u16 psc = 0, scll = 0, sclh = 0; | |
343 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; | |
344 | unsigned long fclk_rate = 12000000; | |
345 | unsigned long internal_clk = 0; | |
346 | struct clk *fclk; | |
347 | ||
348 | if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { | |
349 | /* | |
350 | * Enabling all wakup sources to stop I2C freezing on | |
351 | * WFI instruction. | |
352 | * REVISIT: Some wkup sources might not be needed. | |
353 | */ | |
354 | dev->westate = OMAP_I2C_WE_ALL; | |
355 | } | |
010d442c | 356 | |
6145197b | 357 | if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
358 | /* |
359 | * The I2C functional clock is the armxor_ck, so there's | |
360 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
361 | * always returns 12MHz for the functional clock, we can | |
362 | * do this bit unconditionally. | |
363 | */ | |
27b1fec2 RN |
364 | fclk = clk_get(dev->dev, "fck"); |
365 | fclk_rate = clk_get_rate(fclk); | |
366 | clk_put(fclk); | |
0e9ae109 | 367 | |
010d442c KS |
368 | /* TRM for 5912 says the I2C clock must be prescaled to be |
369 | * between 7 - 12 MHz. The XOR input clock is typically | |
370 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
371 | * | |
372 | * XOR MHz Divider Prescaler | |
373 | * 12 1 0 | |
374 | * 13 2 1 | |
375 | * 19.2 2 1 | |
376 | */ | |
d7aef138 JD |
377 | if (fclk_rate > 12000000) |
378 | psc = fclk_rate / 12000000; | |
010d442c KS |
379 | } |
380 | ||
6145197b | 381 | if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 382 | |
84bf2c86 AK |
383 | /* |
384 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
385 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
386 | * to get longer filter period for better noise suppression. | |
387 | * The filter is iclk (fclk for HS) period. | |
388 | */ | |
3be0053e | 389 | if (dev->speed > 400 || |
6145197b | 390 | dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) |
84bf2c86 AK |
391 | internal_clk = 19200; |
392 | else if (dev->speed > 100) | |
393 | internal_clk = 9600; | |
394 | else | |
395 | internal_clk = 4000; | |
27b1fec2 RN |
396 | fclk = clk_get(dev->dev, "fck"); |
397 | fclk_rate = clk_get_rate(fclk) / 1000; | |
398 | clk_put(fclk); | |
4574eb68 SMK |
399 | |
400 | /* Compute prescaler divisor */ | |
401 | psc = fclk_rate / internal_clk; | |
402 | psc = psc - 1; | |
403 | ||
404 | /* If configured for High Speed */ | |
405 | if (dev->speed > 400) { | |
baf46b4e AK |
406 | unsigned long scl; |
407 | ||
4574eb68 | 408 | /* For first phase of HS mode */ |
baf46b4e AK |
409 | scl = internal_clk / 400; |
410 | fsscll = scl - (scl / 3) - 7; | |
411 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
412 | |
413 | /* For second phase of HS mode */ | |
baf46b4e AK |
414 | scl = fclk_rate / dev->speed; |
415 | hsscll = scl - (scl / 3) - 7; | |
416 | hssclh = (scl / 3) - 5; | |
417 | } else if (dev->speed > 100) { | |
418 | unsigned long scl; | |
419 | ||
420 | /* Fast mode */ | |
421 | scl = internal_clk / dev->speed; | |
422 | fsscll = scl - (scl / 3) - 7; | |
423 | fssclh = (scl / 3) - 5; | |
4574eb68 | 424 | } else { |
baf46b4e AK |
425 | /* Standard mode */ |
426 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
427 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
428 | } |
429 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
430 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
431 | } else { | |
432 | /* Program desired operating rate */ | |
433 | fclk_rate /= (psc + 1) * 1000; | |
434 | if (psc > 2) | |
435 | psc = 2; | |
436 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
437 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
438 | } | |
439 | ||
ef871432 | 440 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
441 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
442 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 | 443 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
95dd3032 S |
444 | |
445 | dev->pscstate = psc; | |
446 | dev->scllstate = scll; | |
447 | dev->sclhstate = sclh; | |
448 | ||
449 | __omap_i2c_init(dev); | |
450 | ||
010d442c KS |
451 | return 0; |
452 | } | |
453 | ||
454 | /* | |
455 | * Waiting on Bus Busy | |
456 | */ | |
457 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
458 | { | |
459 | unsigned long timeout; | |
460 | ||
461 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
462 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
463 | if (time_after(jiffies, timeout)) { | |
464 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
465 | return -ETIMEDOUT; | |
466 | } | |
467 | msleep(1); | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
dd74548d FB |
473 | static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) |
474 | { | |
475 | u16 buf; | |
476 | ||
477 | if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) | |
478 | return; | |
479 | ||
480 | /* | |
481 | * Set up notification threshold based on message size. We're doing | |
482 | * this to try and avoid draining feature as much as possible. Whenever | |
483 | * we have big messages to transfer (bigger than our total fifo size) | |
484 | * then we might use draining feature to transfer the remaining bytes. | |
485 | */ | |
486 | ||
487 | dev->threshold = clamp(size, (u8) 1, dev->fifo_size); | |
488 | ||
489 | buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
490 | ||
491 | if (is_rx) { | |
492 | /* Clear RX Threshold */ | |
493 | buf &= ~(0x3f << 8); | |
494 | buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; | |
495 | } else { | |
496 | /* Clear TX Threshold */ | |
497 | buf &= ~0x3f; | |
498 | buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
499 | } | |
500 | ||
501 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
502 | ||
47dcd016 | 503 | if (dev->rev < OMAP_I2C_REV_ON_3630) |
dd74548d FB |
504 | dev->b_hw = 1; /* Enable hardware fixes */ |
505 | ||
506 | /* calculate wakeup latency constraint for MPU */ | |
49839dc9 PW |
507 | if (dev->set_mpu_wkup_lat != NULL) |
508 | dev->latency = (1000000 * dev->threshold) / | |
509 | (1000 * dev->speed / 8); | |
dd74548d FB |
510 | } |
511 | ||
010d442c KS |
512 | /* |
513 | * Low level master read/write transaction. | |
514 | */ | |
515 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
516 | struct i2c_msg *msg, int stop) | |
517 | { | |
518 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
33d54985 | 519 | unsigned long timeout; |
010d442c KS |
520 | u16 w; |
521 | ||
522 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
523 | msg->addr, msg->len, msg->flags, stop); | |
524 | ||
525 | if (msg->len == 0) | |
526 | return -EINVAL; | |
527 | ||
dd74548d FB |
528 | dev->receiver = !!(msg->flags & I2C_M_RD); |
529 | omap_i2c_resize_fifo(dev, msg->len, dev->receiver); | |
530 | ||
010d442c KS |
531 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); |
532 | ||
533 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
534 | dev->buf = msg->buf; | |
535 | dev->buf_len = msg->len; | |
536 | ||
d60ece5f FB |
537 | /* make sure writes to dev->buf_len are ordered */ |
538 | barrier(); | |
539 | ||
010d442c KS |
540 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); |
541 | ||
b6ee52c3 NM |
542 | /* Clear the FIFO Buffers */ |
543 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
544 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
545 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
546 | ||
0e33bbb2 | 547 | INIT_COMPLETION(dev->cmd_complete); |
010d442c KS |
548 | dev->cmd_err = 0; |
549 | ||
550 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
551 | |
552 | /* High speed configuration */ | |
553 | if (dev->speed > 400) | |
b6ee52c3 | 554 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 555 | |
fb604a3d LP |
556 | if (msg->flags & I2C_M_STOP) |
557 | stop = 1; | |
010d442c KS |
558 | if (msg->flags & I2C_M_TEN) |
559 | w |= OMAP_I2C_CON_XA; | |
560 | if (!(msg->flags & I2C_M_RD)) | |
561 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 562 | |
b6ee52c3 | 563 | if (!dev->b_hw && stop) |
010d442c | 564 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 565 | |
010d442c KS |
566 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
567 | ||
b6ee52c3 NM |
568 | /* |
569 | * Don't write stt and stp together on some hardware. | |
570 | */ | |
571 | if (dev->b_hw && stop) { | |
572 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
573 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
574 | while (con & OMAP_I2C_CON_STT) { | |
575 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
576 | ||
577 | /* Let the user know if i2c is in a bad state */ | |
578 | if (time_after(jiffies, delay)) { | |
579 | dev_err(dev->dev, "controller timed out " | |
580 | "waiting for start condition to finish\n"); | |
581 | return -ETIMEDOUT; | |
582 | } | |
583 | cpu_relax(); | |
584 | } | |
585 | ||
586 | w |= OMAP_I2C_CON_STP; | |
587 | w &= ~OMAP_I2C_CON_STT; | |
588 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
589 | } | |
590 | ||
b7af349b JN |
591 | /* |
592 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
593 | * into arbitration and we're currently unable to recover from it. | |
594 | */ | |
33d54985 S |
595 | timeout = wait_for_completion_timeout(&dev->cmd_complete, |
596 | OMAP_I2C_TIMEOUT); | |
33d54985 | 597 | if (timeout == 0) { |
010d442c | 598 | dev_err(dev->dev, "controller timed out\n"); |
d6c842ad S |
599 | omap_i2c_reset(dev); |
600 | __omap_i2c_init(dev); | |
010d442c KS |
601 | return -ETIMEDOUT; |
602 | } | |
603 | ||
604 | if (likely(!dev->cmd_err)) | |
605 | return 0; | |
606 | ||
607 | /* We have an error */ | |
608 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
609 | OMAP_I2C_STAT_XUDF)) { | |
d6c842ad S |
610 | omap_i2c_reset(dev); |
611 | __omap_i2c_init(dev); | |
010d442c KS |
612 | return -EIO; |
613 | } | |
614 | ||
615 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
616 | if (msg->flags & I2C_M_IGNORE_NAK) | |
617 | return 0; | |
cda2109a GS |
618 | |
619 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
620 | w |= OMAP_I2C_CON_STP; | |
621 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
010d442c KS |
622 | return -EREMOTEIO; |
623 | } | |
624 | return -EIO; | |
625 | } | |
626 | ||
627 | ||
628 | /* | |
629 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
630 | * to do the work during IRQ processing. | |
631 | */ | |
632 | static int | |
633 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
634 | { | |
635 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
636 | int i; | |
637 | int r; | |
638 | ||
3b0fb97c S |
639 | r = pm_runtime_get_sync(dev->dev); |
640 | if (IS_ERR_VALUE(r)) | |
33ec5e81 | 641 | goto out; |
010d442c | 642 | |
c1a473bd TL |
643 | r = omap_i2c_wait_for_bb(dev); |
644 | if (r < 0) | |
010d442c KS |
645 | goto out; |
646 | ||
49839dc9 PW |
647 | if (dev->set_mpu_wkup_lat != NULL) |
648 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
6a91b558 | 649 | |
010d442c KS |
650 | for (i = 0; i < num; i++) { |
651 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
652 | if (r != 0) | |
653 | break; | |
654 | } | |
655 | ||
656 | if (r == 0) | |
657 | r = num; | |
5c64eb26 MN |
658 | |
659 | omap_i2c_wait_for_bb(dev); | |
1ab36045 S |
660 | |
661 | if (dev->set_mpu_wkup_lat != NULL) | |
662 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
663 | ||
010d442c | 664 | out: |
6d8451d5 FB |
665 | pm_runtime_mark_last_busy(dev->dev); |
666 | pm_runtime_put_autosuspend(dev->dev); | |
010d442c KS |
667 | return r; |
668 | } | |
669 | ||
670 | static u32 | |
671 | omap_i2c_func(struct i2c_adapter *adap) | |
672 | { | |
fb604a3d LP |
673 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
674 | I2C_FUNC_PROTOCOL_MANGLING; | |
010d442c KS |
675 | } |
676 | ||
677 | static inline void | |
678 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
679 | { | |
680 | dev->cmd_err |= err; | |
681 | complete(&dev->cmd_complete); | |
682 | } | |
683 | ||
684 | static inline void | |
685 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
686 | { | |
687 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
688 | } | |
689 | ||
f3083d92 | 690 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
691 | { | |
692 | /* | |
693 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
694 | * Not applicable for OMAP4. | |
695 | * Under certain rare conditions, RDR could be set again | |
696 | * when the bus is busy, then ignore the interrupt and | |
697 | * clear the interrupt. | |
698 | */ | |
699 | if (stat & OMAP_I2C_STAT_RDR) { | |
700 | /* Step 1: If RDR is set, clear it */ | |
701 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
702 | ||
703 | /* Step 2: */ | |
704 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
705 | & OMAP_I2C_STAT_BB)) { | |
706 | ||
707 | /* Step 3: */ | |
708 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
709 | & OMAP_I2C_STAT_RDR) { | |
710 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
711 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
712 | } | |
713 | ||
714 | } | |
715 | } | |
716 | } | |
717 | ||
43469d8e PW |
718 | /* rev1 devices are apparently only on some 15xx */ |
719 | #ifdef CONFIG_ARCH_OMAP15XX | |
720 | ||
010d442c | 721 | static irqreturn_t |
4e80f727 | 722 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c KS |
723 | { |
724 | struct omap_i2c_dev *dev = dev_id; | |
725 | u16 iv, w; | |
726 | ||
fab67afb | 727 | if (pm_runtime_suspended(dev->dev)) |
f08ac4e7 TL |
728 | return IRQ_NONE; |
729 | ||
010d442c KS |
730 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
731 | switch (iv) { | |
732 | case 0x00: /* None */ | |
733 | break; | |
734 | case 0x01: /* Arbitration lost */ | |
735 | dev_err(dev->dev, "Arbitration lost\n"); | |
736 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
737 | break; | |
738 | case 0x02: /* No acknowledgement */ | |
739 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
740 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
741 | break; | |
742 | case 0x03: /* Register access ready */ | |
743 | omap_i2c_complete_cmd(dev, 0); | |
744 | break; | |
745 | case 0x04: /* Receive data ready */ | |
746 | if (dev->buf_len) { | |
747 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
748 | *dev->buf++ = w; | |
749 | dev->buf_len--; | |
750 | if (dev->buf_len) { | |
751 | *dev->buf++ = w >> 8; | |
752 | dev->buf_len--; | |
753 | } | |
754 | } else | |
755 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
756 | break; | |
757 | case 0x05: /* Transmit data ready */ | |
758 | if (dev->buf_len) { | |
759 | w = *dev->buf++; | |
760 | dev->buf_len--; | |
761 | if (dev->buf_len) { | |
762 | w |= *dev->buf++ << 8; | |
763 | dev->buf_len--; | |
764 | } | |
765 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
766 | } else | |
767 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
768 | break; | |
769 | default: | |
770 | return IRQ_NONE; | |
771 | } | |
772 | ||
773 | return IRQ_HANDLED; | |
774 | } | |
43469d8e | 775 | #else |
4e80f727 | 776 | #define omap_i2c_omap1_isr NULL |
43469d8e | 777 | #endif |
010d442c | 778 | |
2dd151ab | 779 | /* |
c8db38f0 | 780 | * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing |
2dd151ab AS |
781 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring |
782 | * them from the memory to the I2C interface. | |
783 | */ | |
4151e741 | 784 | static int errata_omap3_i462(struct omap_i2c_dev *dev) |
2dd151ab | 785 | { |
e9f59b9c | 786 | unsigned long timeout = 10000; |
4151e741 | 787 | u16 stat; |
e9f59b9c | 788 | |
4151e741 FB |
789 | do { |
790 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
791 | if (stat & OMAP_I2C_STAT_XUDF) | |
792 | break; | |
793 | ||
794 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
540a4790 | 795 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | |
2dd151ab | 796 | OMAP_I2C_STAT_XDR)); |
b07be0f3 FB |
797 | if (stat & OMAP_I2C_STAT_NACK) { |
798 | dev->cmd_err |= OMAP_I2C_STAT_NACK; | |
799 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); | |
800 | } | |
801 | ||
802 | if (stat & OMAP_I2C_STAT_AL) { | |
803 | dev_err(dev->dev, "Arbitration lost\n"); | |
804 | dev->cmd_err |= OMAP_I2C_STAT_AL; | |
2c5de558 | 805 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); |
b07be0f3 FB |
806 | } |
807 | ||
4151e741 | 808 | return -EIO; |
2dd151ab | 809 | } |
e9f59b9c | 810 | |
2dd151ab | 811 | cpu_relax(); |
4151e741 | 812 | } while (--timeout); |
2dd151ab | 813 | |
e9f59b9c AS |
814 | if (!timeout) { |
815 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
816 | return 0; | |
817 | } | |
818 | ||
2dd151ab AS |
819 | return 0; |
820 | } | |
821 | ||
3312d25e FB |
822 | static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, |
823 | bool is_rdr) | |
824 | { | |
825 | u16 w; | |
826 | ||
827 | while (num_bytes--) { | |
3312d25e FB |
828 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); |
829 | *dev->buf++ = w; | |
830 | dev->buf_len--; | |
831 | ||
832 | /* | |
833 | * Data reg in 2430, omap3 and | |
834 | * omap4 is 8 bit wide | |
835 | */ | |
836 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
837 | *dev->buf++ = w >> 8; |
838 | dev->buf_len--; | |
3312d25e FB |
839 | } |
840 | } | |
841 | } | |
842 | ||
843 | static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, | |
844 | bool is_xdr) | |
845 | { | |
846 | u16 w; | |
847 | ||
848 | while (num_bytes--) { | |
3312d25e FB |
849 | w = *dev->buf++; |
850 | dev->buf_len--; | |
851 | ||
852 | /* | |
853 | * Data reg in 2430, omap3 and | |
854 | * omap4 is 8 bit wide | |
855 | */ | |
856 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
857 | w |= *dev->buf++ << 8; |
858 | dev->buf_len--; | |
3312d25e FB |
859 | } |
860 | ||
861 | if (dev->errata & I2C_OMAP_ERRATA_I462) { | |
862 | int ret; | |
863 | ||
864 | ret = errata_omap3_i462(dev); | |
865 | if (ret < 0) | |
866 | return ret; | |
867 | } | |
868 | ||
869 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
870 | } | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
010d442c | 875 | static irqreturn_t |
3b2f8f82 | 876 | omap_i2c_isr(int irq, void *dev_id) |
010d442c KS |
877 | { |
878 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 FB |
879 | irqreturn_t ret = IRQ_HANDLED; |
880 | u16 mask; | |
881 | u16 stat; | |
882 | ||
883 | spin_lock(&dev->lock); | |
884 | mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
885 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
886 | ||
887 | if (stat & mask) | |
888 | ret = IRQ_WAKE_THREAD; | |
889 | ||
890 | spin_unlock(&dev->lock); | |
891 | ||
892 | return ret; | |
893 | } | |
894 | ||
010d442c | 895 | static irqreturn_t |
3b2f8f82 | 896 | omap_i2c_isr_thread(int this_irq, void *dev_id) |
010d442c KS |
897 | { |
898 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 | 899 | unsigned long flags; |
010d442c | 900 | u16 bits; |
3312d25e | 901 | u16 stat; |
66b92988 | 902 | int err = 0, count = 0; |
010d442c | 903 | |
3b2f8f82 | 904 | spin_lock_irqsave(&dev->lock, flags); |
66b92988 FB |
905 | do { |
906 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
907 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
908 | stat &= bits; | |
909 | ||
079d8af2 FB |
910 | /* If we're in receiver mode, ignore XDR/XRDY */ |
911 | if (dev->receiver) | |
912 | stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); | |
913 | else | |
914 | stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); | |
010d442c | 915 | |
66b92988 FB |
916 | if (!stat) { |
917 | /* my work here is done */ | |
0bdfe0cb | 918 | goto out; |
66b92988 | 919 | } |
f08ac4e7 | 920 | |
010d442c KS |
921 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); |
922 | if (count++ == 100) { | |
923 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
924 | break; | |
925 | } | |
926 | ||
1d7afc95 | 927 | if (stat & OMAP_I2C_STAT_NACK) { |
b6ee52c3 | 928 | err |= OMAP_I2C_STAT_NACK; |
1d7afc95 | 929 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); |
0bdfe0cb | 930 | break; |
1d7afc95 | 931 | } |
78e1cf42 | 932 | |
b6ee52c3 NM |
933 | if (stat & OMAP_I2C_STAT_AL) { |
934 | dev_err(dev->dev, "Arbitration lost\n"); | |
935 | err |= OMAP_I2C_STAT_AL; | |
1d7afc95 | 936 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); |
0bdfe0cb | 937 | break; |
b6ee52c3 | 938 | } |
c55edb99 | 939 | |
a5a595cc | 940 | /* |
cb527ede | 941 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 942 | */ |
b6ee52c3 | 943 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 944 | OMAP_I2C_STAT_AL)) { |
540a4790 FB |
945 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | |
946 | OMAP_I2C_STAT_RDR | | |
947 | OMAP_I2C_STAT_XRDY | | |
948 | OMAP_I2C_STAT_XDR | | |
949 | OMAP_I2C_STAT_ARDY)); | |
0bdfe0cb | 950 | break; |
04c688dd | 951 | } |
c55edb99 | 952 | |
6d9939f6 | 953 | if (stat & OMAP_I2C_STAT_RDR) { |
b6ee52c3 | 954 | u8 num_bytes = 1; |
f3083d92 | 955 | |
6d9939f6 FB |
956 | if (dev->fifo_size) |
957 | num_bytes = dev->buf_len; | |
958 | ||
3312d25e | 959 | omap_i2c_receive_data(dev, num_bytes, true); |
6d9939f6 | 960 | |
f3083d92 | 961 | if (dev->errata & I2C_OMAP_ERRATA_I207) |
962 | i2c_omap_errata_i207(dev, stat); | |
963 | ||
6d9939f6 | 964 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); |
9eb13cf3 | 965 | continue; |
6d9939f6 FB |
966 | } |
967 | ||
968 | if (stat & OMAP_I2C_STAT_RRDY) { | |
969 | u8 num_bytes = 1; | |
970 | ||
dd74548d FB |
971 | if (dev->threshold) |
972 | num_bytes = dev->threshold; | |
6d9939f6 | 973 | |
3312d25e | 974 | omap_i2c_receive_data(dev, num_bytes, false); |
6d9939f6 | 975 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); |
010d442c KS |
976 | continue; |
977 | } | |
c55edb99 | 978 | |
6d9939f6 | 979 | if (stat & OMAP_I2C_STAT_XDR) { |
b6ee52c3 | 980 | u8 num_bytes = 1; |
3312d25e | 981 | int ret; |
6d9939f6 FB |
982 | |
983 | if (dev->fifo_size) | |
984 | num_bytes = dev->buf_len; | |
985 | ||
3312d25e | 986 | ret = omap_i2c_transmit_data(dev, num_bytes, true); |
3312d25e | 987 | if (ret < 0) |
0bdfe0cb | 988 | break; |
6d9939f6 FB |
989 | |
990 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); | |
9eb13cf3 | 991 | continue; |
6d9939f6 FB |
992 | } |
993 | ||
994 | if (stat & OMAP_I2C_STAT_XRDY) { | |
995 | u8 num_bytes = 1; | |
3312d25e | 996 | int ret; |
6d9939f6 | 997 | |
dd74548d FB |
998 | if (dev->threshold) |
999 | num_bytes = dev->threshold; | |
6d9939f6 | 1000 | |
3312d25e | 1001 | ret = omap_i2c_transmit_data(dev, num_bytes, false); |
3312d25e | 1002 | if (ret < 0) |
0bdfe0cb | 1003 | break; |
6d9939f6 FB |
1004 | |
1005 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); | |
010d442c KS |
1006 | continue; |
1007 | } | |
c55edb99 | 1008 | |
010d442c KS |
1009 | if (stat & OMAP_I2C_STAT_ROVR) { |
1010 | dev_err(dev->dev, "Receive overrun\n"); | |
1d7afc95 FB |
1011 | err |= OMAP_I2C_STAT_ROVR; |
1012 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); | |
0bdfe0cb | 1013 | break; |
010d442c | 1014 | } |
c55edb99 | 1015 | |
010d442c | 1016 | if (stat & OMAP_I2C_STAT_XUDF) { |
b6ee52c3 | 1017 | dev_err(dev->dev, "Transmit underflow\n"); |
1d7afc95 FB |
1018 | err |= OMAP_I2C_STAT_XUDF; |
1019 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); | |
0bdfe0cb | 1020 | break; |
010d442c | 1021 | } |
66b92988 | 1022 | } while (stat); |
010d442c | 1023 | |
4a7ec4ed | 1024 | omap_i2c_complete_cmd(dev, err); |
0bdfe0cb FB |
1025 | |
1026 | out: | |
3b2f8f82 | 1027 | spin_unlock_irqrestore(&dev->lock, flags); |
010d442c | 1028 | |
6a85ced2 | 1029 | return IRQ_HANDLED; |
010d442c KS |
1030 | } |
1031 | ||
8f9082c5 | 1032 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
1033 | .master_xfer = omap_i2c_xfer, |
1034 | .functionality = omap_i2c_func, | |
1035 | }; | |
1036 | ||
6145197b BC |
1037 | #ifdef CONFIG_OF |
1038 | static struct omap_i2c_bus_platform_data omap3_pdata = { | |
1039 | .rev = OMAP_I2C_IP_VERSION_1, | |
972deb4f | 1040 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
6145197b BC |
1041 | }; |
1042 | ||
1043 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
1044 | .rev = OMAP_I2C_IP_VERSION_2, | |
1045 | }; | |
1046 | ||
1047 | static const struct of_device_id omap_i2c_of_match[] = { | |
1048 | { | |
1049 | .compatible = "ti,omap4-i2c", | |
1050 | .data = &omap4_pdata, | |
1051 | }, | |
1052 | { | |
1053 | .compatible = "ti,omap3-i2c", | |
1054 | .data = &omap3_pdata, | |
1055 | }, | |
1056 | { }, | |
1057 | }; | |
1058 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
1059 | #endif | |
1060 | ||
47dcd016 S |
1061 | #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) |
1062 | ||
1063 | #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) | |
1064 | #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) | |
1065 | ||
1066 | #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) | |
1067 | #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) | |
1068 | #define OMAP_I2C_SCHEME_0 0 | |
1069 | #define OMAP_I2C_SCHEME_1 1 | |
1070 | ||
0b255e92 | 1071 | static int |
010d442c KS |
1072 | omap_i2c_probe(struct platform_device *pdev) |
1073 | { | |
1074 | struct omap_i2c_dev *dev; | |
1075 | struct i2c_adapter *adap; | |
ac79e4b2 | 1076 | struct resource *mem; |
c4dba011 UKK |
1077 | const struct omap_i2c_bus_platform_data *pdata = |
1078 | pdev->dev.platform_data; | |
6145197b BC |
1079 | struct device_node *node = pdev->dev.of_node; |
1080 | const struct of_device_id *match; | |
ac79e4b2 | 1081 | int irq; |
010d442c | 1082 | int r; |
47dcd016 | 1083 | u32 rev; |
4368de19 | 1084 | u16 minor, major; |
010d442c | 1085 | |
ac79e4b2 FB |
1086 | irq = platform_get_irq(pdev, 0); |
1087 | if (irq < 0) { | |
010d442c | 1088 | dev_err(&pdev->dev, "no irq resource?\n"); |
ac79e4b2 | 1089 | return irq; |
010d442c KS |
1090 | } |
1091 | ||
d9ebd04d FB |
1092 | dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1093 | if (!dev) { | |
1094 | dev_err(&pdev->dev, "Menory allocation failed\n"); | |
1095 | return -ENOMEM; | |
010d442c KS |
1096 | } |
1097 | ||
3cc2d009 | 1098 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
1099 | dev->base = devm_ioremap_resource(&pdev->dev, mem); |
1100 | if (IS_ERR(dev->base)) | |
1101 | return PTR_ERR(dev->base); | |
010d442c | 1102 | |
6c5aa407 | 1103 | match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); |
6145197b BC |
1104 | if (match) { |
1105 | u32 freq = 100000; /* default to 100000 Hz */ | |
1106 | ||
1107 | pdata = match->data; | |
6145197b BC |
1108 | dev->flags = pdata->flags; |
1109 | ||
1110 | of_property_read_u32(node, "clock-frequency", &freq); | |
1111 | /* convert DT freq value in Hz into kHz for speed */ | |
1112 | dev->speed = freq / 1000; | |
1113 | } else if (pdata != NULL) { | |
1114 | dev->speed = pdata->clkrate; | |
1115 | dev->flags = pdata->flags; | |
49839dc9 | 1116 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; |
20c9d2c4 | 1117 | } |
4574eb68 | 1118 | |
010d442c | 1119 | dev->dev = &pdev->dev; |
ac79e4b2 | 1120 | dev->irq = irq; |
55c381e4 | 1121 | |
3b2f8f82 | 1122 | spin_lock_init(&dev->lock); |
55c381e4 | 1123 | |
010d442c | 1124 | platform_set_drvdata(pdev, dev); |
0e33bbb2 | 1125 | init_completion(&dev->cmd_complete); |
010d442c | 1126 | |
6145197b | 1127 | dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1128 | |
7f4b08ee | 1129 | pm_runtime_enable(dev->dev); |
6d8451d5 FB |
1130 | pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); |
1131 | pm_runtime_use_autosuspend(dev->dev); | |
1132 | ||
3b0fb97c S |
1133 | r = pm_runtime_get_sync(dev->dev); |
1134 | if (IS_ERR_VALUE(r)) | |
1135 | goto err_free_mem; | |
010d442c | 1136 | |
47dcd016 S |
1137 | /* |
1138 | * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. | |
1139 | * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. | |
1140 | * Also since the omap_i2c_read_reg uses reg_map_ip_* a | |
1141 | * raw_readw is done. | |
1142 | */ | |
1143 | rev = __raw_readw(dev->base + 0x04); | |
1144 | ||
4368de19 OD |
1145 | dev->scheme = OMAP_I2C_SCHEME(rev); |
1146 | switch (dev->scheme) { | |
47dcd016 S |
1147 | case OMAP_I2C_SCHEME_0: |
1148 | dev->regs = (u8 *)reg_map_ip_v1; | |
1149 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); | |
1150 | minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); | |
1151 | major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); | |
1152 | break; | |
1153 | case OMAP_I2C_SCHEME_1: | |
1154 | /* FALLTHROUGH */ | |
1155 | default: | |
1156 | dev->regs = (u8 *)reg_map_ip_v2; | |
1157 | rev = (rev << 16) | | |
1158 | omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO); | |
1159 | minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); | |
1160 | major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); | |
1161 | dev->rev = rev; | |
1162 | } | |
010d442c | 1163 | |
9aa8ec67 TK |
1164 | dev->errata = 0; |
1165 | ||
a748021c S |
1166 | if (dev->rev >= OMAP_I2C_REV_ON_2430 && |
1167 | dev->rev < OMAP_I2C_REV_ON_4430_PLUS) | |
9aa8ec67 TK |
1168 | dev->errata |= I2C_OMAP_ERRATA_I207; |
1169 | ||
f518b482 | 1170 | if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) |
c8db38f0 | 1171 | dev->errata |= I2C_OMAP_ERRATA_I462; |
8a9d97d3 | 1172 | |
6145197b | 1173 | if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1174 | u16 s; |
1175 | ||
1176 | /* Set up the fifo size - Get total size */ | |
1177 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1178 | dev->fifo_size = 0x8 << s; | |
1179 | ||
1180 | /* | |
1181 | * Set up notification threshold as half the total available | |
1182 | * size. This is to ensure that we can handle the status on int | |
1183 | * call back latencies. | |
1184 | */ | |
1d5a34fe S |
1185 | |
1186 | dev->fifo_size = (dev->fifo_size / 2); | |
1187 | ||
47dcd016 | 1188 | if (dev->rev < OMAP_I2C_REV_ON_3630) |
f38e66e0 | 1189 | dev->b_hw = 1; /* Enable hardware fixes */ |
1d5a34fe | 1190 | |
20c9d2c4 | 1191 | /* calculate wakeup latency constraint for MPU */ |
49839dc9 PW |
1192 | if (dev->set_mpu_wkup_lat != NULL) |
1193 | dev->latency = (1000000 * dev->fifo_size) / | |
1194 | (1000 * dev->speed / 8); | |
b6ee52c3 NM |
1195 | } |
1196 | ||
010d442c KS |
1197 | /* reset ASAP, clearing any IRQs */ |
1198 | omap_i2c_init(dev); | |
1199 | ||
3b2f8f82 FB |
1200 | if (dev->rev < OMAP_I2C_OMAP1_REV_2) |
1201 | r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, | |
1202 | IRQF_NO_SUSPEND, pdev->name, dev); | |
1203 | else | |
1204 | r = devm_request_threaded_irq(&pdev->dev, dev->irq, | |
1205 | omap_i2c_isr, omap_i2c_isr_thread, | |
1206 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
1207 | pdev->name, dev); | |
010d442c KS |
1208 | |
1209 | if (r) { | |
1210 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1211 | goto err_unuse_clocks; | |
1212 | } | |
9c76b878 | 1213 | |
010d442c KS |
1214 | adap = &dev->adapter; |
1215 | i2c_set_adapdata(adap, dev); | |
1216 | adap->owner = THIS_MODULE; | |
1217 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1218 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1219 | adap->algo = &omap_i2c_algo; |
1220 | adap->dev.parent = &pdev->dev; | |
6145197b | 1221 | adap->dev.of_node = pdev->dev.of_node; |
010d442c KS |
1222 | |
1223 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1224 | adap->nr = pdev->id; |
1225 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1226 | if (r) { |
1227 | dev_err(dev->dev, "failure adding adapter\n"); | |
d9ebd04d | 1228 | goto err_unuse_clocks; |
010d442c KS |
1229 | } |
1230 | ||
cd10c74a S |
1231 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, |
1232 | major, minor, dev->speed); | |
c5d3cd6d | 1233 | |
6145197b BC |
1234 | of_i2c_register_devices(adap); |
1235 | ||
6d8451d5 FB |
1236 | pm_runtime_mark_last_busy(dev->dev); |
1237 | pm_runtime_put_autosuspend(dev->dev); | |
62ff2c2b | 1238 | |
010d442c KS |
1239 | return 0; |
1240 | ||
010d442c | 1241 | err_unuse_clocks: |
3e39752d | 1242 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
fab67afb | 1243 | pm_runtime_put(dev->dev); |
24740516 | 1244 | pm_runtime_disable(&pdev->dev); |
010d442c | 1245 | err_free_mem: |
010d442c KS |
1246 | |
1247 | return r; | |
1248 | } | |
1249 | ||
0b255e92 | 1250 | static int omap_i2c_remove(struct platform_device *pdev) |
010d442c KS |
1251 | { |
1252 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
3b0fb97c | 1253 | int ret; |
010d442c | 1254 | |
010d442c | 1255 | i2c_del_adapter(&dev->adapter); |
3b0fb97c S |
1256 | ret = pm_runtime_get_sync(&pdev->dev); |
1257 | if (IS_ERR_VALUE(ret)) | |
1258 | return ret; | |
1259 | ||
010d442c | 1260 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
0861f430 | 1261 | pm_runtime_put(&pdev->dev); |
24740516 | 1262 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1263 | return 0; |
1264 | } | |
1265 | ||
5692d2a2 | 1266 | #ifdef CONFIG_PM |
fab67afb KH |
1267 | #ifdef CONFIG_PM_RUNTIME |
1268 | static int omap_i2c_runtime_suspend(struct device *dev) | |
1269 | { | |
1270 | struct platform_device *pdev = to_platform_device(dev); | |
1271 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
3dae3efb S |
1272 | |
1273 | _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); | |
bd16c82f | 1274 | |
4368de19 OD |
1275 | if (_dev->scheme == OMAP_I2C_SCHEME_0) |
1276 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); | |
1277 | else | |
1278 | omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
1279 | OMAP_I2C_IP_V2_INTERRUPTS_MASK); | |
fab67afb | 1280 | |
3dae3efb | 1281 | if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { |
27e0fbef | 1282 | omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ |
3dae3efb S |
1283 | } else { |
1284 | omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); | |
fab67afb | 1285 | |
3dae3efb S |
1286 | /* Flush posted write */ |
1287 | omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); | |
1288 | } | |
fab67afb KH |
1289 | |
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | static int omap_i2c_runtime_resume(struct device *dev) | |
1294 | { | |
1295 | struct platform_device *pdev = to_platform_device(dev); | |
1296 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
1297 | ||
47dcd016 S |
1298 | if (!_dev->regs) |
1299 | return 0; | |
1300 | ||
554c9674 | 1301 | __omap_i2c_init(_dev); |
fab67afb KH |
1302 | |
1303 | return 0; | |
1304 | } | |
5692d2a2 | 1305 | #endif /* CONFIG_PM_RUNTIME */ |
fab67afb KH |
1306 | |
1307 | static struct dev_pm_ops omap_i2c_pm_ops = { | |
5692d2a2 S |
1308 | SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, |
1309 | omap_i2c_runtime_resume, NULL) | |
fab67afb KH |
1310 | }; |
1311 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) | |
1312 | #else | |
1313 | #define OMAP_I2C_PM_OPS NULL | |
5692d2a2 | 1314 | #endif /* CONFIG_PM */ |
fab67afb | 1315 | |
010d442c KS |
1316 | static struct platform_driver omap_i2c_driver = { |
1317 | .probe = omap_i2c_probe, | |
0b255e92 | 1318 | .remove = omap_i2c_remove, |
010d442c | 1319 | .driver = { |
f7bb0d9a | 1320 | .name = "omap_i2c", |
010d442c | 1321 | .owner = THIS_MODULE, |
fab67afb | 1322 | .pm = OMAP_I2C_PM_OPS, |
6145197b | 1323 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1324 | }, |
1325 | }; | |
1326 | ||
1327 | /* I2C may be needed to bring up other drivers */ | |
1328 | static int __init | |
1329 | omap_i2c_init_driver(void) | |
1330 | { | |
1331 | return platform_driver_register(&omap_i2c_driver); | |
1332 | } | |
1333 | subsys_initcall(omap_i2c_init_driver); | |
1334 | ||
1335 | static void __exit omap_i2c_exit_driver(void) | |
1336 | { | |
1337 | platform_driver_unregister(&omap_i2c_driver); | |
1338 | } | |
1339 | module_exit(omap_i2c_exit_driver); | |
1340 | ||
1341 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1342 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1343 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1344 | MODULE_ALIAS("platform:omap_i2c"); |