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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and |
3 | Philip Edelbrock <phil@netroedge.com> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
1da177e4 LT |
14 | */ |
15 | ||
16 | /* | |
17 | Supports: | |
18 | Intel PIIX4, 440MX | |
506a8b6c | 19 | Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 |
2a2f7404 | 20 | ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 |
032f708b | 21 | AMD Hudson-2, ML, CZ |
1da177e4 LT |
22 | SMSC Victory66 |
23 | ||
2a2f7404 AA |
24 | Note: we assume there can only be one device, with one or more |
25 | SMBus interfaces. | |
2fee61d2 CF |
26 | The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). |
27 | For devices supporting multiple ports the i2c_adapter should provide | |
28 | an i2c_algorithm to access them. | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 LT |
31 | #include <linux/module.h> |
32 | #include <linux/moduleparam.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/stddef.h> | |
1da177e4 LT |
37 | #include <linux/ioport.h> |
38 | #include <linux/i2c.h> | |
c415b303 | 39 | #include <linux/slab.h> |
1da177e4 | 40 | #include <linux/dmi.h> |
54fb4a05 | 41 | #include <linux/acpi.h> |
21782180 | 42 | #include <linux/io.h> |
2fee61d2 | 43 | #include <linux/mutex.h> |
1da177e4 LT |
44 | |
45 | ||
1da177e4 LT |
46 | /* PIIX4 SMBus address offsets */ |
47 | #define SMBHSTSTS (0 + piix4_smba) | |
48 | #define SMBHSLVSTS (1 + piix4_smba) | |
49 | #define SMBHSTCNT (2 + piix4_smba) | |
50 | #define SMBHSTCMD (3 + piix4_smba) | |
51 | #define SMBHSTADD (4 + piix4_smba) | |
52 | #define SMBHSTDAT0 (5 + piix4_smba) | |
53 | #define SMBHSTDAT1 (6 + piix4_smba) | |
54 | #define SMBBLKDAT (7 + piix4_smba) | |
55 | #define SMBSLVCNT (8 + piix4_smba) | |
56 | #define SMBSHDWCMD (9 + piix4_smba) | |
57 | #define SMBSLVEVT (0xA + piix4_smba) | |
58 | #define SMBSLVDAT (0xC + piix4_smba) | |
59 | ||
60 | /* count for request_region */ | |
61 | #define SMBIOSIZE 8 | |
62 | ||
63 | /* PCI Address Constants */ | |
64 | #define SMBBA 0x090 | |
65 | #define SMBHSTCFG 0x0D2 | |
66 | #define SMBSLVC 0x0D3 | |
67 | #define SMBSHDW1 0x0D4 | |
68 | #define SMBSHDW2 0x0D5 | |
69 | #define SMBREV 0x0D6 | |
70 | ||
71 | /* Other settings */ | |
72 | #define MAX_TIMEOUT 500 | |
73 | #define ENABLE_INT9 0 | |
74 | ||
75 | /* PIIX4 constants */ | |
76 | #define PIIX4_QUICK 0x00 | |
77 | #define PIIX4_BYTE 0x04 | |
78 | #define PIIX4_BYTE_DATA 0x08 | |
79 | #define PIIX4_WORD_DATA 0x0C | |
80 | #define PIIX4_BLOCK_DATA 0x14 | |
81 | ||
ca2061e1 CF |
82 | /* Multi-port constants */ |
83 | #define PIIX4_MAX_ADAPTERS 4 | |
84 | ||
2fee61d2 CF |
85 | /* SB800 constants */ |
86 | #define SB800_PIIX4_SMB_IDX 0xcd6 | |
87 | ||
88 | /* SB800 port is selected by bits 2:1 of the smb_en register (0x2c) */ | |
89 | #define SB800_PIIX4_PORT_IDX 0x2c | |
90 | #define SB800_PIIX4_PORT_IDX_MASK 0x06 | |
91 | ||
1da177e4 LT |
92 | /* insmod parameters */ |
93 | ||
94 | /* If force is set to anything different from 0, we forcibly enable the | |
95 | PIIX4. DANGEROUS! */ | |
60507095 | 96 | static int force; |
1da177e4 LT |
97 | module_param (force, int, 0); |
98 | MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); | |
99 | ||
100 | /* If force_addr is set to anything different from 0, we forcibly enable | |
101 | the PIIX4 at the given address. VERY DANGEROUS! */ | |
60507095 | 102 | static int force_addr; |
1da177e4 LT |
103 | module_param (force_addr, int, 0); |
104 | MODULE_PARM_DESC(force_addr, | |
105 | "Forcibly enable the PIIX4 at the given address. " | |
106 | "EXTREMELY DANGEROUS!"); | |
107 | ||
b1c1759c | 108 | static int srvrworks_csb5_delay; |
d6072f84 | 109 | static struct pci_driver piix4_driver; |
1da177e4 | 110 | |
0b255e92 | 111 | static const struct dmi_system_id piix4_dmi_blacklist[] = { |
c2fc54fc JD |
112 | { |
113 | .ident = "Sapphire AM2RD790", | |
114 | .matches = { | |
115 | DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), | |
116 | DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), | |
117 | }, | |
118 | }, | |
119 | { | |
120 | .ident = "DFI Lanparty UT 790FX", | |
121 | .matches = { | |
122 | DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), | |
123 | DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), | |
124 | }, | |
125 | }, | |
126 | { } | |
127 | }; | |
128 | ||
129 | /* The IBM entry is in a separate table because we only check it | |
130 | on Intel-based systems */ | |
0b255e92 | 131 | static const struct dmi_system_id piix4_dmi_ibm[] = { |
1da177e4 LT |
132 | { |
133 | .ident = "IBM", | |
134 | .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, | |
135 | }, | |
136 | { }, | |
137 | }; | |
138 | ||
725d2e3f | 139 | /* SB800 globals */ |
a28e3517 | 140 | static DEFINE_MUTEX(piix4_mutex_sb800); |
725d2e3f CF |
141 | static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { |
142 | "SDA0", "SDA2", "SDA3", "SDA4" | |
143 | }; | |
144 | static const char *piix4_aux_port_name_sb800 = "SDA1"; | |
145 | ||
14a8086d AA |
146 | struct i2c_piix4_adapdata { |
147 | unsigned short smba; | |
2fee61d2 CF |
148 | |
149 | /* SB800 */ | |
150 | bool sb800_main; | |
151 | unsigned short port; | |
14a8086d AA |
152 | }; |
153 | ||
0b255e92 BP |
154 | static int piix4_setup(struct pci_dev *PIIX4_dev, |
155 | const struct pci_device_id *id) | |
1da177e4 LT |
156 | { |
157 | unsigned char temp; | |
14a8086d | 158 | unsigned short piix4_smba; |
1da177e4 | 159 | |
b1c1759c DM |
160 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && |
161 | (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) | |
162 | srvrworks_csb5_delay = 1; | |
163 | ||
c2fc54fc JD |
164 | /* On some motherboards, it was reported that accessing the SMBus |
165 | caused severe hardware problems */ | |
166 | if (dmi_check_system(piix4_dmi_blacklist)) { | |
167 | dev_err(&PIIX4_dev->dev, | |
168 | "Accessing the SMBus on this system is unsafe!\n"); | |
169 | return -EPERM; | |
170 | } | |
171 | ||
1da177e4 | 172 | /* Don't access SMBus on IBM systems which get corrupted eeproms */ |
c2fc54fc | 173 | if (dmi_check_system(piix4_dmi_ibm) && |
1da177e4 | 174 | PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { |
f9ba6c04 | 175 | dev_err(&PIIX4_dev->dev, "IBM system detected; this module " |
1da177e4 LT |
176 | "may corrupt your serial eeprom! Refusing to load " |
177 | "module!\n"); | |
178 | return -EPERM; | |
179 | } | |
180 | ||
181 | /* Determine the address of the SMBus areas */ | |
182 | if (force_addr) { | |
183 | piix4_smba = force_addr & 0xfff0; | |
184 | force = 0; | |
185 | } else { | |
186 | pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); | |
187 | piix4_smba &= 0xfff0; | |
188 | if(piix4_smba == 0) { | |
fa63cd56 | 189 | dev_err(&PIIX4_dev->dev, "SMBus base address " |
1da177e4 LT |
190 | "uninitialized - upgrade BIOS or use " |
191 | "force_addr=0xaddr\n"); | |
192 | return -ENODEV; | |
193 | } | |
194 | } | |
195 | ||
54fb4a05 | 196 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 197 | return -ENODEV; |
54fb4a05 | 198 | |
d6072f84 | 199 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { |
fa63cd56 | 200 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", |
1da177e4 | 201 | piix4_smba); |
fa63cd56 | 202 | return -EBUSY; |
1da177e4 LT |
203 | } |
204 | ||
205 | pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); | |
206 | ||
1da177e4 LT |
207 | /* If force_addr is set, we program the new address here. Just to make |
208 | sure, we disable the PIIX4 first. */ | |
209 | if (force_addr) { | |
210 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); | |
211 | pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); | |
212 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); | |
213 | dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " | |
214 | "new address %04x!\n", piix4_smba); | |
215 | } else if ((temp & 1) == 0) { | |
216 | if (force) { | |
217 | /* This should never need to be done, but has been | |
218 | * noted that many Dell machines have the SMBus | |
219 | * interface on the PIIX4 disabled!? NOTE: This assumes | |
220 | * I/O space and other allocations WERE done by the | |
221 | * Bios! Don't complain if your hardware does weird | |
222 | * things after enabling this. :') Check for Bios | |
223 | * updates before resorting to this. | |
224 | */ | |
225 | pci_write_config_byte(PIIX4_dev, SMBHSTCFG, | |
226 | temp | 1); | |
8117e41e JP |
227 | dev_notice(&PIIX4_dev->dev, |
228 | "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); | |
1da177e4 LT |
229 | } else { |
230 | dev_err(&PIIX4_dev->dev, | |
66f8a8ff | 231 | "SMBus Host Controller not enabled!\n"); |
1da177e4 | 232 | release_region(piix4_smba, SMBIOSIZE); |
1da177e4 LT |
233 | return -ENODEV; |
234 | } | |
235 | } | |
236 | ||
54aaa1ca | 237 | if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) |
66f8a8ff | 238 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); |
1da177e4 | 239 | else if ((temp & 0x0E) == 0) |
66f8a8ff | 240 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); |
1da177e4 LT |
241 | else |
242 | dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " | |
243 | "(or code out of date)!\n"); | |
244 | ||
245 | pci_read_config_byte(PIIX4_dev, SMBREV, &temp); | |
fa63cd56 JD |
246 | dev_info(&PIIX4_dev->dev, |
247 | "SMBus Host Controller at 0x%x, revision %d\n", | |
248 | piix4_smba, temp); | |
1da177e4 | 249 | |
14a8086d | 250 | return piix4_smba; |
1da177e4 LT |
251 | } |
252 | ||
0b255e92 | 253 | static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, |
a94dd00f | 254 | const struct pci_device_id *id, u8 aux) |
87e1960e | 255 | { |
14a8086d | 256 | unsigned short piix4_smba; |
032f708b SH |
257 | u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status; |
258 | u8 i2ccfg, i2ccfg_offset = 0x10; | |
87e1960e | 259 | |
3806e94b | 260 | /* SB800 and later SMBus does not support forcing address */ |
87e1960e | 261 | if (force || force_addr) { |
3806e94b | 262 | dev_err(&PIIX4_dev->dev, "SMBus does not support " |
87e1960e SH |
263 | "forcing address!\n"); |
264 | return -EINVAL; | |
265 | } | |
266 | ||
267 | /* Determine the address of the SMBus areas */ | |
032f708b SH |
268 | if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && |
269 | PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && | |
270 | PIIX4_dev->revision >= 0x41) || | |
271 | (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && | |
bcb29994 | 272 | PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && |
032f708b SH |
273 | PIIX4_dev->revision >= 0x49)) |
274 | smb_en = 0x00; | |
275 | else | |
276 | smb_en = (aux) ? 0x28 : 0x2c; | |
a94dd00f | 277 | |
a28e3517 | 278 | mutex_lock(&piix4_mutex_sb800); |
2fee61d2 CF |
279 | outb_p(smb_en, SB800_PIIX4_SMB_IDX); |
280 | smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); | |
281 | outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); | |
282 | smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); | |
a28e3517 | 283 | mutex_unlock(&piix4_mutex_sb800); |
87e1960e | 284 | |
032f708b SH |
285 | if (!smb_en) { |
286 | smb_en_status = smba_en_lo & 0x10; | |
287 | piix4_smba = smba_en_hi << 8; | |
288 | if (aux) | |
289 | piix4_smba |= 0x20; | |
290 | } else { | |
291 | smb_en_status = smba_en_lo & 0x01; | |
292 | piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; | |
293 | } | |
294 | ||
295 | if (!smb_en_status) { | |
87e1960e | 296 | dev_err(&PIIX4_dev->dev, |
66f8a8ff | 297 | "SMBus Host Controller not enabled!\n"); |
87e1960e SH |
298 | return -ENODEV; |
299 | } | |
300 | ||
87e1960e | 301 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) |
18669eab | 302 | return -ENODEV; |
87e1960e SH |
303 | |
304 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
305 | dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", | |
306 | piix4_smba); | |
307 | return -EBUSY; | |
308 | } | |
309 | ||
a94dd00f RM |
310 | /* Aux SMBus does not support IRQ information */ |
311 | if (aux) { | |
312 | dev_info(&PIIX4_dev->dev, | |
85fd0fe6 SH |
313 | "Auxiliary SMBus Host Controller at 0x%x\n", |
314 | piix4_smba); | |
a94dd00f RM |
315 | return piix4_smba; |
316 | } | |
317 | ||
87e1960e SH |
318 | /* Request the SMBus I2C bus config region */ |
319 | if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { | |
320 | dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " | |
321 | "0x%x already in use!\n", piix4_smba + i2ccfg_offset); | |
322 | release_region(piix4_smba, SMBIOSIZE); | |
87e1960e SH |
323 | return -EBUSY; |
324 | } | |
325 | i2ccfg = inb_p(piix4_smba + i2ccfg_offset); | |
326 | release_region(piix4_smba + i2ccfg_offset, 1); | |
327 | ||
328 | if (i2ccfg & 1) | |
66f8a8ff | 329 | dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); |
87e1960e | 330 | else |
66f8a8ff | 331 | dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); |
87e1960e SH |
332 | |
333 | dev_info(&PIIX4_dev->dev, | |
334 | "SMBus Host Controller at 0x%x, revision %d\n", | |
335 | piix4_smba, i2ccfg >> 4); | |
336 | ||
14a8086d | 337 | return piix4_smba; |
87e1960e SH |
338 | } |
339 | ||
0b255e92 BP |
340 | static int piix4_setup_aux(struct pci_dev *PIIX4_dev, |
341 | const struct pci_device_id *id, | |
342 | unsigned short base_reg_addr) | |
2a2f7404 AA |
343 | { |
344 | /* Set up auxiliary SMBus controllers found on some | |
345 | * AMD chipsets e.g. SP5100 (SB700 derivative) */ | |
346 | ||
347 | unsigned short piix4_smba; | |
348 | ||
349 | /* Read address of auxiliary SMBus controller */ | |
350 | pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); | |
351 | if ((piix4_smba & 1) == 0) { | |
352 | dev_dbg(&PIIX4_dev->dev, | |
353 | "Auxiliary SMBus controller not enabled\n"); | |
354 | return -ENODEV; | |
355 | } | |
356 | ||
357 | piix4_smba &= 0xfff0; | |
358 | if (piix4_smba == 0) { | |
359 | dev_dbg(&PIIX4_dev->dev, | |
360 | "Auxiliary SMBus base address uninitialized\n"); | |
361 | return -ENODEV; | |
362 | } | |
363 | ||
364 | if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) | |
365 | return -ENODEV; | |
366 | ||
367 | if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { | |
368 | dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " | |
369 | "already in use!\n", piix4_smba); | |
370 | return -EBUSY; | |
371 | } | |
372 | ||
373 | dev_info(&PIIX4_dev->dev, | |
374 | "Auxiliary SMBus Host Controller at 0x%x\n", | |
375 | piix4_smba); | |
376 | ||
377 | return piix4_smba; | |
378 | } | |
379 | ||
e154bf6f | 380 | static int piix4_transaction(struct i2c_adapter *piix4_adapter) |
1da177e4 | 381 | { |
e154bf6f AA |
382 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); |
383 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 LT |
384 | int temp; |
385 | int result = 0; | |
386 | int timeout = 0; | |
387 | ||
e154bf6f | 388 | dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
389 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
390 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
391 | inb_p(SMBHSTDAT1)); | |
392 | ||
393 | /* Make sure the SMBus host is ready to start transmitting */ | |
394 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 395 | dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " |
541e6a02 | 396 | "Resetting...\n", temp); |
1da177e4 LT |
397 | outb_p(temp, SMBHSTSTS); |
398 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 399 | dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); |
97140342 | 400 | return -EBUSY; |
1da177e4 | 401 | } else { |
e154bf6f | 402 | dev_dbg(&piix4_adapter->dev, "Successful!\n"); |
1da177e4 LT |
403 | } |
404 | } | |
405 | ||
406 | /* start the transaction by setting bit 6 */ | |
407 | outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); | |
408 | ||
409 | /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ | |
b1c1759c DM |
410 | if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ |
411 | msleep(2); | |
412 | else | |
413 | msleep(1); | |
414 | ||
b6a31950 | 415 | while ((++timeout < MAX_TIMEOUT) && |
b1c1759c | 416 | ((temp = inb_p(SMBHSTSTS)) & 0x01)) |
1da177e4 | 417 | msleep(1); |
1da177e4 LT |
418 | |
419 | /* If the SMBus is still busy, we give up */ | |
b6a31950 | 420 | if (timeout == MAX_TIMEOUT) { |
e154bf6f | 421 | dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); |
97140342 | 422 | result = -ETIMEDOUT; |
1da177e4 LT |
423 | } |
424 | ||
425 | if (temp & 0x10) { | |
97140342 | 426 | result = -EIO; |
e154bf6f | 427 | dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); |
1da177e4 LT |
428 | } |
429 | ||
430 | if (temp & 0x08) { | |
97140342 | 431 | result = -EIO; |
e154bf6f | 432 | dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " |
1da177e4 LT |
433 | "locked until next hard reset. (sorry!)\n"); |
434 | /* Clock stops and slave is stuck in mid-transmission */ | |
435 | } | |
436 | ||
437 | if (temp & 0x04) { | |
97140342 | 438 | result = -ENXIO; |
e154bf6f | 439 | dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); |
1da177e4 LT |
440 | } |
441 | ||
442 | if (inb_p(SMBHSTSTS) != 0x00) | |
443 | outb_p(inb(SMBHSTSTS), SMBHSTSTS); | |
444 | ||
445 | if ((temp = inb_p(SMBHSTSTS)) != 0x00) { | |
e154bf6f | 446 | dev_err(&piix4_adapter->dev, "Failed reset at end of " |
1da177e4 LT |
447 | "transaction (%02x)\n", temp); |
448 | } | |
e154bf6f | 449 | dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " |
1da177e4 LT |
450 | "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), |
451 | inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), | |
452 | inb_p(SMBHSTDAT1)); | |
453 | return result; | |
454 | } | |
455 | ||
97140342 | 456 | /* Return negative errno on error. */ |
1da177e4 LT |
457 | static s32 piix4_access(struct i2c_adapter * adap, u16 addr, |
458 | unsigned short flags, char read_write, | |
459 | u8 command, int size, union i2c_smbus_data * data) | |
460 | { | |
14a8086d AA |
461 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
462 | unsigned short piix4_smba = adapdata->smba; | |
1da177e4 | 463 | int i, len; |
97140342 | 464 | int status; |
1da177e4 LT |
465 | |
466 | switch (size) { | |
1da177e4 | 467 | case I2C_SMBUS_QUICK: |
fa63cd56 | 468 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
469 | SMBHSTADD); |
470 | size = PIIX4_QUICK; | |
471 | break; | |
472 | case I2C_SMBUS_BYTE: | |
fa63cd56 | 473 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
474 | SMBHSTADD); |
475 | if (read_write == I2C_SMBUS_WRITE) | |
476 | outb_p(command, SMBHSTCMD); | |
477 | size = PIIX4_BYTE; | |
478 | break; | |
479 | case I2C_SMBUS_BYTE_DATA: | |
fa63cd56 | 480 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
481 | SMBHSTADD); |
482 | outb_p(command, SMBHSTCMD); | |
483 | if (read_write == I2C_SMBUS_WRITE) | |
484 | outb_p(data->byte, SMBHSTDAT0); | |
485 | size = PIIX4_BYTE_DATA; | |
486 | break; | |
487 | case I2C_SMBUS_WORD_DATA: | |
fa63cd56 | 488 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
489 | SMBHSTADD); |
490 | outb_p(command, SMBHSTCMD); | |
491 | if (read_write == I2C_SMBUS_WRITE) { | |
492 | outb_p(data->word & 0xff, SMBHSTDAT0); | |
493 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | |
494 | } | |
495 | size = PIIX4_WORD_DATA; | |
496 | break; | |
497 | case I2C_SMBUS_BLOCK_DATA: | |
fa63cd56 | 498 | outb_p((addr << 1) | read_write, |
1da177e4 LT |
499 | SMBHSTADD); |
500 | outb_p(command, SMBHSTCMD); | |
501 | if (read_write == I2C_SMBUS_WRITE) { | |
502 | len = data->block[0]; | |
fa63cd56 JD |
503 | if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) |
504 | return -EINVAL; | |
1da177e4 | 505 | outb_p(len, SMBHSTDAT0); |
d7a4c763 | 506 | inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
1da177e4 LT |
507 | for (i = 1; i <= len; i++) |
508 | outb_p(data->block[i], SMBBLKDAT); | |
509 | } | |
510 | size = PIIX4_BLOCK_DATA; | |
511 | break; | |
ac7fc4fb JD |
512 | default: |
513 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); | |
514 | return -EOPNOTSUPP; | |
1da177e4 LT |
515 | } |
516 | ||
517 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); | |
518 | ||
e154bf6f | 519 | status = piix4_transaction(adap); |
97140342 DB |
520 | if (status) |
521 | return status; | |
1da177e4 LT |
522 | |
523 | if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) | |
524 | return 0; | |
525 | ||
526 | ||
527 | switch (size) { | |
3578a075 | 528 | case PIIX4_BYTE: |
1da177e4 LT |
529 | case PIIX4_BYTE_DATA: |
530 | data->byte = inb_p(SMBHSTDAT0); | |
531 | break; | |
532 | case PIIX4_WORD_DATA: | |
533 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | |
534 | break; | |
535 | case PIIX4_BLOCK_DATA: | |
536 | data->block[0] = inb_p(SMBHSTDAT0); | |
fa63cd56 JD |
537 | if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) |
538 | return -EPROTO; | |
d7a4c763 | 539 | inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ |
1da177e4 LT |
540 | for (i = 1; i <= data->block[0]; i++) |
541 | data->block[i] = inb_p(SMBBLKDAT); | |
542 | break; | |
543 | } | |
544 | return 0; | |
545 | } | |
546 | ||
2fee61d2 CF |
547 | /* |
548 | * Handles access to multiple SMBus ports on the SB800. | |
549 | * The port is selected by bits 2:1 of the smb_en register (0x2c). | |
550 | * Returns negative errno on error. | |
551 | * | |
552 | * Note: The selected port must be returned to the initial selection to avoid | |
553 | * problems on certain systems. | |
554 | */ | |
555 | static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, | |
556 | unsigned short flags, char read_write, | |
557 | u8 command, int size, union i2c_smbus_data *data) | |
558 | { | |
559 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); | |
560 | u8 smba_en_lo; | |
561 | u8 port; | |
562 | int retval; | |
563 | ||
a28e3517 | 564 | mutex_lock(&piix4_mutex_sb800); |
2fee61d2 CF |
565 | |
566 | outb_p(SB800_PIIX4_PORT_IDX, SB800_PIIX4_SMB_IDX); | |
567 | smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); | |
568 | ||
569 | port = adapdata->port; | |
570 | if ((smba_en_lo & SB800_PIIX4_PORT_IDX_MASK) != (port << 1)) | |
571 | outb_p((smba_en_lo & ~SB800_PIIX4_PORT_IDX_MASK) | (port << 1), | |
572 | SB800_PIIX4_SMB_IDX + 1); | |
573 | ||
574 | retval = piix4_access(adap, addr, flags, read_write, | |
575 | command, size, data); | |
576 | ||
577 | outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1); | |
578 | ||
a28e3517 | 579 | mutex_unlock(&piix4_mutex_sb800); |
2fee61d2 CF |
580 | |
581 | return retval; | |
582 | } | |
583 | ||
1da177e4 LT |
584 | static u32 piix4_func(struct i2c_adapter *adapter) |
585 | { | |
586 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | |
587 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | |
588 | I2C_FUNC_SMBUS_BLOCK_DATA; | |
589 | } | |
590 | ||
8f9082c5 | 591 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
592 | .smbus_xfer = piix4_access, |
593 | .functionality = piix4_func, | |
594 | }; | |
595 | ||
2fee61d2 CF |
596 | static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { |
597 | .smbus_xfer = piix4_access_sb800, | |
598 | .functionality = piix4_func, | |
599 | }; | |
600 | ||
392debf1 | 601 | static const struct pci_device_id piix4_ids[] = { |
9b7389c0 JD |
602 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, |
603 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, | |
604 | { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, | |
605 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, | |
606 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, | |
607 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, | |
608 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, | |
3806e94b | 609 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, |
bcb29994 | 610 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, |
9b7389c0 JD |
611 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
612 | PCI_DEVICE_ID_SERVERWORKS_OSB4) }, | |
613 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
614 | PCI_DEVICE_ID_SERVERWORKS_CSB5) }, | |
615 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
616 | PCI_DEVICE_ID_SERVERWORKS_CSB6) }, | |
617 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, | |
618 | PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, | |
506a8b6c FL |
619 | { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, |
620 | PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, | |
1da177e4 LT |
621 | { 0, } |
622 | }; | |
623 | ||
624 | MODULE_DEVICE_TABLE (pci, piix4_ids); | |
625 | ||
ca2061e1 | 626 | static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; |
2a2f7404 | 627 | static struct i2c_adapter *piix4_aux_adapter; |
e154bf6f | 628 | |
0b255e92 | 629 | static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, |
83c60158 | 630 | bool sb800_main, unsigned short port, |
725d2e3f | 631 | const char *name, struct i2c_adapter **padap) |
e154bf6f AA |
632 | { |
633 | struct i2c_adapter *adap; | |
634 | struct i2c_piix4_adapdata *adapdata; | |
635 | int retval; | |
636 | ||
637 | adap = kzalloc(sizeof(*adap), GFP_KERNEL); | |
638 | if (adap == NULL) { | |
639 | release_region(smba, SMBIOSIZE); | |
640 | return -ENOMEM; | |
641 | } | |
642 | ||
643 | adap->owner = THIS_MODULE; | |
644 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
83c60158 JD |
645 | adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 |
646 | : &smbus_algorithm; | |
e154bf6f AA |
647 | |
648 | adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); | |
649 | if (adapdata == NULL) { | |
650 | kfree(adap); | |
651 | release_region(smba, SMBIOSIZE); | |
652 | return -ENOMEM; | |
653 | } | |
654 | ||
655 | adapdata->smba = smba; | |
83c60158 JD |
656 | adapdata->sb800_main = sb800_main; |
657 | adapdata->port = port; | |
e154bf6f AA |
658 | |
659 | /* set up the sysfs linkage to our parent device */ | |
660 | adap->dev.parent = &dev->dev; | |
661 | ||
662 | snprintf(adap->name, sizeof(adap->name), | |
725d2e3f | 663 | "SMBus PIIX4 adapter %s at %04x", name, smba); |
e154bf6f AA |
664 | |
665 | i2c_set_adapdata(adap, adapdata); | |
666 | ||
667 | retval = i2c_add_adapter(adap); | |
668 | if (retval) { | |
669 | dev_err(&dev->dev, "Couldn't register adapter!\n"); | |
670 | kfree(adapdata); | |
671 | kfree(adap); | |
672 | release_region(smba, SMBIOSIZE); | |
673 | return retval; | |
674 | } | |
675 | ||
676 | *padap = adap; | |
677 | return 0; | |
678 | } | |
679 | ||
2fee61d2 CF |
680 | static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba) |
681 | { | |
2fee61d2 CF |
682 | struct i2c_piix4_adapdata *adapdata; |
683 | int port; | |
684 | int retval; | |
685 | ||
2fee61d2 | 686 | for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) { |
83c60158 | 687 | retval = piix4_add_adapter(dev, smba, true, port, |
725d2e3f | 688 | piix4_main_port_names_sb800[port], |
2fee61d2 CF |
689 | &piix4_main_adapters[port]); |
690 | if (retval < 0) | |
691 | goto error; | |
2fee61d2 CF |
692 | } |
693 | ||
694 | return retval; | |
695 | ||
696 | error: | |
697 | dev_err(&dev->dev, | |
698 | "Error setting up SB800 adapters. Unregistering!\n"); | |
699 | while (--port >= 0) { | |
700 | adapdata = i2c_get_adapdata(piix4_main_adapters[port]); | |
701 | if (adapdata->smba) { | |
702 | i2c_del_adapter(piix4_main_adapters[port]); | |
703 | kfree(adapdata); | |
704 | kfree(piix4_main_adapters[port]); | |
705 | piix4_main_adapters[port] = NULL; | |
706 | } | |
707 | } | |
708 | ||
2fee61d2 CF |
709 | return retval; |
710 | } | |
711 | ||
0b255e92 | 712 | static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 LT |
713 | { |
714 | int retval; | |
715 | ||
76b3e28f CC |
716 | if ((dev->vendor == PCI_VENDOR_ID_ATI && |
717 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && | |
718 | dev->revision >= 0x40) || | |
2fee61d2 CF |
719 | dev->vendor == PCI_VENDOR_ID_AMD) { |
720 | if (!request_region(SB800_PIIX4_SMB_IDX, 2, "smba_idx")) { | |
721 | dev_err(&dev->dev, | |
722 | "SMBus base address index region 0x%x already in use!\n", | |
723 | SB800_PIIX4_SMB_IDX); | |
724 | return -EBUSY; | |
725 | } | |
726 | ||
87e1960e | 727 | /* base address location etc changed in SB800 */ |
a94dd00f | 728 | retval = piix4_setup_sb800(dev, id, 0); |
2fee61d2 CF |
729 | if (retval < 0) { |
730 | release_region(SB800_PIIX4_SMB_IDX, 2); | |
731 | return retval; | |
732 | } | |
87e1960e | 733 | |
2fee61d2 CF |
734 | /* |
735 | * Try to register multiplexed main SMBus adapter, | |
736 | * give up if we can't | |
737 | */ | |
738 | retval = piix4_add_adapters_sb800(dev, retval); | |
739 | if (retval < 0) { | |
740 | release_region(SB800_PIIX4_SMB_IDX, 2); | |
741 | return retval; | |
742 | } | |
743 | } else { | |
744 | retval = piix4_setup(dev, id); | |
745 | if (retval < 0) | |
746 | return retval; | |
1da177e4 | 747 | |
2fee61d2 | 748 | /* Try to register main SMBus adapter, give up if we can't */ |
83c60158 | 749 | retval = piix4_add_adapter(dev, retval, false, 0, "main", |
2fee61d2 CF |
750 | &piix4_main_adapters[0]); |
751 | if (retval < 0) | |
752 | return retval; | |
753 | } | |
2a2f7404 AA |
754 | |
755 | /* Check for auxiliary SMBus on some AMD chipsets */ | |
a94dd00f RM |
756 | retval = -ENODEV; |
757 | ||
2a2f7404 | 758 | if (dev->vendor == PCI_VENDOR_ID_ATI && |
a94dd00f RM |
759 | dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { |
760 | if (dev->revision < 0x40) { | |
761 | retval = piix4_setup_aux(dev, id, 0x58); | |
762 | } else { | |
763 | /* SB800 added aux bus too */ | |
764 | retval = piix4_setup_sb800(dev, id, 1); | |
2a2f7404 AA |
765 | } |
766 | } | |
767 | ||
a94dd00f RM |
768 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
769 | dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { | |
770 | retval = piix4_setup_sb800(dev, id, 1); | |
771 | } | |
772 | ||
773 | if (retval > 0) { | |
774 | /* Try to add the aux adapter if it exists, | |
775 | * piix4_add_adapter will clean up if this fails */ | |
83c60158 JD |
776 | piix4_add_adapter(dev, retval, false, 0, |
777 | piix4_aux_port_name_sb800, | |
725d2e3f | 778 | &piix4_aux_adapter); |
a94dd00f RM |
779 | } |
780 | ||
2a2f7404 | 781 | return 0; |
1da177e4 LT |
782 | } |
783 | ||
0b255e92 | 784 | static void piix4_adap_remove(struct i2c_adapter *adap) |
1da177e4 | 785 | { |
14a8086d AA |
786 | struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); |
787 | ||
788 | if (adapdata->smba) { | |
789 | i2c_del_adapter(adap); | |
2fee61d2 CF |
790 | if (adapdata->port == 0) { |
791 | release_region(adapdata->smba, SMBIOSIZE); | |
a28e3517 | 792 | if (adapdata->sb800_main) |
2fee61d2 | 793 | release_region(SB800_PIIX4_SMB_IDX, 2); |
2fee61d2 | 794 | } |
e154bf6f AA |
795 | kfree(adapdata); |
796 | kfree(adap); | |
1da177e4 LT |
797 | } |
798 | } | |
799 | ||
0b255e92 | 800 | static void piix4_remove(struct pci_dev *dev) |
14a8086d | 801 | { |
ca2061e1 CF |
802 | int port = PIIX4_MAX_ADAPTERS; |
803 | ||
804 | while (--port >= 0) { | |
805 | if (piix4_main_adapters[port]) { | |
806 | piix4_adap_remove(piix4_main_adapters[port]); | |
807 | piix4_main_adapters[port] = NULL; | |
808 | } | |
e154bf6f | 809 | } |
2a2f7404 AA |
810 | |
811 | if (piix4_aux_adapter) { | |
812 | piix4_adap_remove(piix4_aux_adapter); | |
813 | piix4_aux_adapter = NULL; | |
814 | } | |
14a8086d AA |
815 | } |
816 | ||
1da177e4 LT |
817 | static struct pci_driver piix4_driver = { |
818 | .name = "piix4_smbus", | |
819 | .id_table = piix4_ids, | |
820 | .probe = piix4_probe, | |
0b255e92 | 821 | .remove = piix4_remove, |
1da177e4 LT |
822 | }; |
823 | ||
56f21788 | 824 | module_pci_driver(piix4_driver); |
1da177e4 LT |
825 | |
826 | MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " | |
827 | "Philip Edelbrock <phil@netroedge.com>"); | |
828 | MODULE_DESCRIPTION("PIIX4 SMBus driver"); | |
829 | MODULE_LICENSE("GPL"); |