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UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / drivers / i2c / busses / i2c-piix4.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
1da177e4
LT		 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
4 Philip Edelbrock <phil@netroedge.com>
5
1da177e4
LT		 6*/
7
8/*
9 Supports:
10 Intel PIIX4, 440MX
506a8b6c 11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
2a2f7404 12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
032f708b 13 AMD Hudson-2, ML, CZ
24beb83a 14 Hygon CZ
1da177e4
LT		 15 SMSC Victory66
16
2a2f7404
AA		 17 Note: we assume there can only be one device, with one or more
18 SMBus interfaces.
2fee61d2
CF		 19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
20 For devices supporting multiple ports the i2c_adapter should provide
21 an i2c_algorithm to access them.
1da177e4
LT		 22*/
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/stddef.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/i2c.h>
c415b303 32#include <linux/slab.h>
1da177e4 33#include <linux/dmi.h>
54fb4a05 34#include <linux/acpi.h>
21782180 35#include <linux/io.h>
1da177e4
LT		 36
37
1da177e4
LT		 38/* PIIX4 SMBus address offsets */
39#define SMBHSTSTS (0 + piix4_smba)
40#define SMBHSLVSTS (1 + piix4_smba)
41#define SMBHSTCNT (2 + piix4_smba)
42#define SMBHSTCMD (3 + piix4_smba)
43#define SMBHSTADD (4 + piix4_smba)
44#define SMBHSTDAT0 (5 + piix4_smba)
45#define SMBHSTDAT1 (6 + piix4_smba)
46#define SMBBLKDAT (7 + piix4_smba)
47#define SMBSLVCNT (8 + piix4_smba)
48#define SMBSHDWCMD (9 + piix4_smba)
49#define SMBSLVEVT (0xA + piix4_smba)
50#define SMBSLVDAT (0xC + piix4_smba)
51
52/* count for request_region */
f43128c7 53#define SMBIOSIZE 9
1da177e4
LT		 54
55/* PCI Address Constants */
56#define SMBBA 0x090
57#define SMBHSTCFG 0x0D2
58#define SMBSLVC 0x0D3
59#define SMBSHDW1 0x0D4
60#define SMBSHDW2 0x0D5
61#define SMBREV 0x0D6
62
63/* Other settings */
64#define MAX_TIMEOUT 500
65#define ENABLE_INT9 0
66
67/* PIIX4 constants */
68#define PIIX4_QUICK 0x00
69#define PIIX4_BYTE 0x04
70#define PIIX4_BYTE_DATA 0x08
71#define PIIX4_WORD_DATA 0x0C
72#define PIIX4_BLOCK_DATA 0x14
73
ca2061e1
CF		 74/* Multi-port constants */
75#define PIIX4_MAX_ADAPTERS 4
76
2fee61d2
CF		 77/* SB800 constants */
78#define SB800_PIIX4_SMB_IDX 0xcd6
79
88fa2dfb
RRD		 80#define KERNCZ_IMC_IDX 0x3e
81#define KERNCZ_IMC_DATA 0x3f
82
6befa3fd
JD		 83/*
84 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
85 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
86 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
87 */
2fee61d2 88#define SB800_PIIX4_PORT_IDX 0x2c
6befa3fd
JD		 89#define SB800_PIIX4_PORT_IDX_ALT 0x2e
90#define SB800_PIIX4_PORT_IDX_SEL 0x2f
2fee61d2 91#define SB800_PIIX4_PORT_IDX_MASK 0x06
0fe16195
GR		 92#define SB800_PIIX4_PORT_IDX_SHIFT 1
93
c7c06a15 94/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
0fe16195
GR		 95#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
96#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
97#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
2fee61d2 98
1da177e4
LT		 99/* insmod parameters */
100
101/* If force is set to anything different from 0, we forcibly enable the
102 PIIX4. DANGEROUS! */
60507095 103static int force;
1da177e4
LT		 104module_param (force, int, 0);
105MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
106
107/* If force_addr is set to anything different from 0, we forcibly enable
108 the PIIX4 at the given address. VERY DANGEROUS! */
60507095 109static int force_addr;
c78babcc 110module_param_hw(force_addr, int, ioport, 0);
1da177e4
LT		 111MODULE_PARM_DESC(force_addr,
112 "Forcibly enable the PIIX4 at the given address. "
113 "EXTREMELY DANGEROUS!");
114
b1c1759c 115static int srvrworks_csb5_delay;
d6072f84 116static struct pci_driver piix4_driver;
1da177e4 117
0b255e92 118static const struct dmi_system_id piix4_dmi_blacklist[] = {
c2fc54fc
JD		 119 {
120 .ident = "Sapphire AM2RD790",
121 .matches = {
122 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
123 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
124 },
125 },
126 {
127 .ident = "DFI Lanparty UT 790FX",
128 .matches = {
129 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
130 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
131 },
132 },
133 { }
134};
135
136/* The IBM entry is in a separate table because we only check it
137 on Intel-based systems */
0b255e92 138static const struct dmi_system_id piix4_dmi_ibm[] = {
1da177e4
LT		 139 {
140 .ident = "IBM",
141 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
142 },
143 { },
144};
145
6befa3fd
JD		 146/*
147 * SB800 globals
6befa3fd 148 */
6befa3fd 149static u8 piix4_port_sel_sb800;
0fe16195
GR		 150static u8 piix4_port_mask_sb800;
151static u8 piix4_port_shift_sb800;
725d2e3f 152static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
52795f6f 153 " port 0", " port 2", " port 3", " port 4"
725d2e3f 154};
52795f6f 155static const char *piix4_aux_port_name_sb800 = " port 1";
725d2e3f 156
14a8086d
AA		 157struct i2c_piix4_adapdata {
158 unsigned short smba;
2fee61d2
CF		 159
160 /* SB800 */
161 bool sb800_main;
88fa2dfb 162 bool notify_imc;
33f5ccc3 163 u8 port; /* Port number, shifted */
14a8086d
AA		 164};
165
0b255e92
BP		 166static int piix4_setup(struct pci_dev *PIIX4_dev,
167 const struct pci_device_id *id)
1da177e4
LT		 168{
169 unsigned char temp;
14a8086d 170 unsigned short piix4_smba;
1da177e4 171
b1c1759c
DM		 172 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
173 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
174 srvrworks_csb5_delay = 1;
175
c2fc54fc
JD		 176 /* On some motherboards, it was reported that accessing the SMBus
177 caused severe hardware problems */
178 if (dmi_check_system(piix4_dmi_blacklist)) {
179 dev_err(&PIIX4_dev->dev,
180 "Accessing the SMBus on this system is unsafe!\n");
181 return -EPERM;
182 }
183
1da177e4 184 /* Don't access SMBus on IBM systems which get corrupted eeproms */
c2fc54fc 185 if (dmi_check_system(piix4_dmi_ibm) &&
1da177e4 186 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
f9ba6c04 187 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
1da177e4
LT		 188 "may corrupt your serial eeprom! Refusing to load "
189 "module!\n");
190 return -EPERM;
191 }
192
193 /* Determine the address of the SMBus areas */
194 if (force_addr) {
195 piix4_smba = force_addr & 0xfff0;
196 force = 0;
197 } else {
198 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
199 piix4_smba &= 0xfff0;
200 if(piix4_smba == 0) {
fa63cd56 201 dev_err(&PIIX4_dev->dev, "SMBus base address "
1da177e4
LT		 202 "uninitialized - upgrade BIOS or use "
203 "force_addr=0xaddr\n");
204 return -ENODEV;
205 }
206 }
207
54fb4a05 208 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
18669eab 209 return -ENODEV;
54fb4a05 210
d6072f84 211 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
fa63cd56 212 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
1da177e4 213 piix4_smba);
fa63cd56 214 return -EBUSY;
1da177e4
LT		 215 }
216
217 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
218
1da177e4
LT		 219 /* If force_addr is set, we program the new address here. Just to make
220 sure, we disable the PIIX4 first. */
221 if (force_addr) {
222 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
223 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
224 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
225 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
226 "new address %04x!\n", piix4_smba);
227 } else if ((temp & 1) == 0) {
228 if (force) {
229 /* This should never need to be done, but has been
230 * noted that many Dell machines have the SMBus
231 * interface on the PIIX4 disabled!? NOTE: This assumes
232 * I/O space and other allocations WERE done by the
233 * Bios! Don't complain if your hardware does weird
234 * things after enabling this. :') Check for Bios
235 * updates before resorting to this.
236 */
237 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
238 temp | 1);
8117e41e
JP		 239 dev_notice(&PIIX4_dev->dev,
240 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
1da177e4
LT		 241 } else {
242 dev_err(&PIIX4_dev->dev,
66f8a8ff 243 "SMBus Host Controller not enabled!\n");
1da177e4 244 release_region(piix4_smba, SMBIOSIZE);
1da177e4
LT		 245 return -ENODEV;
246 }
247 }
248
54aaa1ca 249 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
66f8a8ff 250 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
1da177e4 251 else if ((temp & 0x0E) == 0)
66f8a8ff 252 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
1da177e4
LT		 253 else
254 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
255 "(or code out of date)!\n");
256
257 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
fa63cd56
JD		 258 dev_info(&PIIX4_dev->dev,
259 "SMBus Host Controller at 0x%x, revision %d\n",
260 piix4_smba, temp);
1da177e4 261
14a8086d 262 return piix4_smba;
1da177e4
LT		 263}
264
0b255e92 265static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
a94dd00f 266 const struct pci_device_id *id, u8 aux)
87e1960e 267{
14a8086d 268 unsigned short piix4_smba;
6befa3fd 269 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
032f708b 270 u8 i2ccfg, i2ccfg_offset = 0x10;
87e1960e 271
3806e94b 272 /* SB800 and later SMBus does not support forcing address */
87e1960e 273 if (force || force_addr) {
3806e94b 274 dev_err(&PIIX4_dev->dev, "SMBus does not support "
87e1960e
SH		 275 "forcing address!\n");
276 return -EINVAL;
277 }
278
279 /* Determine the address of the SMBus areas */
032f708b
SH		 280 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
281 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
282 PIIX4_dev->revision >= 0x41) ||
283 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
bcb29994 284 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
24beb83a
PW		 285 PIIX4_dev->revision >= 0x49) ||
286 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
287 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
032f708b
SH		 288 smb_en = 0x00;
289 else
290 smb_en = (aux) ? 0x28 : 0x2c;
a94dd00f 291
04b6fcab
GR		 292 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) {
293 dev_err(&PIIX4_dev->dev,
294 "SMB base address index region 0x%x already in use.\n",
295 SB800_PIIX4_SMB_IDX);
296 return -EBUSY;
297 }
298
2fee61d2
CF		 299 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
300 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
301 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
302 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
04b6fcab
GR		 303
304 release_region(SB800_PIIX4_SMB_IDX, 2);
87e1960e 305
032f708b
SH		 306 if (!smb_en) {
307 smb_en_status = smba_en_lo & 0x10;
308 piix4_smba = smba_en_hi << 8;
309 if (aux)
310 piix4_smba |= 0x20;
311 } else {
312 smb_en_status = smba_en_lo & 0x01;
313 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
314 }
315
316 if (!smb_en_status) {
87e1960e 317 dev_err(&PIIX4_dev->dev,
66f8a8ff 318 "SMBus Host Controller not enabled!\n");
87e1960e
SH		 319 return -ENODEV;
320 }
321
87e1960e 322 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
18669eab 323 return -ENODEV;
87e1960e
SH		 324
325 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
326 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
327 piix4_smba);
328 return -EBUSY;
329 }
330
a94dd00f
RM		 331 /* Aux SMBus does not support IRQ information */
332 if (aux) {
333 dev_info(&PIIX4_dev->dev,
85fd0fe6
SH		 334 "Auxiliary SMBus Host Controller at 0x%x\n",
335 piix4_smba);
a94dd00f
RM		 336 return piix4_smba;
337 }
338
87e1960e
SH		 339 /* Request the SMBus I2C bus config region */
340 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
341 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
342 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
343 release_region(piix4_smba, SMBIOSIZE);
87e1960e
SH		 344 return -EBUSY;
345 }
346 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
347 release_region(piix4_smba + i2ccfg_offset, 1);
348
349 if (i2ccfg & 1)
66f8a8ff 350 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
87e1960e 351 else
66f8a8ff 352 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
87e1960e
SH		 353
354 dev_info(&PIIX4_dev->dev,
355 "SMBus Host Controller at 0x%x, revision %d\n",
356 piix4_smba, i2ccfg >> 4);
357
6befa3fd 358 /* Find which register is used for port selection */
24beb83a
PW		 359 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
360 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
c7c06a15
AC		 361 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
362 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
363 PIIX4_dev->revision >= 0x1F)) {
0fe16195
GR		 364 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
365 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
366 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
c7c06a15 367 } else {
0fe16195
GR		 368 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
369 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
370 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
0fe16195 371 }
6befa3fd 372 } else {
04b6fcab
GR		 373 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
374 "sb800_piix4_smb")) {
375 release_region(piix4_smba, SMBIOSIZE);
376 return -EBUSY;
377 }
378
6befa3fd
JD		 379 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
380 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
381 piix4_port_sel_sb800 = (port_sel & 0x01) ?
382 SB800_PIIX4_PORT_IDX_ALT :
383 SB800_PIIX4_PORT_IDX;
0fe16195
GR		 384 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
385 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
04b6fcab 386 release_region(SB800_PIIX4_SMB_IDX, 2);
6befa3fd
JD		 387 }
388
389 dev_info(&PIIX4_dev->dev,
390 "Using register 0x%02x for SMBus port selection\n",
391 (unsigned int)piix4_port_sel_sb800);
392
14a8086d 393 return piix4_smba;
87e1960e
SH		 394}
395
0b255e92
BP		 396static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
397 const struct pci_device_id *id,
398 unsigned short base_reg_addr)
2a2f7404
AA		 399{
400 /* Set up auxiliary SMBus controllers found on some
401 * AMD chipsets e.g. SP5100 (SB700 derivative) */
402
403 unsigned short piix4_smba;
404
405 /* Read address of auxiliary SMBus controller */
406 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
407 if ((piix4_smba & 1) == 0) {
408 dev_dbg(&PIIX4_dev->dev,
409 "Auxiliary SMBus controller not enabled\n");
410 return -ENODEV;
411 }
412
413 piix4_smba &= 0xfff0;
414 if (piix4_smba == 0) {
415 dev_dbg(&PIIX4_dev->dev,
416 "Auxiliary SMBus base address uninitialized\n");
417 return -ENODEV;
418 }
419
420 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
421 return -ENODEV;
422
423 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
424 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
425 "already in use!\n", piix4_smba);
426 return -EBUSY;
427 }
428
429 dev_info(&PIIX4_dev->dev,
430 "Auxiliary SMBus Host Controller at 0x%x\n",
431 piix4_smba);
432
433 return piix4_smba;
434}
435
e154bf6f 436static int piix4_transaction(struct i2c_adapter *piix4_adapter)
1da177e4 437{
e154bf6f
AA		 438 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
439 unsigned short piix4_smba = adapdata->smba;
1da177e4
LT		 440 int temp;
441 int result = 0;
442 int timeout = 0;
443
e154bf6f 444 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
1da177e4
LT		 445 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
446 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
447 inb_p(SMBHSTDAT1));
448
449 /* Make sure the SMBus host is ready to start transmitting */
450 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
e154bf6f 451 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
541e6a02 452 "Resetting...\n", temp);
1da177e4
LT		 453 outb_p(temp, SMBHSTSTS);
454 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
e154bf6f 455 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
97140342 456 return -EBUSY;
1da177e4 457 } else {
e154bf6f 458 dev_dbg(&piix4_adapter->dev, "Successful!\n");
1da177e4
LT		 459 }
460 }
461
462 /* start the transaction by setting bit 6 */
463 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
464
465 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
b1c1759c 466 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
0e89b2fe 467 usleep_range(2000, 2100);
b1c1759c 468 else
0e89b2fe 469 usleep_range(250, 500);
b1c1759c 470
b6a31950 471 while ((++timeout < MAX_TIMEOUT) &&
b1c1759c 472 ((temp = inb_p(SMBHSTSTS)) & 0x01))
0e89b2fe 473 usleep_range(250, 500);
1da177e4
LT		 474
475 /* If the SMBus is still busy, we give up */
b6a31950 476 if (timeout == MAX_TIMEOUT) {
e154bf6f 477 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
97140342 478 result = -ETIMEDOUT;
1da177e4
LT		 479 }
480
481 if (temp & 0x10) {
97140342 482 result = -EIO;
e154bf6f 483 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
1da177e4
LT		 484 }
485
486 if (temp & 0x08) {
97140342 487 result = -EIO;
e154bf6f 488 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
1da177e4
LT		 489 "locked until next hard reset. (sorry!)\n");
490 /* Clock stops and slave is stuck in mid-transmission */
491 }
492
493 if (temp & 0x04) {
97140342 494 result = -ENXIO;
e154bf6f 495 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
1da177e4
LT		 496 }
497
498 if (inb_p(SMBHSTSTS) != 0x00)
499 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
500
501 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
e154bf6f 502 dev_err(&piix4_adapter->dev, "Failed reset at end of "
1da177e4
LT		 503 "transaction (%02x)\n", temp);
504 }
e154bf6f 505 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
1da177e4
LT		 506 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
507 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
508 inb_p(SMBHSTDAT1));
509 return result;
510}
511
97140342 512/* Return negative errno on error. */
1da177e4
LT		 513static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
514 unsigned short flags, char read_write,
515 u8 command, int size, union i2c_smbus_data * data)
516{
14a8086d
AA		 517 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
518 unsigned short piix4_smba = adapdata->smba;
1da177e4 519 int i, len;
97140342 520 int status;
1da177e4
LT		 521
522 switch (size) {
1da177e4 523 case I2C_SMBUS_QUICK:
fa63cd56 524 outb_p((addr << 1) | read_write,
1da177e4
LT		 525 SMBHSTADD);
526 size = PIIX4_QUICK;
527 break;
528 case I2C_SMBUS_BYTE:
fa63cd56 529 outb_p((addr << 1) | read_write,
1da177e4
LT		 530 SMBHSTADD);
531 if (read_write == I2C_SMBUS_WRITE)
532 outb_p(command, SMBHSTCMD);
533 size = PIIX4_BYTE;
534 break;
535 case I2C_SMBUS_BYTE_DATA:
fa63cd56 536 outb_p((addr << 1) | read_write,
1da177e4
LT		 537 SMBHSTADD);
538 outb_p(command, SMBHSTCMD);
539 if (read_write == I2C_SMBUS_WRITE)
540 outb_p(data->byte, SMBHSTDAT0);
541 size = PIIX4_BYTE_DATA;
542 break;
543 case I2C_SMBUS_WORD_DATA:
fa63cd56 544 outb_p((addr << 1) | read_write,
1da177e4
LT		 545 SMBHSTADD);
546 outb_p(command, SMBHSTCMD);
547 if (read_write == I2C_SMBUS_WRITE) {
548 outb_p(data->word & 0xff, SMBHSTDAT0);
549 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
550 }
551 size = PIIX4_WORD_DATA;
552 break;
553 case I2C_SMBUS_BLOCK_DATA:
fa63cd56 554 outb_p((addr << 1) | read_write,
1da177e4
LT		 555 SMBHSTADD);
556 outb_p(command, SMBHSTCMD);
557 if (read_write == I2C_SMBUS_WRITE) {
558 len = data->block[0];
fa63cd56
JD		 559 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
560 return -EINVAL;
1da177e4 561 outb_p(len, SMBHSTDAT0);
d7a4c763 562 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
1da177e4
LT		 563 for (i = 1; i <= len; i++)
564 outb_p(data->block[i], SMBBLKDAT);
565 }
566 size = PIIX4_BLOCK_DATA;
567 break;
ac7fc4fb
JD		 568 default:
569 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
570 return -EOPNOTSUPP;
1da177e4
LT		 571 }
572
573 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
574
e154bf6f 575 status = piix4_transaction(adap);
97140342
DB		 576 if (status)
577 return status;
1da177e4
LT		 578
579 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
580 return 0;
581
582
583 switch (size) {
3578a075 584 case PIIX4_BYTE:
1da177e4
LT		 585 case PIIX4_BYTE_DATA:
586 data->byte = inb_p(SMBHSTDAT0);
587 break;
588 case PIIX4_WORD_DATA:
589 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
590 break;
591 case PIIX4_BLOCK_DATA:
592 data->block[0] = inb_p(SMBHSTDAT0);
fa63cd56
JD		 593 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
594 return -EPROTO;
d7a4c763 595 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
1da177e4
LT		 596 for (i = 1; i <= data->block[0]; i++)
597 data->block[i] = inb_p(SMBBLKDAT);
598 break;
599 }
600 return 0;
601}
602
88fa2dfb
RRD		 603static uint8_t piix4_imc_read(uint8_t idx)
604{
605 outb_p(idx, KERNCZ_IMC_IDX);
606 return inb_p(KERNCZ_IMC_DATA);
607}
608
609static void piix4_imc_write(uint8_t idx, uint8_t value)
610{
611 outb_p(idx, KERNCZ_IMC_IDX);
612 outb_p(value, KERNCZ_IMC_DATA);
613}
614
615static int piix4_imc_sleep(void)
616{
617 int timeout = MAX_TIMEOUT;
618
619 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
620 return -EBUSY;
621
622 /* clear response register */
623 piix4_imc_write(0x82, 0x00);
624 /* request ownership flag */
625 piix4_imc_write(0x83, 0xB4);
626 /* kick off IMC Mailbox command 96 */
627 piix4_imc_write(0x80, 0x96);
628
629 while (timeout--) {
630 if (piix4_imc_read(0x82) == 0xfa) {
631 release_region(KERNCZ_IMC_IDX, 2);
632 return 0;
633 }
634 usleep_range(1000, 2000);
635 }
636
637 release_region(KERNCZ_IMC_IDX, 2);
638 return -ETIMEDOUT;
639}
640
641static void piix4_imc_wakeup(void)
642{
643 int timeout = MAX_TIMEOUT;
644
645 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
646 return;
647
648 /* clear response register */
649 piix4_imc_write(0x82, 0x00);
650 /* release ownership flag */
651 piix4_imc_write(0x83, 0xB5);
652 /* kick off IMC Mailbox command 96 */
653 piix4_imc_write(0x80, 0x96);
654
655 while (timeout--) {
656 if (piix4_imc_read(0x82) == 0xfa)
657 break;
658 usleep_range(1000, 2000);
659 }
660
661 release_region(KERNCZ_IMC_IDX, 2);
662}
663
2fee61d2
CF		 664/*
665 * Handles access to multiple SMBus ports on the SB800.
666 * The port is selected by bits 2:1 of the smb_en register (0x2c).
667 * Returns negative errno on error.
668 *
669 * Note: The selected port must be returned to the initial selection to avoid
670 * problems on certain systems.
671 */
672static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
673 unsigned short flags, char read_write,
674 u8 command, int size, union i2c_smbus_data *data)
675{
676 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
701dc207
RRD		 677 unsigned short piix4_smba = adapdata->smba;
678 int retries = MAX_TIMEOUT;
679 int smbslvcnt;
2fee61d2
CF		 680 u8 smba_en_lo;
681 u8 port;
682 int retval;
683
04b6fcab
GR		 684 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb"))
685 return -EBUSY;
bbb27fc3 686
701dc207
RRD		 687 /* Request the SMBUS semaphore, avoid conflicts with the IMC */
688 smbslvcnt = inb_p(SMBSLVCNT);
689 do {
690 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
691
692 /* Check the semaphore status */
693 smbslvcnt = inb_p(SMBSLVCNT);
694 if (smbslvcnt & 0x10)
695 break;
696
697 usleep_range(1000, 2000);
698 } while (--retries);
699 /* SMBus is still owned by the IMC, we give up */
bbb27fc3 700 if (!retries) {
04b6fcab
GR		 701 retval = -EBUSY;
702 goto release;
bbb27fc3 703 }
2fee61d2 704
88fa2dfb
RRD		 705 /*
706 * Notify the IMC (Integrated Micro Controller) if required.
707 * Among other responsibilities, the IMC is in charge of monitoring
708 * the System fans and temperature sensors, and act accordingly.
709 * All this is done through SMBus and can/will collide
710 * with our transactions if they are long (BLOCK_DATA).
711 * Therefore we need to request the ownership flag during those
712 * transactions.
713 */
714 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
715 int ret;
716
717 ret = piix4_imc_sleep();
718 switch (ret) {
719 case -EBUSY:
720 dev_warn(&adap->dev,
721 "IMC base address index region 0x%x already in use.\n",
722 KERNCZ_IMC_IDX);
723 break;
724 case -ETIMEDOUT:
725 dev_warn(&adap->dev,
726 "Failed to communicate with the IMC.\n");
727 break;
728 default:
729 break;
730 }
731
732 /* If IMC communication fails do not retry */
733 if (ret) {
734 dev_warn(&adap->dev,
735 "Continuing without IMC notification.\n");
736 adapdata->notify_imc = false;
737 }
738 }
739
6befa3fd 740 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
2fee61d2
CF		 741 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
742
743 port = adapdata->port;
0fe16195
GR		 744 if ((smba_en_lo & piix4_port_mask_sb800) != port)
745 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
2fee61d2
CF		 746 SB800_PIIX4_SMB_IDX + 1);
747
748 retval = piix4_access(adap, addr, flags, read_write,
749 command, size, data);
750
751 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
752
701dc207
RRD		 753 /* Release the semaphore */
754 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
755
88fa2dfb
RRD		 756 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
757 piix4_imc_wakeup();
758
04b6fcab
GR		 759release:
760 release_region(SB800_PIIX4_SMB_IDX, 2);
2fee61d2
CF		 761 return retval;
762}
763
1da177e4
LT		 764static u32 piix4_func(struct i2c_adapter *adapter)
765{
766 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
767 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
768 I2C_FUNC_SMBUS_BLOCK_DATA;
769}
770
8f9082c5 771static const struct i2c_algorithm smbus_algorithm = {
1da177e4
LT		 772 .smbus_xfer = piix4_access,
773 .functionality = piix4_func,
774};
775
2fee61d2
CF		 776static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
777 .smbus_xfer = piix4_access_sb800,
778 .functionality = piix4_func,
779};
780
392debf1 781static const struct pci_device_id piix4_ids[] = {
9b7389c0
JD		 782 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
783 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
784 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
785 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
786 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
3806e94b 789 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
bcb29994 790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
24beb83a 791 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
9b7389c0
JD		 792 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
793 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
794 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
795 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
796 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
797 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
798 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
799 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
506a8b6c
FL		 800 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
801 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
1da177e4
LT		 802 { 0, }
803};
804
805MODULE_DEVICE_TABLE (pci, piix4_ids);
806
ca2061e1 807static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
2a2f7404 808static struct i2c_adapter *piix4_aux_adapter;
e154bf6f 809
0b255e92 810static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
88fa2dfb 811 bool sb800_main, u8 port, bool notify_imc,
725d2e3f 812 const char *name, struct i2c_adapter **padap)
e154bf6f
AA		 813{
814 struct i2c_adapter *adap;
815 struct i2c_piix4_adapdata *adapdata;
816 int retval;
817
818 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
819 if (adap == NULL) {
820 release_region(smba, SMBIOSIZE);
821 return -ENOMEM;
822 }
823
824 adap->owner = THIS_MODULE;
825 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
83c60158
JD		 826 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
827 : &smbus_algorithm;
e154bf6f
AA		 828
829 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
830 if (adapdata == NULL) {
831 kfree(adap);
832 release_region(smba, SMBIOSIZE);
833 return -ENOMEM;
834 }
835
836 adapdata->smba = smba;
83c60158 837 adapdata->sb800_main = sb800_main;
0fe16195 838 adapdata->port = port << piix4_port_shift_sb800;
88fa2dfb 839 adapdata->notify_imc = notify_imc;
e154bf6f
AA		 840
841 /* set up the sysfs linkage to our parent device */
842 adap->dev.parent = &dev->dev;
843
844 snprintf(adap->name, sizeof(adap->name),
52795f6f 845 "SMBus PIIX4 adapter%s at %04x", name, smba);
e154bf6f
AA		 846
847 i2c_set_adapdata(adap, adapdata);
848
849 retval = i2c_add_adapter(adap);
850 if (retval) {
e154bf6f
AA		 851 kfree(adapdata);
852 kfree(adap);
853 release_region(smba, SMBIOSIZE);
854 return retval;
855 }
856
857 *padap = adap;
858 return 0;
859}
860
88fa2dfb
RRD		 861static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
862 bool notify_imc)
2fee61d2 863{
2fee61d2
CF		 864 struct i2c_piix4_adapdata *adapdata;
865 int port;
866 int retval;
867
2fee61d2 868 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) {
88fa2dfb 869 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
725d2e3f 870 piix4_main_port_names_sb800[port],
2fee61d2
CF		 871 &piix4_main_adapters[port]);
872 if (retval < 0)
873 goto error;
2fee61d2
CF		 874 }
875
876 return retval;
877
878error:
879 dev_err(&dev->dev,
880 "Error setting up SB800 adapters. Unregistering!\n");
881 while (--port >= 0) {
882 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
883 if (adapdata->smba) {
884 i2c_del_adapter(piix4_main_adapters[port]);
885 kfree(adapdata);
886 kfree(piix4_main_adapters[port]);
887 piix4_main_adapters[port] = NULL;
888 }
889 }
890
2fee61d2
CF		 891 return retval;
892}
893
0b255e92 894static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
1da177e4
LT		 895{
896 int retval;
52795f6f 897 bool is_sb800 = false;
1da177e4 898
76b3e28f
CC		 899 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
900 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
901 dev->revision >= 0x40) ||
24beb83a
PW		 902 dev->vendor == PCI_VENDOR_ID_AMD ||
903 dev->vendor == PCI_VENDOR_ID_HYGON) {
88fa2dfb 904 bool notify_imc = false;
52795f6f
JD		 905 is_sb800 = true;
906
24beb83a
PW		 907 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
908 dev->vendor == PCI_VENDOR_ID_HYGON) &&
88fa2dfb
RRD		 909 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
910 u8 imc;
911
912 /*
913 * Detect if IMC is active or not, this method is
914 * described on coreboot's AMD IMC notes
915 */
916 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
917 0x40, &imc);
918 if (imc & 0x80)
919 notify_imc = true;
920 }
921
87e1960e 922 /* base address location etc changed in SB800 */
a94dd00f 923 retval = piix4_setup_sb800(dev, id, 0);
04b6fcab 924 if (retval < 0)
2fee61d2 925 return retval;
87e1960e 926
2fee61d2
CF		 927 /*
928 * Try to register multiplexed main SMBus adapter,
929 * give up if we can't
930 */
88fa2dfb 931 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
04b6fcab 932 if (retval < 0)
2fee61d2 933 return retval;
2fee61d2
CF		 934 } else {
935 retval = piix4_setup(dev, id);
936 if (retval < 0)
937 return retval;
1da177e4 938
2fee61d2 939 /* Try to register main SMBus adapter, give up if we can't */
88fa2dfb 940 retval = piix4_add_adapter(dev, retval, false, 0, false, "",
2fee61d2
CF		 941 &piix4_main_adapters[0]);
942 if (retval < 0)
943 return retval;
944 }
2a2f7404
AA		 945
946 /* Check for auxiliary SMBus on some AMD chipsets */
a94dd00f
RM		 947 retval = -ENODEV;
948
2a2f7404 949 if (dev->vendor == PCI_VENDOR_ID_ATI &&
a94dd00f
RM		 950 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
951 if (dev->revision < 0x40) {
952 retval = piix4_setup_aux(dev, id, 0x58);
953 } else {
954 /* SB800 added aux bus too */
955 retval = piix4_setup_sb800(dev, id, 1);
2a2f7404
AA		 956 }
957 }
958
a94dd00f
RM		 959 if (dev->vendor == PCI_VENDOR_ID_AMD &&
960 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
961 retval = piix4_setup_sb800(dev, id, 1);
962 }
963
964 if (retval > 0) {
965 /* Try to add the aux adapter if it exists,
966 * piix4_add_adapter will clean up if this fails */
88fa2dfb 967 piix4_add_adapter(dev, retval, false, 0, false,
52795f6f 968 is_sb800 ? piix4_aux_port_name_sb800 : "",
725d2e3f 969 &piix4_aux_adapter);
a94dd00f
RM		 970 }
971
2a2f7404 972 return 0;
1da177e4
LT		 973}
974
0b255e92 975static void piix4_adap_remove(struct i2c_adapter *adap)
1da177e4 976{
14a8086d
AA		 977 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
978
979 if (adapdata->smba) {
980 i2c_del_adapter(adap);
04b6fcab 981 if (adapdata->port == (0 << piix4_port_shift_sb800))
2fee61d2 982 release_region(adapdata->smba, SMBIOSIZE);
e154bf6f
AA		 983 kfree(adapdata);
984 kfree(adap);
1da177e4
LT		 985 }
986}
987
0b255e92 988static void piix4_remove(struct pci_dev *dev)
14a8086d 989{
ca2061e1
CF		 990 int port = PIIX4_MAX_ADAPTERS;
991
992 while (--port >= 0) {
993 if (piix4_main_adapters[port]) {
994 piix4_adap_remove(piix4_main_adapters[port]);
995 piix4_main_adapters[port] = NULL;
996 }
e154bf6f 997 }
2a2f7404
AA		 998
999 if (piix4_aux_adapter) {
1000 piix4_adap_remove(piix4_aux_adapter);
1001 piix4_aux_adapter = NULL;
1002 }
14a8086d
AA		 1003}
1004
1da177e4
LT		 1005static struct pci_driver piix4_driver = {
1006 .name = "piix4_smbus",
1007 .id_table = piix4_ids,
1008 .probe = piix4_probe,
0b255e92 1009 .remove = piix4_remove,
1da177e4
LT		 1010};
1011
56f21788 1012module_pci_driver(piix4_driver);
1da177e4
LT		 1013
1014MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
1015 "Philip Edelbrock <phil@netroedge.com>");
1016MODULE_DESCRIPTION("PIIX4 SMBus driver");
1017MODULE_LICENSE("GPL");
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