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41561f28 VW |
1 | /* |
2 | * Provides I2C support for Philips PNX010x/PNX4008 boards. | |
3 | * | |
4 | * Authors: Dennis Kovalev <dkovalev@ru.mvista.com> | |
5 | * Vitaly Wool <vwool@ru.mvista.com> | |
6 | * | |
7 | * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/completion.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/i2c-pnx.h> | |
a09e64fb | 22 | #include <mach/hardware.h> |
41561f28 VW |
23 | #include <asm/irq.h> |
24 | #include <asm/uaccess.h> | |
25 | ||
26 | #define I2C_PNX_TIMEOUT 10 /* msec */ | |
27 | #define I2C_PNX_SPEED_KHZ 100 | |
28 | #define I2C_PNX_REGION_SIZE 0x100 | |
29 | #define PNX_DEFAULT_FREQ 13 /* MHz */ | |
30 | ||
31 | static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) | |
32 | { | |
33 | while (timeout > 0 && | |
34 | (ioread32(I2C_REG_STS(data)) & mstatus_active)) { | |
35 | mdelay(1); | |
36 | timeout--; | |
37 | } | |
38 | return (timeout <= 0); | |
39 | } | |
40 | ||
41 | static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data) | |
42 | { | |
43 | while (timeout > 0 && | |
44 | (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { | |
45 | mdelay(1); | |
46 | timeout--; | |
47 | } | |
48 | return (timeout <= 0); | |
49 | } | |
50 | ||
51 | static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap) | |
52 | { | |
53 | struct i2c_pnx_algo_data *data = adap->algo_data; | |
54 | struct timer_list *timer = &data->mif.timer; | |
55 | int expires = I2C_PNX_TIMEOUT / (1000 / HZ); | |
56 | ||
57 | del_timer_sync(timer); | |
58 | ||
59 | dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n", | |
60 | jiffies, expires); | |
61 | ||
62 | timer->expires = jiffies + expires; | |
63 | timer->data = (unsigned long)adap; | |
64 | ||
65 | add_timer(timer); | |
66 | } | |
67 | ||
68 | /** | |
69 | * i2c_pnx_start - start a device | |
70 | * @slave_addr: slave address | |
71 | * @adap: pointer to adapter structure | |
72 | * | |
73 | * Generate a START signal in the desired mode. | |
74 | */ | |
75 | static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap) | |
76 | { | |
77 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
78 | ||
08882d20 | 79 | dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__, |
41561f28 VW |
80 | slave_addr, alg_data->mif.mode); |
81 | ||
82 | /* Check for 7 bit slave addresses only */ | |
83 | if (slave_addr & ~0x7f) { | |
84 | dev_err(&adap->dev, "%s: Invalid slave address %x. " | |
85 | "Only 7-bit addresses are supported\n", | |
86 | adap->name, slave_addr); | |
87 | return -EINVAL; | |
88 | } | |
89 | ||
90 | /* First, make sure bus is idle */ | |
91 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { | |
92 | /* Somebody else is monopolizing the bus */ | |
93 | dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, " | |
94 | "cntrl = %x, stat = %x\n", | |
95 | adap->name, slave_addr, | |
96 | ioread32(I2C_REG_CTL(alg_data)), | |
97 | ioread32(I2C_REG_STS(alg_data))); | |
98 | return -EBUSY; | |
99 | } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { | |
100 | /* Sorry, we lost the bus */ | |
101 | dev_err(&adap->dev, "%s: Arbitration failure. " | |
102 | "Slave addr = %02x\n", adap->name, slave_addr); | |
103 | return -EIO; | |
104 | } | |
105 | ||
106 | /* | |
107 | * OK, I2C is enabled and we have the bus. | |
108 | * Clear the current TDI and AFI status flags. | |
109 | */ | |
110 | iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, | |
111 | I2C_REG_STS(alg_data)); | |
112 | ||
08882d20 | 113 | dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__, |
41561f28 VW |
114 | (slave_addr << 1) | start_bit | alg_data->mif.mode); |
115 | ||
116 | /* Write the slave address, START bit and R/W bit */ | |
117 | iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, | |
118 | I2C_REG_TX(alg_data)); | |
119 | ||
08882d20 | 120 | dev_dbg(&adap->dev, "%s(): exit\n", __func__); |
41561f28 VW |
121 | |
122 | return 0; | |
123 | } | |
124 | ||
125 | /** | |
126 | * i2c_pnx_stop - stop a device | |
127 | * @adap: pointer to I2C adapter structure | |
128 | * | |
129 | * Generate a STOP signal to terminate the master transaction. | |
130 | */ | |
131 | static void i2c_pnx_stop(struct i2c_adapter *adap) | |
132 | { | |
133 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
134 | /* Only 1 msec max timeout due to interrupt context */ | |
135 | long timeout = 1000; | |
136 | ||
137 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | |
08882d20 | 138 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
139 | |
140 | /* Write a STOP bit to TX FIFO */ | |
141 | iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data)); | |
142 | ||
143 | /* Wait until the STOP is seen. */ | |
144 | while (timeout > 0 && | |
145 | (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { | |
146 | /* may be called from interrupt context */ | |
147 | udelay(1); | |
148 | timeout--; | |
149 | } | |
150 | ||
151 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | |
08882d20 | 152 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
153 | } |
154 | ||
155 | /** | |
156 | * i2c_pnx_master_xmit - transmit data to slave | |
157 | * @adap: pointer to I2C adapter structure | |
158 | * | |
159 | * Sends one byte of data to the slave | |
160 | */ | |
161 | static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | |
162 | { | |
163 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
164 | u32 val; | |
165 | ||
166 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | |
08882d20 | 167 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
168 | |
169 | if (alg_data->mif.len > 0) { | |
170 | /* We still have something to talk about... */ | |
171 | val = *alg_data->mif.buf++; | |
172 | ||
173 | if (alg_data->mif.len == 1) { | |
174 | val |= stop_bit; | |
175 | if (!alg_data->last) | |
176 | val |= start_bit; | |
177 | } | |
178 | ||
179 | alg_data->mif.len--; | |
180 | iowrite32(val, I2C_REG_TX(alg_data)); | |
181 | ||
08882d20 | 182 | dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__, |
41561f28 VW |
183 | val, alg_data->mif.len + 1); |
184 | ||
185 | if (alg_data->mif.len == 0) { | |
186 | if (alg_data->last) { | |
187 | /* Wait until the STOP is seen. */ | |
188 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
189 | dev_err(&adap->dev, "The bus is still " | |
190 | "active after timeout\n"); | |
191 | } | |
192 | /* Disable master interrupts */ | |
193 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
194 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
195 | I2C_REG_CTL(alg_data)); | |
196 | ||
197 | del_timer_sync(&alg_data->mif.timer); | |
198 | ||
199 | dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n", | |
08882d20 | 200 | __func__); |
41561f28 VW |
201 | |
202 | complete(&alg_data->mif.complete); | |
203 | } | |
204 | } else if (alg_data->mif.len == 0) { | |
205 | /* zero-sized transfer */ | |
206 | i2c_pnx_stop(adap); | |
207 | ||
208 | /* Disable master interrupts. */ | |
209 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
210 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
211 | I2C_REG_CTL(alg_data)); | |
212 | ||
213 | /* Stop timer. */ | |
214 | del_timer_sync(&alg_data->mif.timer); | |
215 | dev_dbg(&adap->dev, "%s(): Waking up xfer routine after " | |
08882d20 | 216 | "zero-xfer.\n", __func__); |
41561f28 VW |
217 | |
218 | complete(&alg_data->mif.complete); | |
219 | } | |
220 | ||
221 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | |
08882d20 | 222 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | /** | |
228 | * i2c_pnx_master_rcv - receive data from slave | |
229 | * @adap: pointer to I2C adapter structure | |
230 | * | |
231 | * Reads one byte data from the slave | |
232 | */ | |
233 | static int i2c_pnx_master_rcv(struct i2c_adapter *adap) | |
234 | { | |
235 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
236 | unsigned int val = 0; | |
237 | u32 ctl = 0; | |
238 | ||
239 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | |
08882d20 | 240 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
241 | |
242 | /* Check, whether there is already data, | |
243 | * or we didn't 'ask' for it yet. | |
244 | */ | |
245 | if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { | |
246 | dev_dbg(&adap->dev, "%s(): Write dummy data to fill " | |
08882d20 | 247 | "Rx-fifo...\n", __func__); |
41561f28 VW |
248 | |
249 | if (alg_data->mif.len == 1) { | |
250 | /* Last byte, do not acknowledge next rcv. */ | |
251 | val |= stop_bit; | |
252 | if (!alg_data->last) | |
253 | val |= start_bit; | |
254 | ||
255 | /* | |
256 | * Enable interrupt RFDAIE (data in Rx fifo), | |
257 | * and disable DRMIE (need data for Tx) | |
258 | */ | |
259 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
260 | ctl |= mcntrl_rffie | mcntrl_daie; | |
261 | ctl &= ~mcntrl_drmie; | |
262 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
263 | } | |
264 | ||
265 | /* | |
266 | * Now we'll 'ask' for data: | |
267 | * For each byte we want to receive, we must | |
268 | * write a (dummy) byte to the Tx-FIFO. | |
269 | */ | |
270 | iowrite32(val, I2C_REG_TX(alg_data)); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | /* Handle data. */ | |
276 | if (alg_data->mif.len > 0) { | |
277 | val = ioread32(I2C_REG_RX(alg_data)); | |
278 | *alg_data->mif.buf++ = (u8) (val & 0xff); | |
08882d20 | 279 | dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val, |
41561f28 VW |
280 | alg_data->mif.len); |
281 | ||
282 | alg_data->mif.len--; | |
283 | if (alg_data->mif.len == 0) { | |
284 | if (alg_data->last) | |
285 | /* Wait until the STOP is seen. */ | |
286 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
287 | dev_err(&adap->dev, "The bus is still " | |
288 | "active after timeout\n"); | |
289 | ||
290 | /* Disable master interrupts */ | |
291 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
292 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
293 | mcntrl_drmie | mcntrl_daie); | |
294 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
295 | ||
296 | /* Kill timer. */ | |
297 | del_timer_sync(&alg_data->mif.timer); | |
298 | complete(&alg_data->mif.complete); | |
299 | } | |
300 | } | |
301 | ||
302 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | |
08882d20 | 303 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
6c566fb7 | 308 | static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) |
41561f28 VW |
309 | { |
310 | u32 stat, ctl; | |
311 | struct i2c_adapter *adap = dev_id; | |
312 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
313 | ||
314 | dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n", | |
08882d20 | 315 | __func__, |
41561f28 VW |
316 | ioread32(I2C_REG_STS(alg_data)), |
317 | ioread32(I2C_REG_CTL(alg_data)), | |
318 | alg_data->mif.mode); | |
319 | stat = ioread32(I2C_REG_STS(alg_data)); | |
320 | ||
321 | /* let's see what kind of event this is */ | |
322 | if (stat & mstatus_afi) { | |
323 | /* We lost arbitration in the midst of a transfer */ | |
324 | alg_data->mif.ret = -EIO; | |
325 | ||
326 | /* Disable master interrupts. */ | |
327 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
328 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
329 | mcntrl_drmie); | |
330 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
331 | ||
332 | /* Stop timer, to prevent timeout. */ | |
333 | del_timer_sync(&alg_data->mif.timer); | |
334 | complete(&alg_data->mif.complete); | |
335 | } else if (stat & mstatus_nai) { | |
336 | /* Slave did not acknowledge, generate a STOP */ | |
337 | dev_dbg(&adap->dev, "%s(): " | |
338 | "Slave did not acknowledge, generating a STOP.\n", | |
08882d20 | 339 | __func__); |
41561f28 VW |
340 | i2c_pnx_stop(adap); |
341 | ||
342 | /* Disable master interrupts. */ | |
343 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
344 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
345 | mcntrl_drmie); | |
346 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
347 | ||
348 | /* Our return value. */ | |
349 | alg_data->mif.ret = -EIO; | |
350 | ||
351 | /* Stop timer, to prevent timeout. */ | |
352 | del_timer_sync(&alg_data->mif.timer); | |
353 | complete(&alg_data->mif.complete); | |
354 | } else { | |
355 | /* | |
356 | * Two options: | |
357 | * - Master Tx needs data. | |
358 | * - There is data in the Rx-fifo | |
359 | * The latter is only the case if we have requested for data, | |
360 | * via a dummy write. (See 'i2c_pnx_master_rcv'.) | |
361 | * We therefore check, as a sanity check, whether that interrupt | |
362 | * has been enabled. | |
363 | */ | |
364 | if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { | |
365 | if (alg_data->mif.mode == I2C_SMBUS_WRITE) { | |
366 | i2c_pnx_master_xmit(adap); | |
367 | } else if (alg_data->mif.mode == I2C_SMBUS_READ) { | |
368 | i2c_pnx_master_rcv(adap); | |
369 | } | |
370 | } | |
371 | } | |
372 | ||
373 | /* Clear TDI and AFI bits */ | |
374 | stat = ioread32(I2C_REG_STS(alg_data)); | |
375 | iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); | |
376 | ||
377 | dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n", | |
08882d20 | 378 | __func__, ioread32(I2C_REG_STS(alg_data)), |
41561f28 VW |
379 | ioread32(I2C_REG_CTL(alg_data))); |
380 | ||
381 | return IRQ_HANDLED; | |
382 | } | |
383 | ||
384 | static void i2c_pnx_timeout(unsigned long data) | |
385 | { | |
386 | struct i2c_adapter *adap = (struct i2c_adapter *)data; | |
387 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
388 | u32 ctl; | |
389 | ||
390 | dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. " | |
391 | "Resetting master...\n", | |
392 | ioread32(I2C_REG_STS(alg_data)), | |
393 | ioread32(I2C_REG_CTL(alg_data))); | |
394 | ||
395 | /* Reset master and disable interrupts */ | |
396 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
397 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie); | |
398 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
399 | ||
400 | ctl |= mcntrl_reset; | |
401 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
402 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
403 | alg_data->mif.ret = -EIO; | |
404 | complete(&alg_data->mif.complete); | |
405 | } | |
406 | ||
407 | static inline void bus_reset_if_active(struct i2c_adapter *adap) | |
408 | { | |
409 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
410 | u32 stat; | |
411 | ||
412 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { | |
413 | dev_err(&adap->dev, | |
414 | "%s: Bus is still active after xfer. Reset it...\n", | |
415 | adap->name); | |
416 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
417 | I2C_REG_CTL(alg_data)); | |
418 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
419 | } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) { | |
420 | /* If there is data in the fifo's after transfer, | |
421 | * flush fifo's by reset. | |
422 | */ | |
423 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
424 | I2C_REG_CTL(alg_data)); | |
425 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
426 | } else if (stat & mstatus_nai) { | |
427 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
428 | I2C_REG_CTL(alg_data)); | |
429 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
430 | } | |
431 | } | |
432 | ||
433 | /** | |
434 | * i2c_pnx_xfer - generic transfer entry point | |
435 | * @adap: pointer to I2C adapter structure | |
436 | * @msgs: array of messages | |
437 | * @num: number of messages | |
438 | * | |
439 | * Initiates the transfer | |
440 | */ | |
441 | static int | |
442 | i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
443 | { | |
444 | struct i2c_msg *pmsg; | |
445 | int rc = 0, completed = 0, i; | |
446 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
447 | u32 stat = ioread32(I2C_REG_STS(alg_data)); | |
448 | ||
449 | dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n", | |
08882d20 | 450 | __func__, num, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
451 | |
452 | bus_reset_if_active(adap); | |
453 | ||
454 | /* Process transactions in a loop. */ | |
455 | for (i = 0; rc >= 0 && i < num; i++) { | |
456 | u8 addr; | |
457 | ||
458 | pmsg = &msgs[i]; | |
459 | addr = pmsg->addr; | |
460 | ||
461 | if (pmsg->flags & I2C_M_TEN) { | |
462 | dev_err(&adap->dev, | |
463 | "%s: 10 bits addr not supported!\n", | |
464 | adap->name); | |
465 | rc = -EINVAL; | |
466 | break; | |
467 | } | |
468 | ||
469 | alg_data->mif.buf = pmsg->buf; | |
470 | alg_data->mif.len = pmsg->len; | |
471 | alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ? | |
472 | I2C_SMBUS_READ : I2C_SMBUS_WRITE; | |
473 | alg_data->mif.ret = 0; | |
474 | alg_data->last = (i == num - 1); | |
475 | ||
08882d20 | 476 | dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__, |
41561f28 VW |
477 | alg_data->mif.mode, |
478 | alg_data->mif.len); | |
479 | ||
480 | i2c_pnx_arm_timer(adap); | |
481 | ||
482 | /* initialize the completion var */ | |
483 | init_completion(&alg_data->mif.complete); | |
484 | ||
485 | /* Enable master interrupt */ | |
486 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie | | |
487 | mcntrl_naie | mcntrl_drmie, | |
488 | I2C_REG_CTL(alg_data)); | |
489 | ||
490 | /* Put start-code and slave-address on the bus. */ | |
491 | rc = i2c_pnx_start(addr, adap); | |
492 | if (rc < 0) | |
493 | break; | |
494 | ||
495 | /* Wait for completion */ | |
496 | wait_for_completion(&alg_data->mif.complete); | |
497 | ||
498 | if (!(rc = alg_data->mif.ret)) | |
499 | completed++; | |
500 | dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n", | |
08882d20 | 501 | __func__, rc); |
41561f28 VW |
502 | |
503 | /* Clear TDI and AFI bits in case they are set. */ | |
504 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { | |
505 | dev_dbg(&adap->dev, | |
506 | "%s: TDI still set... clearing now.\n", | |
507 | adap->name); | |
508 | iowrite32(stat, I2C_REG_STS(alg_data)); | |
509 | } | |
510 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { | |
511 | dev_dbg(&adap->dev, | |
512 | "%s: AFI still set... clearing now.\n", | |
513 | adap->name); | |
514 | iowrite32(stat, I2C_REG_STS(alg_data)); | |
515 | } | |
516 | } | |
517 | ||
518 | bus_reset_if_active(adap); | |
519 | ||
520 | /* Cleanup to be sure... */ | |
521 | alg_data->mif.buf = NULL; | |
522 | alg_data->mif.len = 0; | |
523 | ||
524 | dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n", | |
08882d20 | 525 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
526 | |
527 | if (completed != num) | |
528 | return ((rc < 0) ? rc : -EREMOTEIO); | |
529 | ||
530 | return num; | |
531 | } | |
532 | ||
533 | static u32 i2c_pnx_func(struct i2c_adapter *adapter) | |
534 | { | |
535 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
536 | } | |
537 | ||
538 | static struct i2c_algorithm pnx_algorithm = { | |
539 | .master_xfer = i2c_pnx_xfer, | |
540 | .functionality = i2c_pnx_func, | |
541 | }; | |
542 | ||
543 | static int i2c_pnx_controller_suspend(struct platform_device *pdev, | |
544 | pm_message_t state) | |
545 | { | |
546 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | |
547 | return i2c_pnx->suspend(pdev, state); | |
548 | } | |
549 | ||
550 | static int i2c_pnx_controller_resume(struct platform_device *pdev) | |
551 | { | |
552 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | |
553 | return i2c_pnx->resume(pdev); | |
554 | } | |
555 | ||
556 | static int __devinit i2c_pnx_probe(struct platform_device *pdev) | |
557 | { | |
558 | unsigned long tmp; | |
559 | int ret = 0; | |
560 | struct i2c_pnx_algo_data *alg_data; | |
561 | int freq_mhz; | |
562 | struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; | |
563 | ||
564 | if (!i2c_pnx || !i2c_pnx->adapter) { | |
565 | dev_err(&pdev->dev, "%s: no platform data supplied\n", | |
08882d20 | 566 | __func__); |
41561f28 VW |
567 | ret = -EINVAL; |
568 | goto out; | |
569 | } | |
570 | ||
571 | platform_set_drvdata(pdev, i2c_pnx); | |
572 | ||
573 | if (i2c_pnx->calculate_input_freq) | |
574 | freq_mhz = i2c_pnx->calculate_input_freq(pdev); | |
575 | else { | |
576 | freq_mhz = PNX_DEFAULT_FREQ; | |
577 | dev_info(&pdev->dev, "Setting bus frequency to default value: " | |
898eb71c | 578 | "%d MHz\n", freq_mhz); |
41561f28 VW |
579 | } |
580 | ||
581 | i2c_pnx->adapter->algo = &pnx_algorithm; | |
582 | ||
583 | alg_data = i2c_pnx->adapter->algo_data; | |
584 | init_timer(&alg_data->mif.timer); | |
585 | alg_data->mif.timer.function = i2c_pnx_timeout; | |
586 | alg_data->mif.timer.data = (unsigned long)i2c_pnx->adapter; | |
587 | ||
588 | /* Register I/O resource */ | |
589 | if (!request_region(alg_data->base, I2C_PNX_REGION_SIZE, pdev->name)) { | |
590 | dev_err(&pdev->dev, | |
591 | "I/O region 0x%08x for I2C already in use.\n", | |
592 | alg_data->base); | |
593 | ret = -ENODEV; | |
594 | goto out_drvdata; | |
595 | } | |
596 | ||
597 | if (!(alg_data->ioaddr = | |
598 | (u32)ioremap(alg_data->base, I2C_PNX_REGION_SIZE))) { | |
599 | dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); | |
600 | ret = -ENOMEM; | |
601 | goto out_release; | |
602 | } | |
603 | ||
604 | i2c_pnx->set_clock_run(pdev); | |
605 | ||
606 | /* | |
607 | * Clock Divisor High This value is the number of system clocks | |
608 | * the serial clock (SCL) will be high. | |
609 | * For example, if the system clock period is 50 ns and the maximum | |
610 | * desired serial period is 10000 ns (100 kHz), then CLKHI would be | |
611 | * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value | |
612 | * programmed into CLKHI will vary from this slightly due to | |
613 | * variations in the output pad's rise and fall times as well as | |
614 | * the deglitching filter length. | |
615 | */ | |
616 | ||
617 | tmp = ((freq_mhz * 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; | |
618 | iowrite32(tmp, I2C_REG_CKH(alg_data)); | |
619 | iowrite32(tmp, I2C_REG_CKL(alg_data)); | |
620 | ||
621 | iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); | |
622 | if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { | |
623 | ret = -ENODEV; | |
624 | goto out_unmap; | |
625 | } | |
626 | init_completion(&alg_data->mif.complete); | |
627 | ||
628 | ret = request_irq(alg_data->irq, i2c_pnx_interrupt, | |
629 | 0, pdev->name, i2c_pnx->adapter); | |
630 | if (ret) | |
631 | goto out_clock; | |
632 | ||
633 | /* Register this adapter with the I2C subsystem */ | |
634 | i2c_pnx->adapter->dev.parent = &pdev->dev; | |
635 | ret = i2c_add_adapter(i2c_pnx->adapter); | |
636 | if (ret < 0) { | |
637 | dev_err(&pdev->dev, "I2C: Failed to add bus\n"); | |
638 | goto out_irq; | |
639 | } | |
640 | ||
641 | dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", | |
642 | i2c_pnx->adapter->name, alg_data->base, alg_data->irq); | |
643 | ||
644 | return 0; | |
645 | ||
646 | out_irq: | |
647 | free_irq(alg_data->irq, alg_data); | |
648 | out_clock: | |
649 | i2c_pnx->set_clock_stop(pdev); | |
650 | out_unmap: | |
651 | iounmap((void *)alg_data->ioaddr); | |
652 | out_release: | |
653 | release_region(alg_data->base, I2C_PNX_REGION_SIZE); | |
654 | out_drvdata: | |
655 | platform_set_drvdata(pdev, NULL); | |
656 | out: | |
657 | return ret; | |
658 | } | |
659 | ||
660 | static int __devexit i2c_pnx_remove(struct platform_device *pdev) | |
661 | { | |
662 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | |
663 | struct i2c_adapter *adap = i2c_pnx->adapter; | |
664 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
665 | ||
666 | free_irq(alg_data->irq, alg_data); | |
667 | i2c_del_adapter(adap); | |
668 | i2c_pnx->set_clock_stop(pdev); | |
669 | iounmap((void *)alg_data->ioaddr); | |
670 | release_region(alg_data->base, I2C_PNX_REGION_SIZE); | |
671 | platform_set_drvdata(pdev, NULL); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | static struct platform_driver i2c_pnx_driver = { | |
677 | .driver = { | |
678 | .name = "pnx-i2c", | |
679 | .owner = THIS_MODULE, | |
680 | }, | |
681 | .probe = i2c_pnx_probe, | |
682 | .remove = __devexit_p(i2c_pnx_remove), | |
683 | .suspend = i2c_pnx_controller_suspend, | |
684 | .resume = i2c_pnx_controller_resume, | |
685 | }; | |
686 | ||
687 | static int __init i2c_adap_pnx_init(void) | |
688 | { | |
689 | return platform_driver_register(&i2c_pnx_driver); | |
690 | } | |
691 | ||
692 | static void __exit i2c_adap_pnx_exit(void) | |
693 | { | |
694 | platform_driver_unregister(&i2c_pnx_driver); | |
695 | } | |
696 | ||
697 | MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>"); | |
698 | MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses"); | |
699 | MODULE_LICENSE("GPL"); | |
add8eda7 | 700 | MODULE_ALIAS("platform:pnx-i2c"); |
41561f28 | 701 | |
41561f28 VW |
702 | /* We need to make sure I2C is initialized before USB */ |
703 | subsys_initcall(i2c_adap_pnx_init); | |
41561f28 | 704 | module_exit(i2c_adap_pnx_exit); |