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Commit | Line | Data |
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41561f28 VW |
1 | /* |
2 | * Provides I2C support for Philips PNX010x/PNX4008 boards. | |
3 | * | |
4 | * Authors: Dennis Kovalev <dkovalev@ru.mvista.com> | |
5 | * Vitaly Wool <vwool@ru.mvista.com> | |
6 | * | |
7 | * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/completion.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/i2c-pnx.h> | |
a7d73d8c | 22 | #include <linux/io.h> |
0321cb83 RK |
23 | #include <linux/err.h> |
24 | #include <linux/clk.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
0321cb83 | 26 | |
a09e64fb | 27 | #include <mach/hardware.h> |
a7d73d8c | 28 | #include <mach/i2c.h> |
41561f28 VW |
29 | |
30 | #define I2C_PNX_TIMEOUT 10 /* msec */ | |
31 | #define I2C_PNX_SPEED_KHZ 100 | |
32 | #define I2C_PNX_REGION_SIZE 0x100 | |
41561f28 VW |
33 | |
34 | static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) | |
35 | { | |
36 | while (timeout > 0 && | |
37 | (ioread32(I2C_REG_STS(data)) & mstatus_active)) { | |
38 | mdelay(1); | |
39 | timeout--; | |
40 | } | |
41 | return (timeout <= 0); | |
42 | } | |
43 | ||
44 | static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data) | |
45 | { | |
46 | while (timeout > 0 && | |
47 | (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { | |
48 | mdelay(1); | |
49 | timeout--; | |
50 | } | |
51 | return (timeout <= 0); | |
52 | } | |
53 | ||
81d6724a | 54 | static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 55 | { |
81d6724a | 56 | struct timer_list *timer = &alg_data->mif.timer; |
eed18b5f | 57 | unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT); |
41561f28 | 58 | |
b2f125bc KW |
59 | if (expires <= 1) |
60 | expires = 2; | |
61 | ||
41561f28 VW |
62 | del_timer_sync(timer); |
63 | ||
eed18b5f | 64 | dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n", |
41561f28 VW |
65 | jiffies, expires); |
66 | ||
67 | timer->expires = jiffies + expires; | |
81d6724a | 68 | timer->data = (unsigned long)&alg_data; |
41561f28 VW |
69 | |
70 | add_timer(timer); | |
71 | } | |
72 | ||
73 | /** | |
74 | * i2c_pnx_start - start a device | |
75 | * @slave_addr: slave address | |
76 | * @adap: pointer to adapter structure | |
77 | * | |
78 | * Generate a START signal in the desired mode. | |
79 | */ | |
81d6724a RK |
80 | static int i2c_pnx_start(unsigned char slave_addr, |
81 | struct i2c_pnx_algo_data *alg_data) | |
41561f28 | 82 | { |
81d6724a | 83 | dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__, |
41561f28 VW |
84 | slave_addr, alg_data->mif.mode); |
85 | ||
86 | /* Check for 7 bit slave addresses only */ | |
87 | if (slave_addr & ~0x7f) { | |
4be53dbe RK |
88 | dev_err(&alg_data->adapter.dev, |
89 | "%s: Invalid slave address %x. Only 7-bit addresses are supported\n", | |
90 | alg_data->adapter.name, slave_addr); | |
41561f28 VW |
91 | return -EINVAL; |
92 | } | |
93 | ||
94 | /* First, make sure bus is idle */ | |
95 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { | |
96 | /* Somebody else is monopolizing the bus */ | |
4be53dbe RK |
97 | dev_err(&alg_data->adapter.dev, |
98 | "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n", | |
99 | alg_data->adapter.name, slave_addr, | |
100 | ioread32(I2C_REG_CTL(alg_data)), | |
101 | ioread32(I2C_REG_STS(alg_data))); | |
41561f28 VW |
102 | return -EBUSY; |
103 | } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { | |
104 | /* Sorry, we lost the bus */ | |
4be53dbe RK |
105 | dev_err(&alg_data->adapter.dev, |
106 | "%s: Arbitration failure. Slave addr = %02x\n", | |
107 | alg_data->adapter.name, slave_addr); | |
41561f28 VW |
108 | return -EIO; |
109 | } | |
110 | ||
111 | /* | |
112 | * OK, I2C is enabled and we have the bus. | |
113 | * Clear the current TDI and AFI status flags. | |
114 | */ | |
115 | iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, | |
116 | I2C_REG_STS(alg_data)); | |
117 | ||
81d6724a | 118 | dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__, |
41561f28 VW |
119 | (slave_addr << 1) | start_bit | alg_data->mif.mode); |
120 | ||
121 | /* Write the slave address, START bit and R/W bit */ | |
122 | iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, | |
123 | I2C_REG_TX(alg_data)); | |
124 | ||
81d6724a | 125 | dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__); |
41561f28 VW |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
130 | /** | |
131 | * i2c_pnx_stop - stop a device | |
132 | * @adap: pointer to I2C adapter structure | |
133 | * | |
134 | * Generate a STOP signal to terminate the master transaction. | |
135 | */ | |
81d6724a | 136 | static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 137 | { |
41561f28 VW |
138 | /* Only 1 msec max timeout due to interrupt context */ |
139 | long timeout = 1000; | |
140 | ||
81d6724a | 141 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
08882d20 | 142 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
143 | |
144 | /* Write a STOP bit to TX FIFO */ | |
145 | iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data)); | |
146 | ||
147 | /* Wait until the STOP is seen. */ | |
148 | while (timeout > 0 && | |
149 | (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { | |
150 | /* may be called from interrupt context */ | |
151 | udelay(1); | |
152 | timeout--; | |
153 | } | |
154 | ||
81d6724a | 155 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
08882d20 | 156 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
157 | } |
158 | ||
159 | /** | |
160 | * i2c_pnx_master_xmit - transmit data to slave | |
161 | * @adap: pointer to I2C adapter structure | |
162 | * | |
163 | * Sends one byte of data to the slave | |
164 | */ | |
81d6724a | 165 | static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 166 | { |
41561f28 VW |
167 | u32 val; |
168 | ||
81d6724a | 169 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
08882d20 | 170 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
171 | |
172 | if (alg_data->mif.len > 0) { | |
173 | /* We still have something to talk about... */ | |
174 | val = *alg_data->mif.buf++; | |
175 | ||
41561f28 VW |
176 | alg_data->mif.len--; |
177 | iowrite32(val, I2C_REG_TX(alg_data)); | |
178 | ||
4be53dbe RK |
179 | dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n", |
180 | __func__, val, alg_data->mif.len + 1); | |
41561f28 VW |
181 | |
182 | if (alg_data->mif.len == 0) { | |
183 | if (alg_data->last) { | |
184 | /* Wait until the STOP is seen. */ | |
185 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
4be53dbe RK |
186 | dev_err(&alg_data->adapter.dev, |
187 | "The bus is still active after timeout\n"); | |
41561f28 VW |
188 | } |
189 | /* Disable master interrupts */ | |
190 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
191 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
192 | I2C_REG_CTL(alg_data)); | |
193 | ||
194 | del_timer_sync(&alg_data->mif.timer); | |
195 | ||
4be53dbe RK |
196 | dev_dbg(&alg_data->adapter.dev, |
197 | "%s(): Waking up xfer routine.\n", | |
08882d20 | 198 | __func__); |
41561f28 VW |
199 | |
200 | complete(&alg_data->mif.complete); | |
201 | } | |
202 | } else if (alg_data->mif.len == 0) { | |
203 | /* zero-sized transfer */ | |
81d6724a | 204 | i2c_pnx_stop(alg_data); |
41561f28 VW |
205 | |
206 | /* Disable master interrupts. */ | |
207 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
208 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
209 | I2C_REG_CTL(alg_data)); | |
210 | ||
211 | /* Stop timer. */ | |
212 | del_timer_sync(&alg_data->mif.timer); | |
4be53dbe RK |
213 | dev_dbg(&alg_data->adapter.dev, |
214 | "%s(): Waking up xfer routine after zero-xfer.\n", | |
215 | __func__); | |
41561f28 VW |
216 | |
217 | complete(&alg_data->mif.complete); | |
218 | } | |
219 | ||
81d6724a | 220 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
08882d20 | 221 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
226 | /** | |
227 | * i2c_pnx_master_rcv - receive data from slave | |
228 | * @adap: pointer to I2C adapter structure | |
229 | * | |
230 | * Reads one byte data from the slave | |
231 | */ | |
81d6724a | 232 | static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 233 | { |
41561f28 VW |
234 | unsigned int val = 0; |
235 | u32 ctl = 0; | |
236 | ||
81d6724a | 237 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
08882d20 | 238 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
239 | |
240 | /* Check, whether there is already data, | |
241 | * or we didn't 'ask' for it yet. | |
242 | */ | |
243 | if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { | |
4be53dbe RK |
244 | dev_dbg(&alg_data->adapter.dev, |
245 | "%s(): Write dummy data to fill Rx-fifo...\n", | |
246 | __func__); | |
41561f28 VW |
247 | |
248 | if (alg_data->mif.len == 1) { | |
41561f28 VW |
249 | /* |
250 | * Enable interrupt RFDAIE (data in Rx fifo), | |
251 | * and disable DRMIE (need data for Tx) | |
252 | */ | |
253 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
254 | ctl |= mcntrl_rffie | mcntrl_daie; | |
255 | ctl &= ~mcntrl_drmie; | |
256 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
257 | } | |
258 | ||
259 | /* | |
260 | * Now we'll 'ask' for data: | |
261 | * For each byte we want to receive, we must | |
262 | * write a (dummy) byte to the Tx-FIFO. | |
263 | */ | |
264 | iowrite32(val, I2C_REG_TX(alg_data)); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | /* Handle data. */ | |
270 | if (alg_data->mif.len > 0) { | |
271 | val = ioread32(I2C_REG_RX(alg_data)); | |
272 | *alg_data->mif.buf++ = (u8) (val & 0xff); | |
4be53dbe RK |
273 | dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n", |
274 | __func__, val, alg_data->mif.len); | |
41561f28 VW |
275 | |
276 | alg_data->mif.len--; | |
277 | if (alg_data->mif.len == 0) { | |
278 | if (alg_data->last) | |
279 | /* Wait until the STOP is seen. */ | |
280 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
4be53dbe RK |
281 | dev_err(&alg_data->adapter.dev, |
282 | "The bus is still active after timeout\n"); | |
41561f28 VW |
283 | |
284 | /* Disable master interrupts */ | |
285 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
286 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
287 | mcntrl_drmie | mcntrl_daie); | |
288 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
289 | ||
290 | /* Kill timer. */ | |
291 | del_timer_sync(&alg_data->mif.timer); | |
292 | complete(&alg_data->mif.complete); | |
293 | } | |
294 | } | |
295 | ||
81d6724a | 296 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
08882d20 | 297 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
6c566fb7 | 302 | static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) |
41561f28 | 303 | { |
81d6724a | 304 | struct i2c_pnx_algo_data *alg_data = dev_id; |
41561f28 | 305 | u32 stat, ctl; |
41561f28 | 306 | |
4be53dbe RK |
307 | dev_dbg(&alg_data->adapter.dev, |
308 | "%s(): mstat = %x mctrl = %x, mode = %d\n", | |
08882d20 | 309 | __func__, |
41561f28 VW |
310 | ioread32(I2C_REG_STS(alg_data)), |
311 | ioread32(I2C_REG_CTL(alg_data)), | |
312 | alg_data->mif.mode); | |
313 | stat = ioread32(I2C_REG_STS(alg_data)); | |
314 | ||
315 | /* let's see what kind of event this is */ | |
316 | if (stat & mstatus_afi) { | |
317 | /* We lost arbitration in the midst of a transfer */ | |
318 | alg_data->mif.ret = -EIO; | |
319 | ||
320 | /* Disable master interrupts. */ | |
321 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
322 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
323 | mcntrl_drmie); | |
324 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
325 | ||
326 | /* Stop timer, to prevent timeout. */ | |
327 | del_timer_sync(&alg_data->mif.timer); | |
328 | complete(&alg_data->mif.complete); | |
329 | } else if (stat & mstatus_nai) { | |
330 | /* Slave did not acknowledge, generate a STOP */ | |
4be53dbe RK |
331 | dev_dbg(&alg_data->adapter.dev, |
332 | "%s(): Slave did not acknowledge, generating a STOP.\n", | |
08882d20 | 333 | __func__); |
81d6724a | 334 | i2c_pnx_stop(alg_data); |
41561f28 VW |
335 | |
336 | /* Disable master interrupts. */ | |
337 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
338 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
339 | mcntrl_drmie); | |
340 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
341 | ||
342 | /* Our return value. */ | |
343 | alg_data->mif.ret = -EIO; | |
344 | ||
345 | /* Stop timer, to prevent timeout. */ | |
346 | del_timer_sync(&alg_data->mif.timer); | |
347 | complete(&alg_data->mif.complete); | |
348 | } else { | |
349 | /* | |
350 | * Two options: | |
351 | * - Master Tx needs data. | |
352 | * - There is data in the Rx-fifo | |
353 | * The latter is only the case if we have requested for data, | |
354 | * via a dummy write. (See 'i2c_pnx_master_rcv'.) | |
355 | * We therefore check, as a sanity check, whether that interrupt | |
356 | * has been enabled. | |
357 | */ | |
358 | if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { | |
359 | if (alg_data->mif.mode == I2C_SMBUS_WRITE) { | |
81d6724a | 360 | i2c_pnx_master_xmit(alg_data); |
41561f28 | 361 | } else if (alg_data->mif.mode == I2C_SMBUS_READ) { |
81d6724a | 362 | i2c_pnx_master_rcv(alg_data); |
41561f28 VW |
363 | } |
364 | } | |
365 | } | |
366 | ||
367 | /* Clear TDI and AFI bits */ | |
368 | stat = ioread32(I2C_REG_STS(alg_data)); | |
369 | iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); | |
370 | ||
4be53dbe RK |
371 | dev_dbg(&alg_data->adapter.dev, |
372 | "%s(): exiting, stat = %x ctrl = %x.\n", | |
08882d20 | 373 | __func__, ioread32(I2C_REG_STS(alg_data)), |
41561f28 VW |
374 | ioread32(I2C_REG_CTL(alg_data))); |
375 | ||
376 | return IRQ_HANDLED; | |
377 | } | |
378 | ||
379 | static void i2c_pnx_timeout(unsigned long data) | |
380 | { | |
81d6724a | 381 | struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data; |
41561f28 VW |
382 | u32 ctl; |
383 | ||
4be53dbe RK |
384 | dev_err(&alg_data->adapter.dev, |
385 | "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n", | |
386 | ioread32(I2C_REG_STS(alg_data)), | |
387 | ioread32(I2C_REG_CTL(alg_data))); | |
41561f28 VW |
388 | |
389 | /* Reset master and disable interrupts */ | |
390 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
391 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie); | |
392 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
393 | ||
394 | ctl |= mcntrl_reset; | |
395 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
396 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
397 | alg_data->mif.ret = -EIO; | |
398 | complete(&alg_data->mif.complete); | |
399 | } | |
400 | ||
81d6724a | 401 | static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data) |
41561f28 | 402 | { |
41561f28 VW |
403 | u32 stat; |
404 | ||
405 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { | |
81d6724a | 406 | dev_err(&alg_data->adapter.dev, |
41561f28 | 407 | "%s: Bus is still active after xfer. Reset it...\n", |
4be53dbe | 408 | alg_data->adapter.name); |
41561f28 VW |
409 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, |
410 | I2C_REG_CTL(alg_data)); | |
411 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
412 | } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) { | |
413 | /* If there is data in the fifo's after transfer, | |
414 | * flush fifo's by reset. | |
415 | */ | |
416 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
417 | I2C_REG_CTL(alg_data)); | |
418 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
419 | } else if (stat & mstatus_nai) { | |
420 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
421 | I2C_REG_CTL(alg_data)); | |
422 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
423 | } | |
424 | } | |
425 | ||
426 | /** | |
427 | * i2c_pnx_xfer - generic transfer entry point | |
428 | * @adap: pointer to I2C adapter structure | |
429 | * @msgs: array of messages | |
430 | * @num: number of messages | |
431 | * | |
432 | * Initiates the transfer | |
433 | */ | |
434 | static int | |
435 | i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
436 | { | |
437 | struct i2c_msg *pmsg; | |
438 | int rc = 0, completed = 0, i; | |
439 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
440 | u32 stat = ioread32(I2C_REG_STS(alg_data)); | |
441 | ||
4be53dbe RK |
442 | dev_dbg(&alg_data->adapter.dev, |
443 | "%s(): entering: %d messages, stat = %04x.\n", | |
08882d20 | 444 | __func__, num, ioread32(I2C_REG_STS(alg_data))); |
41561f28 | 445 | |
81d6724a | 446 | bus_reset_if_active(alg_data); |
41561f28 VW |
447 | |
448 | /* Process transactions in a loop. */ | |
449 | for (i = 0; rc >= 0 && i < num; i++) { | |
450 | u8 addr; | |
451 | ||
452 | pmsg = &msgs[i]; | |
453 | addr = pmsg->addr; | |
454 | ||
455 | if (pmsg->flags & I2C_M_TEN) { | |
81d6724a | 456 | dev_err(&alg_data->adapter.dev, |
41561f28 | 457 | "%s: 10 bits addr not supported!\n", |
81d6724a | 458 | alg_data->adapter.name); |
41561f28 VW |
459 | rc = -EINVAL; |
460 | break; | |
461 | } | |
462 | ||
463 | alg_data->mif.buf = pmsg->buf; | |
464 | alg_data->mif.len = pmsg->len; | |
465 | alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ? | |
466 | I2C_SMBUS_READ : I2C_SMBUS_WRITE; | |
467 | alg_data->mif.ret = 0; | |
468 | alg_data->last = (i == num - 1); | |
469 | ||
4be53dbe RK |
470 | dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n", |
471 | __func__, alg_data->mif.mode, alg_data->mif.len); | |
41561f28 | 472 | |
81d6724a | 473 | i2c_pnx_arm_timer(alg_data); |
41561f28 VW |
474 | |
475 | /* initialize the completion var */ | |
476 | init_completion(&alg_data->mif.complete); | |
477 | ||
478 | /* Enable master interrupt */ | |
479 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie | | |
480 | mcntrl_naie | mcntrl_drmie, | |
481 | I2C_REG_CTL(alg_data)); | |
482 | ||
483 | /* Put start-code and slave-address on the bus. */ | |
81d6724a | 484 | rc = i2c_pnx_start(addr, alg_data); |
41561f28 VW |
485 | if (rc < 0) |
486 | break; | |
487 | ||
488 | /* Wait for completion */ | |
489 | wait_for_completion(&alg_data->mif.complete); | |
490 | ||
491 | if (!(rc = alg_data->mif.ret)) | |
492 | completed++; | |
4be53dbe RK |
493 | dev_dbg(&alg_data->adapter.dev, |
494 | "%s(): Complete, return code = %d.\n", | |
08882d20 | 495 | __func__, rc); |
41561f28 VW |
496 | |
497 | /* Clear TDI and AFI bits in case they are set. */ | |
498 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { | |
81d6724a | 499 | dev_dbg(&alg_data->adapter.dev, |
41561f28 | 500 | "%s: TDI still set... clearing now.\n", |
81d6724a | 501 | alg_data->adapter.name); |
41561f28 VW |
502 | iowrite32(stat, I2C_REG_STS(alg_data)); |
503 | } | |
504 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { | |
81d6724a | 505 | dev_dbg(&alg_data->adapter.dev, |
41561f28 | 506 | "%s: AFI still set... clearing now.\n", |
81d6724a | 507 | alg_data->adapter.name); |
41561f28 VW |
508 | iowrite32(stat, I2C_REG_STS(alg_data)); |
509 | } | |
510 | } | |
511 | ||
81d6724a | 512 | bus_reset_if_active(alg_data); |
41561f28 VW |
513 | |
514 | /* Cleanup to be sure... */ | |
515 | alg_data->mif.buf = NULL; | |
516 | alg_data->mif.len = 0; | |
517 | ||
81d6724a | 518 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n", |
08882d20 | 519 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
520 | |
521 | if (completed != num) | |
522 | return ((rc < 0) ? rc : -EREMOTEIO); | |
523 | ||
524 | return num; | |
525 | } | |
526 | ||
527 | static u32 i2c_pnx_func(struct i2c_adapter *adapter) | |
528 | { | |
529 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
530 | } | |
531 | ||
532 | static struct i2c_algorithm pnx_algorithm = { | |
533 | .master_xfer = i2c_pnx_xfer, | |
534 | .functionality = i2c_pnx_func, | |
535 | }; | |
536 | ||
a0dcf19f | 537 | #ifdef CONFIG_PM |
41561f28 VW |
538 | static int i2c_pnx_controller_suspend(struct platform_device *pdev, |
539 | pm_message_t state) | |
540 | { | |
9d7f7363 | 541 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
0321cb83 | 542 | |
ebdbbf20 RK |
543 | /* FIXME: shouldn't this be clk_disable? */ |
544 | clk_enable(alg_data->clk); | |
0321cb83 RK |
545 | |
546 | return 0; | |
41561f28 VW |
547 | } |
548 | ||
549 | static int i2c_pnx_controller_resume(struct platform_device *pdev) | |
550 | { | |
9d7f7363 | 551 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
0321cb83 | 552 | |
ebdbbf20 | 553 | return clk_enable(alg_data->clk); |
41561f28 | 554 | } |
a0dcf19f RK |
555 | #else |
556 | #define i2c_pnx_controller_suspend NULL | |
557 | #define i2c_pnx_controller_resume NULL | |
558 | #endif | |
41561f28 VW |
559 | |
560 | static int __devinit i2c_pnx_probe(struct platform_device *pdev) | |
561 | { | |
562 | unsigned long tmp; | |
563 | int ret = 0; | |
564 | struct i2c_pnx_algo_data *alg_data; | |
6fff3da9 | 565 | unsigned long freq; |
41561f28 VW |
566 | struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; |
567 | ||
9d7f7363 | 568 | if (!i2c_pnx || !i2c_pnx->name) { |
41561f28 | 569 | dev_err(&pdev->dev, "%s: no platform data supplied\n", |
08882d20 | 570 | __func__); |
41561f28 VW |
571 | ret = -EINVAL; |
572 | goto out; | |
573 | } | |
574 | ||
44c5d739 RK |
575 | alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL); |
576 | if (!alg_data) { | |
577 | ret = -ENOMEM; | |
578 | goto err_kzalloc; | |
579 | } | |
580 | ||
9d7f7363 | 581 | platform_set_drvdata(pdev, alg_data); |
41561f28 | 582 | |
9d7f7363 RK |
583 | strlcpy(alg_data->adapter.name, i2c_pnx->name, |
584 | sizeof(alg_data->adapter.name)); | |
585 | alg_data->adapter.dev.parent = &pdev->dev; | |
586 | alg_data->adapter.algo = &pnx_algorithm; | |
587 | alg_data->adapter.algo_data = alg_data; | |
588 | alg_data->adapter.nr = pdev->id; | |
589 | alg_data->i2c_pnx = i2c_pnx; | |
0321cb83 RK |
590 | |
591 | alg_data->clk = clk_get(&pdev->dev, NULL); | |
592 | if (IS_ERR(alg_data->clk)) { | |
593 | ret = PTR_ERR(alg_data->clk); | |
594 | goto out_drvdata; | |
595 | } | |
596 | ||
41561f28 VW |
597 | init_timer(&alg_data->mif.timer); |
598 | alg_data->mif.timer.function = i2c_pnx_timeout; | |
81d6724a | 599 | alg_data->mif.timer.data = (unsigned long)alg_data; |
41561f28 VW |
600 | |
601 | /* Register I/O resource */ | |
44c5d739 | 602 | if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE, |
449d2c75 | 603 | pdev->name)) { |
41561f28 VW |
604 | dev_err(&pdev->dev, |
605 | "I/O region 0x%08x for I2C already in use.\n", | |
44c5d739 | 606 | i2c_pnx->base); |
41561f28 | 607 | ret = -ENODEV; |
0321cb83 | 608 | goto out_clkget; |
41561f28 VW |
609 | } |
610 | ||
44c5d739 | 611 | alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
88d968b2 | 612 | if (!alg_data->ioaddr) { |
41561f28 VW |
613 | dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); |
614 | ret = -ENOMEM; | |
615 | goto out_release; | |
616 | } | |
617 | ||
ebdbbf20 RK |
618 | ret = clk_enable(alg_data->clk); |
619 | if (ret) | |
620 | goto out_unmap; | |
41561f28 | 621 | |
6fff3da9 RK |
622 | freq = clk_get_rate(alg_data->clk); |
623 | ||
41561f28 VW |
624 | /* |
625 | * Clock Divisor High This value is the number of system clocks | |
626 | * the serial clock (SCL) will be high. | |
627 | * For example, if the system clock period is 50 ns and the maximum | |
628 | * desired serial period is 10000 ns (100 kHz), then CLKHI would be | |
629 | * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value | |
630 | * programmed into CLKHI will vary from this slightly due to | |
631 | * variations in the output pad's rise and fall times as well as | |
632 | * the deglitching filter length. | |
633 | */ | |
634 | ||
6fff3da9 | 635 | tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; |
be80dbaa KW |
636 | if (tmp > 0x3FF) |
637 | tmp = 0x3FF; | |
41561f28 VW |
638 | iowrite32(tmp, I2C_REG_CKH(alg_data)); |
639 | iowrite32(tmp, I2C_REG_CKL(alg_data)); | |
640 | ||
641 | iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); | |
642 | if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { | |
643 | ret = -ENODEV; | |
ebdbbf20 | 644 | goto out_clock; |
41561f28 VW |
645 | } |
646 | init_completion(&alg_data->mif.complete); | |
647 | ||
44c5d739 | 648 | ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt, |
81d6724a | 649 | 0, pdev->name, alg_data); |
41561f28 VW |
650 | if (ret) |
651 | goto out_clock; | |
652 | ||
653 | /* Register this adapter with the I2C subsystem */ | |
9d7f7363 | 654 | ret = i2c_add_numbered_adapter(&alg_data->adapter); |
41561f28 VW |
655 | if (ret < 0) { |
656 | dev_err(&pdev->dev, "I2C: Failed to add bus\n"); | |
657 | goto out_irq; | |
658 | } | |
659 | ||
660 | dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", | |
9d7f7363 | 661 | alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq); |
41561f28 VW |
662 | |
663 | return 0; | |
664 | ||
665 | out_irq: | |
81d6724a | 666 | free_irq(i2c_pnx->irq, alg_data); |
41561f28 | 667 | out_clock: |
ebdbbf20 | 668 | clk_disable(alg_data->clk); |
41561f28 | 669 | out_unmap: |
88d968b2 | 670 | iounmap(alg_data->ioaddr); |
41561f28 | 671 | out_release: |
44c5d739 | 672 | release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
0321cb83 RK |
673 | out_clkget: |
674 | clk_put(alg_data->clk); | |
41561f28 | 675 | out_drvdata: |
44c5d739 RK |
676 | kfree(alg_data); |
677 | err_kzalloc: | |
41561f28 VW |
678 | platform_set_drvdata(pdev, NULL); |
679 | out: | |
680 | return ret; | |
681 | } | |
682 | ||
683 | static int __devexit i2c_pnx_remove(struct platform_device *pdev) | |
684 | { | |
9d7f7363 RK |
685 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
686 | struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx; | |
41561f28 | 687 | |
81d6724a | 688 | free_irq(i2c_pnx->irq, alg_data); |
9d7f7363 | 689 | i2c_del_adapter(&alg_data->adapter); |
ebdbbf20 | 690 | clk_disable(alg_data->clk); |
88d968b2 | 691 | iounmap(alg_data->ioaddr); |
44c5d739 | 692 | release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
0321cb83 | 693 | clk_put(alg_data->clk); |
44c5d739 | 694 | kfree(alg_data); |
41561f28 VW |
695 | platform_set_drvdata(pdev, NULL); |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static struct platform_driver i2c_pnx_driver = { | |
701 | .driver = { | |
702 | .name = "pnx-i2c", | |
703 | .owner = THIS_MODULE, | |
704 | }, | |
705 | .probe = i2c_pnx_probe, | |
706 | .remove = __devexit_p(i2c_pnx_remove), | |
707 | .suspend = i2c_pnx_controller_suspend, | |
708 | .resume = i2c_pnx_controller_resume, | |
709 | }; | |
710 | ||
711 | static int __init i2c_adap_pnx_init(void) | |
712 | { | |
713 | return platform_driver_register(&i2c_pnx_driver); | |
714 | } | |
715 | ||
716 | static void __exit i2c_adap_pnx_exit(void) | |
717 | { | |
718 | platform_driver_unregister(&i2c_pnx_driver); | |
719 | } | |
720 | ||
721 | MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>"); | |
722 | MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses"); | |
723 | MODULE_LICENSE("GPL"); | |
add8eda7 | 724 | MODULE_ALIAS("platform:pnx-i2c"); |
41561f28 | 725 | |
41561f28 VW |
726 | /* We need to make sure I2C is initialized before USB */ |
727 | subsys_initcall(i2c_adap_pnx_init); | |
41561f28 | 728 | module_exit(i2c_adap_pnx_exit); |