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Commit | Line | Data |
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b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
3ad2f3fb | 15 | * Jun 2002: Properly separated algo/adap [FB] |
b652b438 RK |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
b652b438 RK |
25 | #include <linux/init.h> |
26 | #include <linux/time.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/i2c-pxa.h> | |
63fe122b HZ |
32 | #include <linux/of.h> |
33 | #include <linux/of_device.h> | |
baa8cab0 | 34 | #include <linux/of_i2c.h> |
d052d1be | 35 | #include <linux/platform_device.h> |
c3cef3f3 RK |
36 | #include <linux/err.h> |
37 | #include <linux/clk.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
21782180 | 39 | #include <linux/io.h> |
b459396e | 40 | #include <linux/i2c/pxa-i2c.h> |
b652b438 | 41 | |
b652b438 | 42 | #include <asm/irq.h> |
283afa06 | 43 | |
d6668c7c SAS |
44 | struct pxa_reg_layout { |
45 | u32 ibmr; | |
46 | u32 idbr; | |
47 | u32 icr; | |
48 | u32 isr; | |
49 | u32 isar; | |
50 | }; | |
51 | ||
52 | enum pxa_i2c_types { | |
53 | REGS_PXA2XX, | |
54 | REGS_PXA3XX, | |
7e94dd15 | 55 | REGS_CE4100, |
d6668c7c SAS |
56 | }; |
57 | ||
f23d4911 | 58 | /* |
d6668c7c | 59 | * I2C registers definitions |
f23d4911 | 60 | */ |
d6668c7c SAS |
61 | static struct pxa_reg_layout pxa_reg_layout[] = { |
62 | [REGS_PXA2XX] = { | |
d6668c7c SAS |
63 | .ibmr = 0x00, |
64 | .idbr = 0x08, | |
65 | .icr = 0x10, | |
66 | .isr = 0x18, | |
67 | .isar = 0x20, | |
68 | }, | |
23e74a86 VK |
69 | [REGS_PXA3XX] = { |
70 | .ibmr = 0x00, | |
71 | .idbr = 0x04, | |
72 | .icr = 0x08, | |
73 | .isr = 0x0c, | |
74 | .isar = 0x10, | |
75 | }, | |
7e94dd15 SAS |
76 | [REGS_CE4100] = { |
77 | .ibmr = 0x14, | |
78 | .idbr = 0x0c, | |
79 | .icr = 0x00, | |
80 | .isr = 0x04, | |
81 | /* no isar register */ | |
82 | }, | |
d6668c7c | 83 | }; |
f23d4911 EM |
84 | |
85 | static const struct platform_device_id i2c_pxa_id_table[] = { | |
d6668c7c SAS |
86 | { "pxa2xx-i2c", REGS_PXA2XX }, |
87 | { "pxa3xx-pwri2c", REGS_PXA3XX }, | |
7e94dd15 | 88 | { "ce4100-i2c", REGS_CE4100 }, |
f23d4911 EM |
89 | { }, |
90 | }; | |
91 | MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); | |
92 | ||
283afa06 | 93 | /* |
d6668c7c | 94 | * I2C bit definitions |
283afa06 | 95 | */ |
283afa06 EM |
96 | |
97 | #define ICR_START (1 << 0) /* start bit */ | |
98 | #define ICR_STOP (1 << 1) /* stop bit */ | |
99 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ | |
100 | #define ICR_TB (1 << 3) /* transfer byte bit */ | |
101 | #define ICR_MA (1 << 4) /* master abort */ | |
102 | #define ICR_SCLE (1 << 5) /* master clock enable */ | |
103 | #define ICR_IUE (1 << 6) /* unit enable */ | |
104 | #define ICR_GCD (1 << 7) /* general call disable */ | |
105 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ | |
106 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ | |
107 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ | |
108 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ | |
109 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ | |
110 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ | |
111 | #define ICR_UR (1 << 14) /* unit reset */ | |
112 | #define ICR_FM (1 << 15) /* fast mode */ | |
113 | ||
114 | #define ISR_RWM (1 << 0) /* read/write mode */ | |
115 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ | |
116 | #define ISR_UB (1 << 2) /* unit busy */ | |
117 | #define ISR_IBB (1 << 3) /* bus busy */ | |
118 | #define ISR_SSD (1 << 4) /* slave stop detected */ | |
119 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ | |
120 | #define ISR_ITE (1 << 6) /* tx buffer empty */ | |
121 | #define ISR_IRF (1 << 7) /* rx buffer full */ | |
122 | #define ISR_GCAD (1 << 8) /* general call address detected */ | |
123 | #define ISR_SAD (1 << 9) /* slave address detected */ | |
124 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ | |
b652b438 RK |
125 | |
126 | struct pxa_i2c { | |
127 | spinlock_t lock; | |
128 | wait_queue_head_t wait; | |
129 | struct i2c_msg *msg; | |
130 | unsigned int msg_num; | |
131 | unsigned int msg_idx; | |
132 | unsigned int msg_ptr; | |
133 | unsigned int slave_addr; | |
134 | ||
135 | struct i2c_adapter adap; | |
c3cef3f3 | 136 | struct clk *clk; |
b652b438 RK |
137 | #ifdef CONFIG_I2C_PXA_SLAVE |
138 | struct i2c_slave_client *slave; | |
139 | #endif | |
140 | ||
141 | unsigned int irqlogidx; | |
142 | u32 isrlog[32]; | |
143 | u32 icrlog[32]; | |
a7b4e550 GL |
144 | |
145 | void __iomem *reg_base; | |
d6668c7c SAS |
146 | void __iomem *reg_ibmr; |
147 | void __iomem *reg_idbr; | |
148 | void __iomem *reg_icr; | |
149 | void __iomem *reg_isr; | |
150 | void __iomem *reg_isar; | |
a7b4e550 GL |
151 | |
152 | unsigned long iobase; | |
153 | unsigned long iosize; | |
154 | ||
155 | int irq; | |
c46c9482 JC |
156 | unsigned int use_pio :1; |
157 | unsigned int fast_mode :1; | |
b652b438 RK |
158 | }; |
159 | ||
d6668c7c SAS |
160 | #define _IBMR(i2c) ((i2c)->reg_ibmr) |
161 | #define _IDBR(i2c) ((i2c)->reg_idbr) | |
162 | #define _ICR(i2c) ((i2c)->reg_icr) | |
163 | #define _ISR(i2c) ((i2c)->reg_isr) | |
164 | #define _ISAR(i2c) ((i2c)->reg_isar) | |
a7b4e550 | 165 | |
b652b438 RK |
166 | /* |
167 | * I2C Slave mode address | |
168 | */ | |
169 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
170 | ||
b652b438 RK |
171 | #ifdef DEBUG |
172 | ||
173 | struct bits { | |
174 | u32 mask; | |
175 | const char *set; | |
176 | const char *unset; | |
177 | }; | |
ed11399d | 178 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
179 | |
180 | static inline void | |
181 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
182 | { | |
183 | printk("%s %08x: ", prefix, val); | |
184 | while (num--) { | |
185 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
186 | if (str) | |
187 | printk("%s ", str); | |
188 | bits++; | |
189 | } | |
190 | } | |
191 | ||
192 | static const struct bits isr_bits[] = { | |
ed11399d JS |
193 | PXA_BIT(ISR_RWM, "RX", "TX"), |
194 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
195 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
196 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
197 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
198 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
199 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
200 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
201 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
202 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
203 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
204 | }; |
205 | ||
206 | static void decode_ISR(unsigned int val) | |
207 | { | |
6fd60fa9 | 208 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
209 | printk("\n"); |
210 | } | |
211 | ||
212 | static const struct bits icr_bits[] = { | |
ed11399d JS |
213 | PXA_BIT(ICR_START, "START", NULL), |
214 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
215 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
216 | PXA_BIT(ICR_TB, "TB", NULL), | |
217 | PXA_BIT(ICR_MA, "MA", NULL), | |
218 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
219 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
220 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
221 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
222 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
223 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
224 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
225 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
226 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
227 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
228 | }; |
229 | ||
d6a7b5f8 | 230 | #ifdef CONFIG_I2C_PXA_SLAVE |
b652b438 RK |
231 | static void decode_ICR(unsigned int val) |
232 | { | |
6fd60fa9 | 233 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
234 | printk("\n"); |
235 | } | |
d6a7b5f8 | 236 | #endif |
b652b438 RK |
237 | |
238 | static unsigned int i2c_debug = DEBUG; | |
239 | ||
240 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
241 | { | |
a7b4e550 GL |
242 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
243 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
244 | } |
245 | ||
08882d20 | 246 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) |
b652b438 RK |
247 | |
248 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
249 | { | |
250 | unsigned int i; | |
154d22b0 FS |
251 | printk(KERN_ERR "i2c: error: %s\n", why); |
252 | printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
b652b438 | 253 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); |
154d22b0 FS |
254 | printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n", |
255 | readl(_ICR(i2c)), readl(_ISR(i2c))); | |
256 | printk(KERN_DEBUG "i2c: log: "); | |
b652b438 RK |
257 | for (i = 0; i < i2c->irqlogidx; i++) |
258 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
259 | printk("\n"); | |
260 | } | |
261 | ||
0d813d99 WS |
262 | #else /* ifdef DEBUG */ |
263 | ||
264 | #define i2c_debug 0 | |
265 | ||
266 | #define show_state(i2c) do { } while (0) | |
267 | #define decode_ISR(val) do { } while (0) | |
268 | #define decode_ICR(val) do { } while (0) | |
269 | #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) | |
270 | ||
271 | #endif /* ifdef DEBUG / else */ | |
272 | ||
273 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
274 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); | |
275 | ||
b652b438 RK |
276 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) |
277 | { | |
a7b4e550 | 278 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
279 | } |
280 | ||
281 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
282 | { | |
387fa6a5 | 283 | int i = 250; |
b652b438 RK |
284 | |
285 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 286 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
287 | return; |
288 | } | |
289 | ||
387fa6a5 | 290 | while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
a7b4e550 | 291 | unsigned long icr = readl(_ICR(i2c)); |
b652b438 RK |
292 | |
293 | icr &= ~ICR_START; | |
294 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
295 | ||
a7b4e550 | 296 | writel(icr, _ICR(i2c)); |
b652b438 RK |
297 | |
298 | show_state(i2c); | |
299 | ||
387fa6a5 DES |
300 | mdelay(1); |
301 | i --; | |
b652b438 RK |
302 | } |
303 | ||
a7b4e550 GL |
304 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
305 | _ICR(i2c)); | |
b652b438 RK |
306 | } |
307 | ||
308 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
309 | { | |
310 | int timeout = DEF_TIMEOUT; | |
311 | ||
a7b4e550 GL |
312 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
313 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
314 | timeout += 4; |
315 | ||
316 | msleep(2); | |
317 | show_state(i2c); | |
318 | } | |
319 | ||
d10db3a0 | 320 | if (timeout < 0) |
b652b438 RK |
321 | show_state(i2c); |
322 | ||
d10db3a0 | 323 | return timeout < 0 ? I2C_RETRY : 0; |
b652b438 RK |
324 | } |
325 | ||
326 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
327 | { | |
328 | unsigned long timeout = jiffies + HZ*4; | |
329 | ||
330 | while (time_before(jiffies, timeout)) { | |
331 | if (i2c_debug > 1) | |
6fd60fa9 | 332 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 333 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 334 | |
a7b4e550 | 335 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 336 | if (i2c_debug > 0) |
6fd60fa9 | 337 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
338 | goto out; |
339 | } | |
340 | ||
341 | /* wait for unit and bus being not busy, and we also do a | |
342 | * quick check of the i2c lines themselves to ensure they've | |
343 | * gone high... | |
344 | */ | |
a7b4e550 | 345 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 346 | if (i2c_debug > 0) |
6fd60fa9 | 347 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
348 | return 1; |
349 | } | |
350 | ||
351 | msleep(1); | |
352 | } | |
353 | ||
354 | if (i2c_debug > 0) | |
6fd60fa9 | 355 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
356 | out: |
357 | return 0; | |
358 | } | |
359 | ||
360 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
361 | { | |
362 | if (i2c_debug) | |
6fd60fa9 | 363 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 364 | |
a7b4e550 | 365 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 366 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 367 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 368 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
369 | return I2C_RETRY; |
370 | } | |
371 | } | |
372 | ||
a7b4e550 | 373 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
374 | return 0; |
375 | } | |
376 | ||
377 | #ifdef CONFIG_I2C_PXA_SLAVE | |
378 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
379 | { | |
380 | unsigned long timeout = jiffies + HZ*1; | |
381 | ||
382 | /* wait for stop */ | |
383 | ||
384 | show_state(i2c); | |
385 | ||
386 | while (time_before(jiffies, timeout)) { | |
387 | if (i2c_debug > 1) | |
6fd60fa9 | 388 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 389 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 390 | |
a7b4e550 GL |
391 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
392 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
393 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 394 | if (i2c_debug > 1) |
6fd60fa9 | 395 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
396 | return 1; |
397 | } | |
398 | ||
399 | msleep(1); | |
400 | } | |
401 | ||
402 | if (i2c_debug > 0) | |
6fd60fa9 | 403 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
404 | return 0; |
405 | } | |
406 | ||
407 | /* | |
408 | * clear the hold on the bus, and take of anything else | |
409 | * that has been configured | |
410 | */ | |
411 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
412 | { | |
413 | show_state(i2c); | |
414 | ||
415 | if (errcode < 0) { | |
416 | udelay(100); /* simple delay */ | |
417 | } else { | |
418 | /* we need to wait for the stop condition to end */ | |
419 | ||
420 | /* if we where in stop, then clear... */ | |
a7b4e550 | 421 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 422 | udelay(100); |
a7b4e550 | 423 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
424 | } |
425 | ||
426 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
427 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
428 | __func__); | |
b652b438 RK |
429 | return; |
430 | } | |
431 | } | |
432 | ||
a7b4e550 GL |
433 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
434 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
435 | |
436 | if (i2c_debug) { | |
a7b4e550 GL |
437 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
438 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
439 | } |
440 | } | |
441 | #else | |
442 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
443 | #endif | |
444 | ||
445 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
446 | { | |
447 | pr_debug("Resetting I2C Controller Unit\n"); | |
448 | ||
449 | /* abort any transfer currently under way */ | |
450 | i2c_pxa_abort(i2c); | |
451 | ||
452 | /* reset according to 9.8 */ | |
a7b4e550 GL |
453 | writel(ICR_UR, _ICR(i2c)); |
454 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
455 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 456 | |
7e94dd15 SAS |
457 | if (i2c->reg_isar) |
458 | writel(i2c->slave_addr, _ISAR(i2c)); | |
b652b438 RK |
459 | |
460 | /* set control register values */ | |
c46c9482 | 461 | writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); |
b652b438 RK |
462 | |
463 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 464 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 465 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
466 | #endif |
467 | ||
468 | i2c_pxa_set_slave(i2c, 0); | |
469 | ||
470 | /* enable unit */ | |
a7b4e550 | 471 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
472 | udelay(100); |
473 | } | |
474 | ||
475 | ||
476 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
477 | /* |
478 | * PXA I2C Slave mode | |
479 | */ | |
480 | ||
481 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
482 | { | |
483 | if (isr & ISR_BED) { | |
484 | /* what should we do here? */ | |
485 | } else { | |
84b5abe6 RK |
486 | int ret = 0; |
487 | ||
488 | if (i2c->slave != NULL) | |
489 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 490 | |
a7b4e550 GL |
491 | writel(ret, _IDBR(i2c)); |
492 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
493 | } |
494 | } | |
495 | ||
496 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
497 | { | |
a7b4e550 | 498 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
499 | |
500 | if (i2c->slave != NULL) | |
501 | i2c->slave->write(i2c->slave->data, byte); | |
502 | ||
a7b4e550 | 503 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
504 | } |
505 | ||
506 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
507 | { | |
508 | int timeout; | |
509 | ||
510 | if (i2c_debug > 0) | |
6fd60fa9 | 511 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
512 | (isr & ISR_RWM) ? 'r' : 't'); |
513 | ||
514 | if (i2c->slave != NULL) | |
515 | i2c->slave->event(i2c->slave->data, | |
516 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
517 | ||
518 | /* | |
519 | * slave could interrupt in the middle of us generating a | |
520 | * start condition... if this happens, we'd better back off | |
521 | * and stop holding the poor thing up | |
522 | */ | |
a7b4e550 GL |
523 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
524 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
525 | |
526 | timeout = 0x10000; | |
527 | ||
528 | while (1) { | |
a7b4e550 | 529 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
530 | break; |
531 | ||
532 | timeout--; | |
533 | ||
534 | if (timeout <= 0) { | |
6fd60fa9 | 535 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
536 | break; |
537 | } | |
538 | } | |
539 | ||
a7b4e550 | 540 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
541 | } |
542 | ||
543 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
544 | { | |
545 | if (i2c_debug > 2) | |
6fd60fa9 | 546 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
547 | |
548 | if (i2c->slave != NULL) | |
549 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
550 | ||
551 | if (i2c_debug > 2) | |
6fd60fa9 | 552 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
553 | |
554 | /* | |
555 | * If we have a master-mode message waiting, | |
556 | * kick it off now that the slave has completed. | |
557 | */ | |
558 | if (i2c->msg) | |
559 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
560 | } | |
561 | #else | |
562 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
563 | { | |
564 | if (isr & ISR_BED) { | |
565 | /* what should we do here? */ | |
566 | } else { | |
a7b4e550 GL |
567 | writel(0, _IDBR(i2c)); |
568 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
569 | } |
570 | } | |
571 | ||
572 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
573 | { | |
a7b4e550 | 574 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
575 | } |
576 | ||
577 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
578 | { | |
579 | int timeout; | |
580 | ||
581 | /* | |
582 | * slave could interrupt in the middle of us generating a | |
583 | * start condition... if this happens, we'd better back off | |
584 | * and stop holding the poor thing up | |
585 | */ | |
a7b4e550 GL |
586 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
587 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
588 | |
589 | timeout = 0x10000; | |
590 | ||
591 | while (1) { | |
a7b4e550 | 592 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
593 | break; |
594 | ||
595 | timeout--; | |
596 | ||
597 | if (timeout <= 0) { | |
6fd60fa9 | 598 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
599 | break; |
600 | } | |
601 | } | |
602 | ||
a7b4e550 | 603 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
604 | } |
605 | ||
606 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
607 | { | |
608 | if (i2c->msg) | |
609 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
610 | } | |
611 | #endif | |
612 | ||
613 | /* | |
614 | * PXA I2C Master mode | |
615 | */ | |
616 | ||
617 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
618 | { | |
619 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
620 | ||
621 | if (msg->flags & I2C_M_RD) | |
622 | addr |= 1; | |
623 | ||
624 | return addr; | |
625 | } | |
626 | ||
627 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
628 | { | |
629 | u32 icr; | |
630 | ||
631 | /* | |
632 | * Step 1: target slave address into IDBR | |
633 | */ | |
a7b4e550 | 634 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
635 | |
636 | /* | |
637 | * Step 2: initiate the write. | |
638 | */ | |
a7b4e550 GL |
639 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
640 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
641 | } |
642 | ||
7d054817 JD |
643 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
644 | { | |
645 | u32 icr; | |
646 | ||
647 | /* | |
648 | * Clear the STOP and ACK flags | |
649 | */ | |
650 | icr = readl(_ICR(i2c)); | |
651 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 652 | writel(icr, _ICR(i2c)); |
7d054817 JD |
653 | } |
654 | ||
b7a36701 MR |
655 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
656 | { | |
657 | /* make timeout the same as for interrupt based functions */ | |
658 | long timeout = 2 * DEF_TIMEOUT; | |
659 | ||
660 | /* | |
661 | * Wait for the bus to become free. | |
662 | */ | |
663 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { | |
664 | udelay(1000); | |
665 | show_state(i2c); | |
666 | } | |
667 | ||
d10db3a0 | 668 | if (timeout < 0) { |
b7a36701 MR |
669 | show_state(i2c); |
670 | dev_err(&i2c->adap.dev, | |
671 | "i2c_pxa: timeout waiting for bus free\n"); | |
672 | return I2C_RETRY; | |
673 | } | |
674 | ||
675 | /* | |
676 | * Set master mode. | |
677 | */ | |
678 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, | |
684 | struct i2c_msg *msg, int num) | |
685 | { | |
686 | unsigned long timeout = 500000; /* 5 seconds */ | |
687 | int ret = 0; | |
688 | ||
689 | ret = i2c_pxa_pio_set_master(i2c); | |
690 | if (ret) | |
691 | goto out; | |
692 | ||
693 | i2c->msg = msg; | |
694 | i2c->msg_num = num; | |
695 | i2c->msg_idx = 0; | |
696 | i2c->msg_ptr = 0; | |
697 | i2c->irqlogidx = 0; | |
698 | ||
699 | i2c_pxa_start_message(i2c); | |
700 | ||
a746b578 | 701 | while (i2c->msg_num > 0 && --timeout) { |
b7a36701 MR |
702 | i2c_pxa_handler(0, i2c); |
703 | udelay(10); | |
704 | } | |
705 | ||
706 | i2c_pxa_stop_message(i2c); | |
707 | ||
708 | /* | |
709 | * We place the return code in i2c->msg_idx. | |
710 | */ | |
711 | ret = i2c->msg_idx; | |
712 | ||
713 | out: | |
714 | if (timeout == 0) | |
715 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
716 | ||
717 | return ret; | |
718 | } | |
719 | ||
b652b438 | 720 | /* |
3fb9a655 | 721 | * We are protected by the adapter bus mutex. |
b652b438 RK |
722 | */ |
723 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
724 | { | |
725 | long timeout; | |
726 | int ret; | |
727 | ||
728 | /* | |
729 | * Wait for the bus to become free. | |
730 | */ | |
731 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
732 | if (ret) { | |
6fd60fa9 | 733 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
734 | goto out; |
735 | } | |
736 | ||
737 | /* | |
738 | * Set master mode. | |
739 | */ | |
740 | ret = i2c_pxa_set_master(i2c); | |
741 | if (ret) { | |
6fd60fa9 | 742 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
743 | goto out; |
744 | } | |
745 | ||
746 | spin_lock_irq(&i2c->lock); | |
747 | ||
748 | i2c->msg = msg; | |
749 | i2c->msg_num = num; | |
750 | i2c->msg_idx = 0; | |
751 | i2c->msg_ptr = 0; | |
752 | i2c->irqlogidx = 0; | |
753 | ||
754 | i2c_pxa_start_message(i2c); | |
755 | ||
756 | spin_unlock_irq(&i2c->lock); | |
757 | ||
758 | /* | |
759 | * The rest of the processing occurs in the interrupt handler. | |
760 | */ | |
761 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 762 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
763 | |
764 | /* | |
765 | * We place the return code in i2c->msg_idx. | |
766 | */ | |
767 | ret = i2c->msg_idx; | |
768 | ||
93c92cfd | 769 | if (!timeout && i2c->msg_num) { |
b652b438 | 770 | i2c_pxa_scream_blue_murder(i2c, "timeout"); |
93c92cfd SAS |
771 | ret = I2C_RETRY; |
772 | } | |
b652b438 RK |
773 | |
774 | out: | |
775 | return ret; | |
776 | } | |
777 | ||
b7a36701 MR |
778 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
779 | struct i2c_msg msgs[], int num) | |
780 | { | |
781 | struct pxa_i2c *i2c = adap->algo_data; | |
782 | int ret, i; | |
783 | ||
784 | /* If the I2C controller is disabled we need to reset it | |
785 | (probably due to a suspend/resume destroying state). We do | |
786 | this here as we can then avoid worrying about resuming the | |
787 | controller before its users. */ | |
788 | if (!(readl(_ICR(i2c)) & ICR_IUE)) | |
789 | i2c_pxa_reset(i2c); | |
790 | ||
791 | for (i = adap->retries; i >= 0; i--) { | |
792 | ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); | |
793 | if (ret != I2C_RETRY) | |
794 | goto out; | |
795 | ||
796 | if (i2c_debug) | |
797 | dev_dbg(&adap->dev, "Retrying transmission\n"); | |
798 | udelay(100); | |
799 | } | |
800 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
801 | ret = -EREMOTEIO; | |
802 | out: | |
803 | i2c_pxa_set_slave(i2c, ret); | |
804 | return ret; | |
805 | } | |
806 | ||
b652b438 RK |
807 | /* |
808 | * i2c_pxa_master_complete - complete the message and wake up. | |
809 | */ | |
810 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
811 | { | |
812 | i2c->msg_ptr = 0; | |
813 | i2c->msg = NULL; | |
814 | i2c->msg_idx ++; | |
815 | i2c->msg_num = 0; | |
816 | if (ret) | |
817 | i2c->msg_idx = ret; | |
b7a36701 MR |
818 | if (!i2c->use_pio) |
819 | wake_up(&i2c->wait); | |
b652b438 RK |
820 | } |
821 | ||
822 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
823 | { | |
a7b4e550 | 824 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
825 | |
826 | again: | |
827 | /* | |
828 | * If ISR_ALD is set, we lost arbitration. | |
829 | */ | |
830 | if (isr & ISR_ALD) { | |
831 | /* | |
832 | * Do we need to do anything here? The PXA docs | |
833 | * are vague about what happens. | |
834 | */ | |
835 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
836 | ||
837 | /* | |
838 | * We ignore this error. We seem to see spurious ALDs | |
839 | * for seemingly no reason. If we handle them as I think | |
840 | * they should, we end up causing an I2C error, which | |
841 | * is painful for some systems. | |
842 | */ | |
843 | return; /* ignore */ | |
844 | } | |
845 | ||
846 | if (isr & ISR_BED) { | |
847 | int ret = BUS_ERROR; | |
848 | ||
849 | /* | |
850 | * I2C bus error - either the device NAK'd us, or | |
851 | * something more serious happened. If we were NAK'd | |
852 | * on the initial address phase, we can retry. | |
853 | */ | |
854 | if (isr & ISR_ACKNAK) { | |
855 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
856 | ret = I2C_RETRY; | |
857 | else | |
858 | ret = XFER_NAKED; | |
859 | } | |
860 | i2c_pxa_master_complete(i2c, ret); | |
861 | } else if (isr & ISR_RWM) { | |
862 | /* | |
863 | * Read mode. We have just sent the address byte, and | |
864 | * now we must initiate the transfer. | |
865 | */ | |
866 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
867 | i2c->msg_idx == i2c->msg_num - 1) | |
868 | icr |= ICR_STOP | ICR_ACKNAK; | |
869 | ||
870 | icr |= ICR_ALDIE | ICR_TB; | |
871 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
872 | /* | |
873 | * Write mode. Write the next data byte. | |
874 | */ | |
a7b4e550 | 875 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
876 | |
877 | icr |= ICR_ALDIE | ICR_TB; | |
878 | ||
879 | /* | |
880 | * If this is the last byte of the last message, send | |
881 | * a STOP. | |
882 | */ | |
883 | if (i2c->msg_ptr == i2c->msg->len && | |
884 | i2c->msg_idx == i2c->msg_num - 1) | |
885 | icr |= ICR_STOP; | |
886 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
887 | /* | |
888 | * Next segment of the message. | |
889 | */ | |
890 | i2c->msg_ptr = 0; | |
891 | i2c->msg_idx ++; | |
892 | i2c->msg++; | |
893 | ||
894 | /* | |
895 | * If we aren't doing a repeated start and address, | |
896 | * go back and try to send the next byte. Note that | |
897 | * we do not support switching the R/W direction here. | |
898 | */ | |
899 | if (i2c->msg->flags & I2C_M_NOSTART) | |
900 | goto again; | |
901 | ||
902 | /* | |
903 | * Write the next address. | |
904 | */ | |
a7b4e550 | 905 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
906 | |
907 | /* | |
908 | * And trigger a repeated start, and send the byte. | |
909 | */ | |
910 | icr &= ~ICR_ALDIE; | |
911 | icr |= ICR_START | ICR_TB; | |
912 | } else { | |
913 | if (i2c->msg->len == 0) { | |
914 | /* | |
915 | * Device probes have a message length of zero | |
916 | * and need the bus to be reset before it can | |
917 | * be used again. | |
918 | */ | |
919 | i2c_pxa_reset(i2c); | |
920 | } | |
921 | i2c_pxa_master_complete(i2c, 0); | |
922 | } | |
923 | ||
924 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
925 | ||
a7b4e550 | 926 | writel(icr, _ICR(i2c)); |
b652b438 RK |
927 | show_state(i2c); |
928 | } | |
929 | ||
930 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
931 | { | |
a7b4e550 | 932 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
933 | |
934 | /* | |
935 | * Read the byte. | |
936 | */ | |
a7b4e550 | 937 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
938 | |
939 | if (i2c->msg_ptr < i2c->msg->len) { | |
940 | /* | |
941 | * If this is the last byte of the last | |
942 | * message, send a STOP. | |
943 | */ | |
944 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
945 | icr |= ICR_STOP | ICR_ACKNAK; | |
946 | ||
947 | icr |= ICR_ALDIE | ICR_TB; | |
948 | } else { | |
949 | i2c_pxa_master_complete(i2c, 0); | |
950 | } | |
951 | ||
952 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
953 | ||
a7b4e550 | 954 | writel(icr, _ICR(i2c)); |
b652b438 RK |
955 | } |
956 | ||
c66dc529 SAS |
957 | #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ |
958 | ISR_SAD | ISR_BED) | |
7d12e780 | 959 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
960 | { |
961 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 962 | u32 isr = readl(_ISR(i2c)); |
b652b438 | 963 | |
97491ba3 | 964 | if (!(isr & VALID_INT_SOURCE)) |
c66dc529 SAS |
965 | return IRQ_NONE; |
966 | ||
b652b438 | 967 | if (i2c_debug > 2 && 0) { |
6fd60fa9 | 968 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 969 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
970 | decode_ISR(isr); |
971 | } | |
972 | ||
7e3d7db5 | 973 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
974 | i2c->isrlog[i2c->irqlogidx++] = isr; |
975 | ||
976 | show_state(i2c); | |
977 | ||
978 | /* | |
979 | * Always clear all pending IRQs. | |
980 | */ | |
97491ba3 | 981 | writel(isr & VALID_INT_SOURCE, _ISR(i2c)); |
b652b438 RK |
982 | |
983 | if (isr & ISR_SAD) | |
984 | i2c_pxa_slave_start(i2c, isr); | |
985 | if (isr & ISR_SSD) | |
986 | i2c_pxa_slave_stop(i2c); | |
987 | ||
988 | if (i2c_pxa_is_slavemode(i2c)) { | |
989 | if (isr & ISR_ITE) | |
990 | i2c_pxa_slave_txempty(i2c, isr); | |
991 | if (isr & ISR_IRF) | |
992 | i2c_pxa_slave_rxfull(i2c, isr); | |
993 | } else if (i2c->msg) { | |
994 | if (isr & ISR_ITE) | |
995 | i2c_pxa_irq_txempty(i2c, isr); | |
996 | if (isr & ISR_IRF) | |
997 | i2c_pxa_irq_rxfull(i2c, isr); | |
998 | } else { | |
999 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
1000 | } | |
1001 | ||
1002 | return IRQ_HANDLED; | |
1003 | } | |
1004 | ||
1005 | ||
1006 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
1007 | { | |
1008 | struct pxa_i2c *i2c = adap->algo_data; | |
1009 | int ret, i; | |
1010 | ||
1011 | for (i = adap->retries; i >= 0; i--) { | |
1012 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
1013 | if (ret != I2C_RETRY) | |
1014 | goto out; | |
1015 | ||
1016 | if (i2c_debug) | |
6fd60fa9 | 1017 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
1018 | udelay(100); |
1019 | } | |
1020 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
1021 | ret = -EREMOTEIO; | |
1022 | out: | |
1023 | i2c_pxa_set_slave(i2c, ret); | |
1024 | return ret; | |
1025 | } | |
1026 | ||
da16e324 RK |
1027 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
1028 | { | |
1029 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
1030 | } | |
1031 | ||
8f9082c5 | 1032 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 1033 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 1034 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
1035 | }; |
1036 | ||
b7a36701 MR |
1037 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
1038 | .master_xfer = i2c_pxa_pio_xfer, | |
1039 | .functionality = i2c_pxa_functionality, | |
1040 | }; | |
1041 | ||
63fe122b HZ |
1042 | static struct of_device_id i2c_pxa_dt_ids[] = { |
1043 | { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX }, | |
1044 | { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX }, | |
1045 | { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX }, | |
1046 | {} | |
1047 | }; | |
1048 | MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); | |
1049 | ||
1050 | static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, | |
1051 | enum pxa_i2c_types *i2c_types) | |
b652b438 | 1052 | { |
63fe122b HZ |
1053 | struct device_node *np = pdev->dev.of_node; |
1054 | const struct of_device_id *of_id = | |
1055 | of_match_device(i2c_pxa_dt_ids, &pdev->dev); | |
b652b438 | 1056 | |
63fe122b HZ |
1057 | if (!of_id) |
1058 | return 1; | |
fe69c555 DA |
1059 | |
1060 | /* For device tree we always use the dynamic or alias-assigned ID */ | |
1061 | i2c->adap.nr = -1; | |
1062 | ||
63fe122b HZ |
1063 | if (of_get_property(np, "mrvl,i2c-polling", NULL)) |
1064 | i2c->use_pio = 1; | |
1065 | if (of_get_property(np, "mrvl,i2c-fast-mode", NULL)) | |
1066 | i2c->fast_mode = 1; | |
1067 | *i2c_types = (u32)(of_id->data); | |
1068 | return 0; | |
1069 | } | |
a7b4e550 | 1070 | |
63fe122b HZ |
1071 | static int i2c_pxa_probe_pdata(struct platform_device *pdev, |
1072 | struct pxa_i2c *i2c, | |
1073 | enum pxa_i2c_types *i2c_types) | |
1074 | { | |
1075 | struct i2c_pxa_platform_data *plat = pdev->dev.platform_data; | |
1076 | const struct platform_device_id *id = platform_get_device_id(pdev); | |
1077 | ||
1078 | *i2c_types = id->driver_data; | |
1079 | if (plat) { | |
1080 | i2c->use_pio = plat->use_pio; | |
1081 | i2c->fast_mode = plat->fast_mode; | |
1082 | } | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int i2c_pxa_probe(struct platform_device *dev) | |
1087 | { | |
1088 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; | |
1089 | enum pxa_i2c_types i2c_type; | |
1090 | struct pxa_i2c *i2c; | |
1091 | struct resource *res = NULL; | |
1092 | int ret, irq; | |
a7b4e550 | 1093 | |
6776f3d2 | 1094 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
1095 | if (!i2c) { |
1096 | ret = -ENOMEM; | |
1097 | goto emalloc; | |
1098 | } | |
1099 | ||
fe69c555 DA |
1100 | /* Default adapter num to device id; i2c_pxa_probe_dt can override. */ |
1101 | i2c->adap.nr = dev->id; | |
1102 | ||
63fe122b HZ |
1103 | ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type); |
1104 | if (ret > 0) | |
1105 | ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type); | |
1106 | if (ret < 0) | |
1107 | goto eclk; | |
1108 | ||
1109 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1110 | irq = platform_get_irq(dev, 0); | |
1111 | if (res == NULL || irq < 0) { | |
1112 | ret = -ENODEV; | |
1113 | goto eclk; | |
1114 | } | |
1115 | ||
1116 | if (!request_mem_region(res->start, resource_size(res), res->name)) { | |
1117 | ret = -ENOMEM; | |
1118 | goto eclk; | |
1119 | } | |
1120 | ||
6776f3d2 | 1121 | i2c->adap.owner = THIS_MODULE; |
6776f3d2 ES |
1122 | i2c->adap.retries = 5; |
1123 | ||
1124 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 1125 | init_waitqueue_head(&i2c->wait); |
6776f3d2 | 1126 | |
fe69c555 | 1127 | strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); |
a7b4e550 | 1128 | |
e0d8b13a | 1129 | i2c->clk = clk_get(&dev->dev, NULL); |
c3cef3f3 RK |
1130 | if (IS_ERR(i2c->clk)) { |
1131 | ret = PTR_ERR(i2c->clk); | |
1132 | goto eclk; | |
1133 | } | |
1134 | ||
c6ffddea | 1135 | i2c->reg_base = ioremap(res->start, resource_size(res)); |
a7b4e550 GL |
1136 | if (!i2c->reg_base) { |
1137 | ret = -EIO; | |
1138 | goto eremap; | |
1139 | } | |
d6668c7c SAS |
1140 | |
1141 | i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; | |
1142 | i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; | |
1143 | i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; | |
1144 | i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; | |
7e94dd15 SAS |
1145 | if (i2c_type != REGS_CE4100) |
1146 | i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; | |
a7b4e550 GL |
1147 | |
1148 | i2c->iobase = res->start; | |
c6ffddea | 1149 | i2c->iosize = resource_size(res); |
a7b4e550 GL |
1150 | |
1151 | i2c->irq = irq; | |
b652b438 RK |
1152 | |
1153 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
1154 | ||
b652b438 | 1155 | if (plat) { |
63fe122b | 1156 | #ifdef CONFIG_I2C_PXA_SLAVE |
b652b438 | 1157 | i2c->slave_addr = plat->slave_addr; |
beea494d | 1158 | i2c->slave = plat->slave; |
b652b438 | 1159 | #endif |
b7a36701 | 1160 | i2c->adap.class = plat->class; |
b7a36701 MR |
1161 | } |
1162 | ||
7a10f473 | 1163 | clk_prepare_enable(i2c->clk); |
63fe122b | 1164 | |
b7a36701 MR |
1165 | if (i2c->use_pio) { |
1166 | i2c->adap.algo = &i2c_pxa_pio_algorithm; | |
1167 | } else { | |
1168 | i2c->adap.algo = &i2c_pxa_algorithm; | |
c66dc529 | 1169 | ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED, |
fe69c555 | 1170 | dev_name(&dev->dev), i2c); |
b7a36701 MR |
1171 | if (ret) |
1172 | goto ereqirq; | |
1173 | } | |
a7b4e550 | 1174 | |
b652b438 RK |
1175 | i2c_pxa_reset(i2c); |
1176 | ||
1177 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1178 | i2c->adap.dev.parent = &dev->dev; |
baa8cab0 SAS |
1179 | #ifdef CONFIG_OF |
1180 | i2c->adap.dev.of_node = dev->dev.of_node; | |
1181 | #endif | |
b652b438 | 1182 | |
488bf314 | 1183 | ret = i2c_add_numbered_adapter(&i2c->adap); |
b652b438 RK |
1184 | if (ret < 0) { |
1185 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 1186 | goto eadapt; |
b652b438 | 1187 | } |
baa8cab0 | 1188 | of_i2c_register_devices(&i2c->adap); |
b652b438 | 1189 | |
3ae5eaec | 1190 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
1191 | |
1192 | #ifdef CONFIG_I2C_PXA_SLAVE | |
1193 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
22e965c2 | 1194 | dev_name(&i2c->adap.dev), i2c->slave_addr); |
b652b438 RK |
1195 | #else |
1196 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
22e965c2 | 1197 | dev_name(&i2c->adap.dev)); |
b652b438 RK |
1198 | #endif |
1199 | return 0; | |
1200 | ||
a7b4e550 | 1201 | eadapt: |
b7a36701 MR |
1202 | if (!i2c->use_pio) |
1203 | free_irq(irq, i2c); | |
a7b4e550 | 1204 | ereqirq: |
7a10f473 | 1205 | clk_disable_unprepare(i2c->clk); |
a92b36ed | 1206 | iounmap(i2c->reg_base); |
a7b4e550 | 1207 | eremap: |
c3cef3f3 RK |
1208 | clk_put(i2c->clk); |
1209 | eclk: | |
a7b4e550 GL |
1210 | kfree(i2c); |
1211 | emalloc: | |
c6ffddea | 1212 | release_mem_region(res->start, resource_size(res)); |
b652b438 RK |
1213 | return ret; |
1214 | } | |
1215 | ||
0a6d2246 | 1216 | static int i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 1217 | { |
3ae5eaec | 1218 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 1219 | |
b652b438 | 1220 | i2c_del_adapter(&i2c->adap); |
b7a36701 MR |
1221 | if (!i2c->use_pio) |
1222 | free_irq(i2c->irq, i2c); | |
c3cef3f3 | 1223 | |
7a10f473 | 1224 | clk_disable_unprepare(i2c->clk); |
c3cef3f3 | 1225 | clk_put(i2c->clk); |
c3cef3f3 | 1226 | |
a92b36ed | 1227 | iounmap(i2c->reg_base); |
a7b4e550 GL |
1228 | release_mem_region(i2c->iobase, i2c->iosize); |
1229 | kfree(i2c); | |
b652b438 RK |
1230 | |
1231 | return 0; | |
1232 | } | |
1233 | ||
e7d48fa2 | 1234 | #ifdef CONFIG_PM |
57f4d4f1 | 1235 | static int i2c_pxa_suspend_noirq(struct device *dev) |
e7d48fa2 | 1236 | { |
57f4d4f1 MD |
1237 | struct platform_device *pdev = to_platform_device(dev); |
1238 | struct pxa_i2c *i2c = platform_get_drvdata(pdev); | |
1239 | ||
e7d48fa2 | 1240 | clk_disable(i2c->clk); |
57f4d4f1 | 1241 | |
e7d48fa2 RK |
1242 | return 0; |
1243 | } | |
1244 | ||
57f4d4f1 | 1245 | static int i2c_pxa_resume_noirq(struct device *dev) |
e7d48fa2 | 1246 | { |
57f4d4f1 MD |
1247 | struct platform_device *pdev = to_platform_device(dev); |
1248 | struct pxa_i2c *i2c = platform_get_drvdata(pdev); | |
e7d48fa2 RK |
1249 | |
1250 | clk_enable(i2c->clk); | |
1251 | i2c_pxa_reset(i2c); | |
1252 | ||
1253 | return 0; | |
1254 | } | |
57f4d4f1 | 1255 | |
47145210 | 1256 | static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { |
57f4d4f1 MD |
1257 | .suspend_noirq = i2c_pxa_suspend_noirq, |
1258 | .resume_noirq = i2c_pxa_resume_noirq, | |
1259 | }; | |
1260 | ||
1261 | #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) | |
e7d48fa2 | 1262 | #else |
57f4d4f1 | 1263 | #define I2C_PXA_DEV_PM_OPS NULL |
e7d48fa2 RK |
1264 | #endif |
1265 | ||
3ae5eaec | 1266 | static struct platform_driver i2c_pxa_driver = { |
b652b438 | 1267 | .probe = i2c_pxa_probe, |
0a6d2246 | 1268 | .remove = i2c_pxa_remove, |
3ae5eaec RK |
1269 | .driver = { |
1270 | .name = "pxa2xx-i2c", | |
a92b36ed | 1271 | .owner = THIS_MODULE, |
57f4d4f1 | 1272 | .pm = I2C_PXA_DEV_PM_OPS, |
63fe122b | 1273 | .of_match_table = i2c_pxa_dt_ids, |
3ae5eaec | 1274 | }, |
f23d4911 | 1275 | .id_table = i2c_pxa_id_table, |
b652b438 RK |
1276 | }; |
1277 | ||
1278 | static int __init i2c_adap_pxa_init(void) | |
1279 | { | |
3ae5eaec | 1280 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1281 | } |
1282 | ||
a92b36ed | 1283 | static void __exit i2c_adap_pxa_exit(void) |
b652b438 | 1284 | { |
d6a7b5f8 | 1285 | platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1286 | } |
1287 | ||
ece5f7b3 | 1288 | MODULE_LICENSE("GPL"); |
add8eda7 | 1289 | MODULE_ALIAS("platform:pxa2xx-i2c"); |
ece5f7b3 | 1290 | |
47a9b137 | 1291 | subsys_initcall(i2c_adap_pxa_init); |
b652b438 | 1292 | module_exit(i2c_adap_pxa_exit); |