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10c5a842 BA |
1 | /* |
2 | * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. | |
3 | * Copyright (c) 2014, Sony Mobile Communications AB. | |
4 | * | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 and | |
8 | * only version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
9cedf3b2 | 17 | #include <linux/atomic.h> |
10c5a842 BA |
18 | #include <linux/clk.h> |
19 | #include <linux/delay.h> | |
9cedf3b2 S |
20 | #include <linux/dmaengine.h> |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/dma-mapping.h> | |
10c5a842 BA |
23 | #include <linux/err.h> |
24 | #include <linux/i2c.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/of.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/pm_runtime.h> | |
9cedf3b2 | 31 | #include <linux/scatterlist.h> |
10c5a842 BA |
32 | |
33 | /* QUP Registers */ | |
34 | #define QUP_CONFIG 0x000 | |
35 | #define QUP_STATE 0x004 | |
36 | #define QUP_IO_MODE 0x008 | |
37 | #define QUP_SW_RESET 0x00c | |
38 | #define QUP_OPERATIONAL 0x018 | |
39 | #define QUP_ERROR_FLAGS 0x01c | |
40 | #define QUP_ERROR_FLAGS_EN 0x020 | |
9cedf3b2 | 41 | #define QUP_OPERATIONAL_MASK 0x028 |
10c5a842 BA |
42 | #define QUP_HW_VERSION 0x030 |
43 | #define QUP_MX_OUTPUT_CNT 0x100 | |
44 | #define QUP_OUT_FIFO_BASE 0x110 | |
45 | #define QUP_MX_WRITE_CNT 0x150 | |
46 | #define QUP_MX_INPUT_CNT 0x200 | |
47 | #define QUP_MX_READ_CNT 0x208 | |
48 | #define QUP_IN_FIFO_BASE 0x218 | |
49 | #define QUP_I2C_CLK_CTL 0x400 | |
50 | #define QUP_I2C_STATUS 0x404 | |
191424bb | 51 | #define QUP_I2C_MASTER_GEN 0x408 |
10c5a842 BA |
52 | |
53 | /* QUP States and reset values */ | |
54 | #define QUP_RESET_STATE 0 | |
55 | #define QUP_RUN_STATE 1 | |
56 | #define QUP_PAUSE_STATE 3 | |
57 | #define QUP_STATE_MASK 3 | |
58 | ||
59 | #define QUP_STATE_VALID BIT(2) | |
60 | #define QUP_I2C_MAST_GEN BIT(4) | |
9cedf3b2 | 61 | #define QUP_I2C_FLUSH BIT(6) |
10c5a842 BA |
62 | |
63 | #define QUP_OPERATIONAL_RESET 0x000ff0 | |
64 | #define QUP_I2C_STATUS_RESET 0xfffffc | |
65 | ||
66 | /* QUP OPERATIONAL FLAGS */ | |
67 | #define QUP_I2C_NACK_FLAG BIT(3) | |
68 | #define QUP_OUT_NOT_EMPTY BIT(4) | |
69 | #define QUP_IN_NOT_EMPTY BIT(5) | |
70 | #define QUP_OUT_FULL BIT(6) | |
71 | #define QUP_OUT_SVC_FLAG BIT(8) | |
72 | #define QUP_IN_SVC_FLAG BIT(9) | |
73 | #define QUP_MX_OUTPUT_DONE BIT(10) | |
74 | #define QUP_MX_INPUT_DONE BIT(11) | |
75 | ||
76 | /* I2C mini core related values */ | |
77 | #define QUP_CLOCK_AUTO_GATE BIT(13) | |
78 | #define I2C_MINI_CORE (2 << 8) | |
79 | #define I2C_N_VAL 15 | |
191424bb S |
80 | #define I2C_N_VAL_V2 7 |
81 | ||
10c5a842 BA |
82 | /* Most significant word offset in FIFO port */ |
83 | #define QUP_MSW_SHIFT (I2C_N_VAL + 1) | |
84 | ||
85 | /* Packing/Unpacking words in FIFOs, and IO modes */ | |
86 | #define QUP_OUTPUT_BLK_MODE (1 << 10) | |
9cedf3b2 | 87 | #define QUP_OUTPUT_BAM_MODE (3 << 10) |
10c5a842 | 88 | #define QUP_INPUT_BLK_MODE (1 << 12) |
9cedf3b2 S |
89 | #define QUP_INPUT_BAM_MODE (3 << 12) |
90 | #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE) | |
10c5a842 BA |
91 | #define QUP_UNPACK_EN BIT(14) |
92 | #define QUP_PACK_EN BIT(15) | |
93 | ||
94 | #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN) | |
191424bb | 95 | #define QUP_V2_TAGS_EN 1 |
10c5a842 BA |
96 | |
97 | #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03) | |
98 | #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07) | |
99 | #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03) | |
100 | #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07) | |
101 | ||
102 | /* QUP tags */ | |
103 | #define QUP_TAG_START (1 << 8) | |
104 | #define QUP_TAG_DATA (2 << 8) | |
105 | #define QUP_TAG_STOP (3 << 8) | |
106 | #define QUP_TAG_REC (4 << 8) | |
9cedf3b2 S |
107 | #define QUP_BAM_INPUT_EOT 0x93 |
108 | #define QUP_BAM_FLUSH_STOP 0x96 | |
10c5a842 | 109 | |
191424bb S |
110 | /* QUP v2 tags */ |
111 | #define QUP_TAG_V2_START 0x81 | |
112 | #define QUP_TAG_V2_DATAWR 0x82 | |
113 | #define QUP_TAG_V2_DATAWR_STOP 0x83 | |
114 | #define QUP_TAG_V2_DATARD 0x85 | |
115 | #define QUP_TAG_V2_DATARD_STOP 0x87 | |
116 | ||
10c5a842 BA |
117 | /* Status, Error flags */ |
118 | #define I2C_STATUS_WR_BUFFER_FULL BIT(0) | |
119 | #define I2C_STATUS_BUS_ACTIVE BIT(8) | |
120 | #define I2C_STATUS_ERROR_MASK 0x38000fc | |
121 | #define QUP_STATUS_ERROR_FLAGS 0x7c | |
122 | ||
123 | #define QUP_READ_LIMIT 256 | |
c4f0c5fb S |
124 | #define SET_BIT 0x1 |
125 | #define RESET_BIT 0x0 | |
126 | #define ONE_BYTE 0x1 | |
f7418793 | 127 | #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) |
10c5a842 | 128 | |
9cedf3b2 S |
129 | #define MX_TX_RX_LEN SZ_64K |
130 | #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT) | |
131 | ||
132 | /* Max timeout in ms for 32k bytes */ | |
133 | #define TOUT_MAX 300 | |
134 | ||
191424bb S |
135 | struct qup_i2c_block { |
136 | int count; | |
137 | int pos; | |
138 | int tx_tag_len; | |
139 | int rx_tag_len; | |
140 | int data_len; | |
141 | u8 tags[6]; | |
142 | }; | |
143 | ||
9cedf3b2 S |
144 | struct qup_i2c_tag { |
145 | u8 *start; | |
146 | dma_addr_t addr; | |
147 | }; | |
148 | ||
149 | struct qup_i2c_bam { | |
150 | struct qup_i2c_tag tag; | |
151 | struct dma_chan *dma; | |
152 | struct scatterlist *sg; | |
153 | }; | |
154 | ||
10c5a842 BA |
155 | struct qup_i2c_dev { |
156 | struct device *dev; | |
157 | void __iomem *base; | |
158 | int irq; | |
159 | struct clk *clk; | |
160 | struct clk *pclk; | |
161 | struct i2c_adapter adap; | |
162 | ||
163 | int clk_ctl; | |
164 | int out_fifo_sz; | |
165 | int in_fifo_sz; | |
166 | int out_blk_sz; | |
167 | int in_blk_sz; | |
168 | ||
169 | unsigned long one_byte_t; | |
191424bb | 170 | struct qup_i2c_block blk; |
10c5a842 BA |
171 | |
172 | struct i2c_msg *msg; | |
173 | /* Current posion in user message buffer */ | |
174 | int pos; | |
175 | /* I2C protocol errors */ | |
176 | u32 bus_err; | |
177 | /* QUP core errors */ | |
178 | u32 qup_err; | |
179 | ||
f7418793 S |
180 | /* To check if this is the last msg */ |
181 | bool is_last; | |
182 | ||
183 | /* To configure when bus is in run state */ | |
184 | int config_run; | |
185 | ||
9cedf3b2 S |
186 | /* dma parameters */ |
187 | bool is_dma; | |
188 | struct dma_pool *dpool; | |
189 | struct qup_i2c_tag start_tag; | |
190 | struct qup_i2c_bam brx; | |
191 | struct qup_i2c_bam btx; | |
192 | ||
10c5a842 BA |
193 | struct completion xfer; |
194 | }; | |
195 | ||
196 | static irqreturn_t qup_i2c_interrupt(int irq, void *dev) | |
197 | { | |
198 | struct qup_i2c_dev *qup = dev; | |
199 | u32 bus_err; | |
200 | u32 qup_err; | |
201 | u32 opflags; | |
202 | ||
203 | bus_err = readl(qup->base + QUP_I2C_STATUS); | |
204 | qup_err = readl(qup->base + QUP_ERROR_FLAGS); | |
205 | opflags = readl(qup->base + QUP_OPERATIONAL); | |
206 | ||
207 | if (!qup->msg) { | |
208 | /* Clear Error interrupt */ | |
209 | writel(QUP_RESET_STATE, qup->base + QUP_STATE); | |
210 | return IRQ_HANDLED; | |
211 | } | |
212 | ||
213 | bus_err &= I2C_STATUS_ERROR_MASK; | |
214 | qup_err &= QUP_STATUS_ERROR_FLAGS; | |
215 | ||
2b84a4dd AS |
216 | /* Clear the error bits in QUP_ERROR_FLAGS */ |
217 | if (qup_err) | |
10c5a842 | 218 | writel(qup_err, qup->base + QUP_ERROR_FLAGS); |
10c5a842 | 219 | |
2b84a4dd AS |
220 | /* Clear the error bits in QUP_I2C_STATUS */ |
221 | if (bus_err) | |
222 | writel(bus_err, qup->base + QUP_I2C_STATUS); | |
223 | ||
224 | /* Reset the QUP State in case of error */ | |
225 | if (qup_err || bus_err) { | |
10c5a842 BA |
226 | writel(QUP_RESET_STATE, qup->base + QUP_STATE); |
227 | goto done; | |
228 | } | |
229 | ||
230 | if (opflags & QUP_IN_SVC_FLAG) | |
231 | writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); | |
232 | ||
233 | if (opflags & QUP_OUT_SVC_FLAG) | |
234 | writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); | |
235 | ||
236 | done: | |
237 | qup->qup_err = qup_err; | |
238 | qup->bus_err = bus_err; | |
239 | complete(&qup->xfer); | |
240 | return IRQ_HANDLED; | |
241 | } | |
242 | ||
243 | static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, | |
244 | u32 req_state, u32 req_mask) | |
245 | { | |
246 | int retries = 1; | |
247 | u32 state; | |
248 | ||
249 | /* | |
250 | * State transition takes 3 AHB clocks cycles + 3 I2C master clock | |
251 | * cycles. So retry once after a 1uS delay. | |
252 | */ | |
253 | do { | |
254 | state = readl(qup->base + QUP_STATE); | |
255 | ||
256 | if (state & QUP_STATE_VALID && | |
257 | (state & req_mask) == req_state) | |
258 | return 0; | |
259 | ||
260 | udelay(1); | |
261 | } while (retries--); | |
262 | ||
263 | return -ETIMEDOUT; | |
264 | } | |
265 | ||
266 | static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) | |
267 | { | |
268 | return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); | |
269 | } | |
270 | ||
9cedf3b2 S |
271 | static void qup_i2c_flush(struct qup_i2c_dev *qup) |
272 | { | |
273 | u32 val = readl(qup->base + QUP_STATE); | |
274 | ||
275 | val |= QUP_I2C_FLUSH; | |
276 | writel(val, qup->base + QUP_STATE); | |
277 | } | |
278 | ||
10c5a842 BA |
279 | static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) |
280 | { | |
281 | return qup_i2c_poll_state_mask(qup, 0, 0); | |
282 | } | |
283 | ||
284 | static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) | |
285 | { | |
286 | return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); | |
287 | } | |
288 | ||
289 | static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) | |
290 | { | |
291 | if (qup_i2c_poll_state_valid(qup) != 0) | |
292 | return -EIO; | |
293 | ||
294 | writel(state, qup->base + QUP_STATE); | |
295 | ||
296 | if (qup_i2c_poll_state(qup, state) != 0) | |
297 | return -EIO; | |
298 | return 0; | |
299 | } | |
300 | ||
c4f0c5fb S |
301 | /** |
302 | * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path | |
303 | * @qup: The qup_i2c_dev device | |
304 | * @op: The bit/event to wait on | |
305 | * @val: value of the bit to wait on, 0 or 1 | |
306 | * @len: The length the bytes to be transferred | |
307 | */ | |
308 | static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val, | |
309 | int len) | |
10c5a842 BA |
310 | { |
311 | unsigned long timeout; | |
312 | u32 opflags; | |
313 | u32 status; | |
c4f0c5fb | 314 | u32 shift = __ffs(op); |
fbf9921f | 315 | int ret = 0; |
10c5a842 | 316 | |
c4f0c5fb S |
317 | len *= qup->one_byte_t; |
318 | /* timeout after a wait of twice the max time */ | |
319 | timeout = jiffies + len * 4; | |
10c5a842 BA |
320 | |
321 | for (;;) { | |
322 | opflags = readl(qup->base + QUP_OPERATIONAL); | |
323 | status = readl(qup->base + QUP_I2C_STATUS); | |
324 | ||
c4f0c5fb | 325 | if (((opflags & op) >> shift) == val) { |
f7418793 | 326 | if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) { |
fbf9921f S |
327 | if (!(status & I2C_STATUS_BUS_ACTIVE)) { |
328 | ret = 0; | |
329 | goto done; | |
330 | } | |
c4f0c5fb | 331 | } else { |
fbf9921f S |
332 | ret = 0; |
333 | goto done; | |
c4f0c5fb S |
334 | } |
335 | } | |
10c5a842 | 336 | |
fbf9921f S |
337 | if (time_after(jiffies, timeout)) { |
338 | ret = -ETIMEDOUT; | |
339 | goto done; | |
340 | } | |
c4f0c5fb | 341 | usleep_range(len, len * 2); |
10c5a842 | 342 | } |
fbf9921f S |
343 | |
344 | done: | |
345 | if (qup->bus_err || qup->qup_err) | |
346 | ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; | |
347 | ||
348 | return ret; | |
10c5a842 BA |
349 | } |
350 | ||
191424bb S |
351 | static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup, |
352 | struct i2c_msg *msg) | |
353 | { | |
354 | /* Number of entries to shift out, including the tags */ | |
355 | int total = msg->len + qup->blk.tx_tag_len; | |
356 | ||
f7418793 S |
357 | total |= qup->config_run; |
358 | ||
191424bb S |
359 | if (total < qup->out_fifo_sz) { |
360 | /* FIFO mode */ | |
361 | writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); | |
362 | writel(total, qup->base + QUP_MX_WRITE_CNT); | |
363 | } else { | |
364 | /* BLOCK mode (transfer data on chunks) */ | |
365 | writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN, | |
366 | qup->base + QUP_IO_MODE); | |
367 | writel(total, qup->base + QUP_MX_OUTPUT_CNT); | |
368 | } | |
369 | } | |
370 | ||
10c5a842 BA |
371 | static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg) |
372 | { | |
373 | /* Number of entries to shift out, including the start */ | |
374 | int total = msg->len + 1; | |
375 | ||
376 | if (total < qup->out_fifo_sz) { | |
377 | /* FIFO mode */ | |
378 | writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); | |
379 | writel(total, qup->base + QUP_MX_WRITE_CNT); | |
380 | } else { | |
381 | /* BLOCK mode (transfer data on chunks) */ | |
382 | writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN, | |
383 | qup->base + QUP_IO_MODE); | |
384 | writel(total, qup->base + QUP_MX_OUTPUT_CNT); | |
385 | } | |
386 | } | |
387 | ||
52db223e S |
388 | static int check_for_fifo_space(struct qup_i2c_dev *qup) |
389 | { | |
390 | int ret; | |
391 | ||
392 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
393 | if (ret) | |
394 | goto out; | |
395 | ||
396 | ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL, | |
397 | RESET_BIT, 4 * ONE_BYTE); | |
398 | if (ret) { | |
399 | /* Fifo is full. Drain out the fifo */ | |
400 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
401 | if (ret) | |
402 | goto out; | |
403 | ||
404 | ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, | |
405 | RESET_BIT, 256 * ONE_BYTE); | |
406 | if (ret) { | |
407 | dev_err(qup->dev, "timeout for fifo out full"); | |
408 | goto out; | |
409 | } | |
410 | ||
411 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
412 | if (ret) | |
413 | goto out; | |
414 | } | |
415 | ||
416 | out: | |
417 | return ret; | |
418 | } | |
419 | ||
c4f0c5fb | 420 | static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg) |
10c5a842 BA |
421 | { |
422 | u32 addr = msg->addr << 1; | |
423 | u32 qup_tag; | |
10c5a842 BA |
424 | int idx; |
425 | u32 val; | |
c4f0c5fb | 426 | int ret = 0; |
10c5a842 BA |
427 | |
428 | if (qup->pos == 0) { | |
429 | val = QUP_TAG_START | addr; | |
430 | idx = 1; | |
431 | } else { | |
432 | val = 0; | |
433 | idx = 0; | |
434 | } | |
435 | ||
436 | while (qup->pos < msg->len) { | |
437 | /* Check that there's space in the FIFO for our pair */ | |
52db223e | 438 | ret = check_for_fifo_space(qup); |
c4f0c5fb S |
439 | if (ret) |
440 | return ret; | |
10c5a842 BA |
441 | |
442 | if (qup->pos == msg->len - 1) | |
443 | qup_tag = QUP_TAG_STOP; | |
444 | else | |
445 | qup_tag = QUP_TAG_DATA; | |
446 | ||
447 | if (idx & 1) | |
448 | val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; | |
449 | else | |
450 | val = qup_tag | msg->buf[qup->pos]; | |
451 | ||
452 | /* Write out the pair and the last odd value */ | |
453 | if (idx & 1 || qup->pos == msg->len - 1) | |
454 | writel(val, qup->base + QUP_OUT_FIFO_BASE); | |
455 | ||
456 | qup->pos++; | |
457 | idx++; | |
458 | } | |
c4f0c5fb | 459 | |
52db223e S |
460 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); |
461 | ||
c4f0c5fb | 462 | return ret; |
10c5a842 BA |
463 | } |
464 | ||
191424bb S |
465 | static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, |
466 | struct i2c_msg *msg) | |
467 | { | |
468 | memset(&qup->blk, 0, sizeof(qup->blk)); | |
469 | ||
470 | qup->blk.data_len = msg->len; | |
471 | qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT; | |
472 | ||
473 | /* 4 bytes for first block and 2 writes for rest */ | |
474 | qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2; | |
475 | ||
476 | /* There are 2 tag bytes that are read in to fifo for every block */ | |
477 | if (msg->flags & I2C_M_RD) | |
478 | qup->blk.rx_tag_len = qup->blk.count * 2; | |
479 | } | |
480 | ||
481 | static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf, | |
482 | int dlen, u8 *dbuf) | |
483 | { | |
484 | u32 val = 0, idx = 0, pos = 0, i = 0, t; | |
485 | int len = tlen + dlen; | |
486 | u8 *buf = tbuf; | |
487 | int ret = 0; | |
488 | ||
489 | while (len > 0) { | |
52db223e S |
490 | ret = check_for_fifo_space(qup); |
491 | if (ret) | |
191424bb | 492 | return ret; |
191424bb S |
493 | |
494 | t = (len >= 4) ? 4 : len; | |
495 | ||
496 | while (idx < t) { | |
497 | if (!i && (pos >= tlen)) { | |
498 | buf = dbuf; | |
499 | pos = 0; | |
500 | i = 1; | |
501 | } | |
502 | val |= buf[pos++] << (idx++ * 8); | |
503 | } | |
504 | ||
505 | writel(val, qup->base + QUP_OUT_FIFO_BASE); | |
506 | idx = 0; | |
507 | val = 0; | |
508 | len -= 4; | |
509 | } | |
510 | ||
52db223e S |
511 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); |
512 | ||
191424bb S |
513 | return ret; |
514 | } | |
515 | ||
516 | static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) | |
517 | { | |
518 | int data_len; | |
519 | ||
520 | if (qup->blk.data_len > QUP_READ_LIMIT) | |
521 | data_len = QUP_READ_LIMIT; | |
522 | else | |
523 | data_len = qup->blk.data_len; | |
524 | ||
525 | return data_len; | |
526 | } | |
527 | ||
528 | static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, | |
9cedf3b2 | 529 | struct i2c_msg *msg, int is_dma) |
191424bb | 530 | { |
e3c60f3d | 531 | u16 addr = i2c_8bit_addr_from_msg(msg); |
191424bb S |
532 | int len = 0; |
533 | int data_len; | |
534 | ||
9cedf3b2 S |
535 | int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); |
536 | ||
191424bb S |
537 | if (qup->blk.pos == 0) { |
538 | tags[len++] = QUP_TAG_V2_START; | |
539 | tags[len++] = addr & 0xff; | |
540 | ||
541 | if (msg->flags & I2C_M_TEN) | |
542 | tags[len++] = addr >> 8; | |
543 | } | |
544 | ||
545 | /* Send _STOP commands for the last block */ | |
9cedf3b2 | 546 | if (last) { |
191424bb S |
547 | if (msg->flags & I2C_M_RD) |
548 | tags[len++] = QUP_TAG_V2_DATARD_STOP; | |
549 | else | |
550 | tags[len++] = QUP_TAG_V2_DATAWR_STOP; | |
551 | } else { | |
552 | if (msg->flags & I2C_M_RD) | |
553 | tags[len++] = QUP_TAG_V2_DATARD; | |
554 | else | |
555 | tags[len++] = QUP_TAG_V2_DATAWR; | |
556 | } | |
557 | ||
558 | data_len = qup_i2c_get_data_len(qup); | |
559 | ||
560 | /* 0 implies 256 bytes */ | |
561 | if (data_len == QUP_READ_LIMIT) | |
562 | tags[len++] = 0; | |
563 | else | |
564 | tags[len++] = data_len; | |
565 | ||
9cedf3b2 S |
566 | if ((msg->flags & I2C_M_RD) && last && is_dma) { |
567 | tags[len++] = QUP_BAM_INPUT_EOT; | |
568 | tags[len++] = QUP_BAM_FLUSH_STOP; | |
569 | } | |
570 | ||
191424bb S |
571 | return len; |
572 | } | |
573 | ||
574 | static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg) | |
575 | { | |
576 | int data_len = 0, tag_len, index; | |
577 | int ret; | |
578 | ||
9cedf3b2 | 579 | tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0); |
191424bb S |
580 | index = msg->len - qup->blk.data_len; |
581 | ||
582 | /* only tags are written for read */ | |
583 | if (!(msg->flags & I2C_M_RD)) | |
584 | data_len = qup_i2c_get_data_len(qup); | |
585 | ||
586 | ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags, | |
587 | data_len, &msg->buf[index]); | |
588 | qup->blk.data_len -= data_len; | |
589 | ||
590 | return ret; | |
591 | } | |
592 | ||
9cedf3b2 S |
593 | static void qup_i2c_bam_cb(void *data) |
594 | { | |
595 | struct qup_i2c_dev *qup = data; | |
596 | ||
597 | complete(&qup->xfer); | |
598 | } | |
599 | ||
600 | static int qup_sg_set_buf(struct scatterlist *sg, void *buf, | |
685983f4 S |
601 | unsigned int buflen, struct qup_i2c_dev *qup, |
602 | int dir) | |
9cedf3b2 S |
603 | { |
604 | int ret; | |
605 | ||
606 | sg_set_buf(sg, buf, buflen); | |
607 | ret = dma_map_sg(qup->dev, sg, 1, dir); | |
608 | if (!ret) | |
609 | return -EINVAL; | |
610 | ||
9cedf3b2 S |
611 | return 0; |
612 | } | |
613 | ||
614 | static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) | |
615 | { | |
616 | if (qup->btx.dma) | |
617 | dma_release_channel(qup->btx.dma); | |
618 | if (qup->brx.dma) | |
619 | dma_release_channel(qup->brx.dma); | |
620 | qup->btx.dma = NULL; | |
621 | qup->brx.dma = NULL; | |
622 | } | |
623 | ||
624 | static int qup_i2c_req_dma(struct qup_i2c_dev *qup) | |
625 | { | |
626 | int err; | |
627 | ||
628 | if (!qup->btx.dma) { | |
629 | qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx"); | |
630 | if (IS_ERR(qup->btx.dma)) { | |
631 | err = PTR_ERR(qup->btx.dma); | |
632 | qup->btx.dma = NULL; | |
633 | dev_err(qup->dev, "\n tx channel not available"); | |
634 | return err; | |
635 | } | |
636 | } | |
637 | ||
638 | if (!qup->brx.dma) { | |
639 | qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx"); | |
640 | if (IS_ERR(qup->brx.dma)) { | |
641 | dev_err(qup->dev, "\n rx channel not available"); | |
642 | err = PTR_ERR(qup->brx.dma); | |
643 | qup->brx.dma = NULL; | |
644 | qup_i2c_rel_dma(qup); | |
645 | return err; | |
646 | } | |
647 | } | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg, | |
652 | int num) | |
653 | { | |
654 | struct dma_async_tx_descriptor *txd, *rxd = NULL; | |
655 | int ret = 0, idx = 0, limit = QUP_READ_LIMIT; | |
656 | dma_cookie_t cookie_rx, cookie_tx; | |
657 | u32 rx_nents = 0, tx_nents = 0, len, blocks, rem; | |
658 | u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0; | |
659 | u8 *tags; | |
660 | ||
661 | while (idx < num) { | |
9cedf3b2 S |
662 | tx_len = 0, len = 0, i = 0; |
663 | ||
664 | qup->is_last = (idx == (num - 1)); | |
665 | ||
666 | qup_i2c_set_blk_data(qup, msg); | |
667 | ||
5c135e15 AS |
668 | blocks = qup->blk.count; |
669 | rem = msg->len - (blocks - 1) * limit; | |
670 | ||
9cedf3b2 S |
671 | if (msg->flags & I2C_M_RD) { |
672 | rx_nents += (blocks * 2) + 1; | |
673 | tx_nents += 1; | |
674 | ||
675 | while (qup->blk.pos < blocks) { | |
5c135e15 | 676 | tlen = (i == (blocks - 1)) ? rem : limit; |
9cedf3b2 S |
677 | tags = &qup->start_tag.start[off + len]; |
678 | len += qup_i2c_set_tags(tags, qup, msg, 1); | |
5c135e15 | 679 | qup->blk.data_len -= tlen; |
9cedf3b2 S |
680 | |
681 | /* scratch buf to read the start and len tags */ | |
682 | ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++], | |
683 | &qup->brx.tag.start[0], | |
685983f4 | 684 | 2, qup, DMA_FROM_DEVICE); |
9cedf3b2 S |
685 | |
686 | if (ret) | |
687 | return ret; | |
688 | ||
689 | ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++], | |
690 | &msg->buf[limit * i], | |
685983f4 S |
691 | tlen, qup, |
692 | DMA_FROM_DEVICE); | |
9cedf3b2 S |
693 | if (ret) |
694 | return ret; | |
695 | ||
696 | i++; | |
697 | qup->blk.pos = i; | |
698 | } | |
699 | ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++], | |
700 | &qup->start_tag.start[off], | |
685983f4 | 701 | len, qup, DMA_TO_DEVICE); |
9cedf3b2 S |
702 | if (ret) |
703 | return ret; | |
704 | ||
705 | off += len; | |
706 | /* scratch buf to read the BAM EOT and FLUSH tags */ | |
707 | ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++], | |
708 | &qup->brx.tag.start[0], | |
685983f4 | 709 | 2, qup, DMA_FROM_DEVICE); |
9cedf3b2 S |
710 | if (ret) |
711 | return ret; | |
712 | } else { | |
713 | tx_nents += (blocks * 2); | |
714 | ||
715 | while (qup->blk.pos < blocks) { | |
5c135e15 | 716 | tlen = (i == (blocks - 1)) ? rem : limit; |
9cedf3b2 S |
717 | tags = &qup->start_tag.start[off + tx_len]; |
718 | len = qup_i2c_set_tags(tags, qup, msg, 1); | |
5c135e15 | 719 | qup->blk.data_len -= tlen; |
9cedf3b2 S |
720 | |
721 | ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++], | |
685983f4 S |
722 | tags, len, |
723 | qup, DMA_TO_DEVICE); | |
9cedf3b2 S |
724 | if (ret) |
725 | return ret; | |
726 | ||
727 | tx_len += len; | |
728 | ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++], | |
729 | &msg->buf[limit * i], | |
685983f4 | 730 | tlen, qup, DMA_TO_DEVICE); |
9cedf3b2 S |
731 | if (ret) |
732 | return ret; | |
733 | i++; | |
734 | qup->blk.pos = i; | |
735 | } | |
736 | off += tx_len; | |
737 | ||
738 | if (idx == (num - 1)) { | |
739 | len = 1; | |
740 | if (rx_nents) { | |
741 | qup->btx.tag.start[0] = | |
742 | QUP_BAM_INPUT_EOT; | |
743 | len++; | |
744 | } | |
745 | qup->btx.tag.start[len - 1] = | |
746 | QUP_BAM_FLUSH_STOP; | |
747 | ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++], | |
748 | &qup->btx.tag.start[0], | |
685983f4 | 749 | len, qup, DMA_TO_DEVICE); |
9cedf3b2 S |
750 | if (ret) |
751 | return ret; | |
752 | tx_nents += 1; | |
753 | } | |
754 | } | |
755 | idx++; | |
756 | msg++; | |
757 | } | |
758 | ||
759 | txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents, | |
760 | DMA_MEM_TO_DEV, | |
761 | DMA_PREP_INTERRUPT | DMA_PREP_FENCE); | |
762 | if (!txd) { | |
763 | dev_err(qup->dev, "failed to get tx desc\n"); | |
764 | ret = -EINVAL; | |
765 | goto desc_err; | |
766 | } | |
767 | ||
768 | if (!rx_nents) { | |
769 | txd->callback = qup_i2c_bam_cb; | |
770 | txd->callback_param = qup; | |
771 | } | |
772 | ||
773 | cookie_tx = dmaengine_submit(txd); | |
774 | if (dma_submit_error(cookie_tx)) { | |
775 | ret = -EINVAL; | |
776 | goto desc_err; | |
777 | } | |
778 | ||
779 | dma_async_issue_pending(qup->btx.dma); | |
780 | ||
781 | if (rx_nents) { | |
782 | rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, | |
783 | rx_nents, DMA_DEV_TO_MEM, | |
784 | DMA_PREP_INTERRUPT); | |
785 | if (!rxd) { | |
786 | dev_err(qup->dev, "failed to get rx desc\n"); | |
787 | ret = -EINVAL; | |
788 | ||
789 | /* abort TX descriptors */ | |
790 | dmaengine_terminate_all(qup->btx.dma); | |
791 | goto desc_err; | |
792 | } | |
793 | ||
794 | rxd->callback = qup_i2c_bam_cb; | |
795 | rxd->callback_param = qup; | |
796 | cookie_rx = dmaengine_submit(rxd); | |
797 | if (dma_submit_error(cookie_rx)) { | |
798 | ret = -EINVAL; | |
799 | goto desc_err; | |
800 | } | |
801 | ||
802 | dma_async_issue_pending(qup->brx.dma); | |
803 | } | |
804 | ||
805 | if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) { | |
806 | dev_err(qup->dev, "normal trans timed out\n"); | |
807 | ret = -ETIMEDOUT; | |
808 | } | |
809 | ||
810 | if (ret || qup->bus_err || qup->qup_err) { | |
fbf9921f S |
811 | if (qup_i2c_change_state(qup, QUP_RUN_STATE)) { |
812 | dev_err(qup->dev, "change to run state timed out"); | |
813 | goto desc_err; | |
814 | } | |
9cedf3b2 | 815 | |
fbf9921f S |
816 | if (rx_nents) |
817 | writel(QUP_BAM_INPUT_EOT, | |
818 | qup->base + QUP_OUT_FIFO_BASE); | |
9cedf3b2 | 819 | |
fbf9921f | 820 | writel(QUP_BAM_FLUSH_STOP, qup->base + QUP_OUT_FIFO_BASE); |
9cedf3b2 | 821 | |
fbf9921f | 822 | qup_i2c_flush(qup); |
9cedf3b2 | 823 | |
fbf9921f S |
824 | /* wait for remaining interrupts to occur */ |
825 | if (!wait_for_completion_timeout(&qup->xfer, HZ)) | |
826 | dev_err(qup->dev, "flush timed out\n"); | |
9cedf3b2 | 827 | |
fbf9921f | 828 | qup_i2c_rel_dma(qup); |
9cedf3b2 | 829 | |
fbf9921f | 830 | ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; |
9cedf3b2 S |
831 | } |
832 | ||
fbf9921f | 833 | desc_err: |
9cedf3b2 S |
834 | dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE); |
835 | ||
836 | if (rx_nents) | |
837 | dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents, | |
838 | DMA_FROM_DEVICE); | |
fbf9921f | 839 | |
9cedf3b2 S |
840 | return ret; |
841 | } | |
842 | ||
843 | static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, | |
844 | int num) | |
845 | { | |
846 | struct qup_i2c_dev *qup = i2c_get_adapdata(adap); | |
847 | int ret = 0; | |
848 | ||
849 | enable_irq(qup->irq); | |
850 | ret = qup_i2c_req_dma(qup); | |
851 | ||
852 | if (ret) | |
853 | goto out; | |
854 | ||
9cedf3b2 S |
855 | writel(0, qup->base + QUP_MX_INPUT_CNT); |
856 | writel(0, qup->base + QUP_MX_OUTPUT_CNT); | |
857 | ||
858 | /* set BAM mode */ | |
859 | writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); | |
860 | ||
861 | /* mask fifo irqs */ | |
862 | writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); | |
863 | ||
864 | /* set RUN STATE */ | |
865 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
866 | if (ret) | |
867 | goto out; | |
868 | ||
869 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
870 | ||
871 | qup->msg = msg; | |
872 | ret = qup_i2c_bam_do_xfer(qup, qup->msg, num); | |
873 | out: | |
874 | disable_irq(qup->irq); | |
875 | ||
876 | qup->msg = NULL; | |
877 | return ret; | |
878 | } | |
879 | ||
191424bb S |
880 | static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, |
881 | struct i2c_msg *msg) | |
10c5a842 BA |
882 | { |
883 | unsigned long left; | |
191424bb S |
884 | int ret = 0; |
885 | ||
886 | left = wait_for_completion_timeout(&qup->xfer, HZ); | |
887 | if (!left) { | |
888 | writel(1, qup->base + QUP_SW_RESET); | |
889 | ret = -ETIMEDOUT; | |
890 | } | |
891 | ||
fbf9921f S |
892 | if (qup->bus_err || qup->qup_err) |
893 | ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; | |
191424bb S |
894 | |
895 | return ret; | |
896 | } | |
897 | ||
898 | static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg) | |
899 | { | |
900 | int ret = 0; | |
901 | ||
902 | qup->msg = msg; | |
903 | qup->pos = 0; | |
904 | enable_irq(qup->irq); | |
905 | qup_i2c_set_blk_data(qup, msg); | |
906 | qup_i2c_set_write_mode_v2(qup, msg); | |
907 | ||
908 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
909 | if (ret) | |
910 | goto err; | |
911 | ||
912 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
913 | ||
914 | do { | |
915 | ret = qup_i2c_issue_xfer_v2(qup, msg); | |
916 | if (ret) | |
917 | goto err; | |
918 | ||
919 | ret = qup_i2c_wait_for_complete(qup, msg); | |
920 | if (ret) | |
921 | goto err; | |
922 | ||
923 | qup->blk.pos++; | |
924 | } while (qup->blk.pos < qup->blk.count); | |
925 | ||
926 | ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE); | |
927 | ||
928 | err: | |
929 | disable_irq(qup->irq); | |
930 | qup->msg = NULL; | |
931 | ||
932 | return ret; | |
933 | } | |
934 | ||
935 | static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg) | |
936 | { | |
10c5a842 BA |
937 | int ret; |
938 | ||
939 | qup->msg = msg; | |
940 | qup->pos = 0; | |
941 | ||
942 | enable_irq(qup->irq); | |
943 | ||
944 | qup_i2c_set_write_mode(qup, msg); | |
945 | ||
946 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
947 | if (ret) | |
948 | goto err; | |
949 | ||
950 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
951 | ||
952 | do { | |
953 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
954 | if (ret) | |
955 | goto err; | |
956 | ||
c4f0c5fb S |
957 | ret = qup_i2c_issue_write(qup, msg); |
958 | if (ret) | |
959 | goto err; | |
10c5a842 BA |
960 | |
961 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
962 | if (ret) | |
963 | goto err; | |
964 | ||
191424bb S |
965 | ret = qup_i2c_wait_for_complete(qup, msg); |
966 | if (ret) | |
10c5a842 | 967 | goto err; |
10c5a842 BA |
968 | } while (qup->pos < msg->len); |
969 | ||
970 | /* Wait for the outstanding data in the fifo to drain */ | |
c4f0c5fb | 971 | ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE); |
10c5a842 BA |
972 | err: |
973 | disable_irq(qup->irq); | |
974 | qup->msg = NULL; | |
975 | ||
976 | return ret; | |
977 | } | |
978 | ||
979 | static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len) | |
980 | { | |
981 | if (len < qup->in_fifo_sz) { | |
982 | /* FIFO mode */ | |
983 | writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); | |
984 | writel(len, qup->base + QUP_MX_READ_CNT); | |
985 | } else { | |
986 | /* BLOCK mode (transfer data on chunks) */ | |
987 | writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN, | |
988 | qup->base + QUP_IO_MODE); | |
989 | writel(len, qup->base + QUP_MX_INPUT_CNT); | |
990 | } | |
991 | } | |
992 | ||
191424bb S |
993 | static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len) |
994 | { | |
995 | int tx_len = qup->blk.tx_tag_len; | |
996 | ||
997 | len += qup->blk.rx_tag_len; | |
f7418793 S |
998 | len |= qup->config_run; |
999 | tx_len |= qup->config_run; | |
191424bb S |
1000 | |
1001 | if (len < qup->in_fifo_sz) { | |
1002 | /* FIFO mode */ | |
1003 | writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); | |
191424bb | 1004 | writel(tx_len, qup->base + QUP_MX_WRITE_CNT); |
f7418793 | 1005 | writel(len, qup->base + QUP_MX_READ_CNT); |
191424bb S |
1006 | } else { |
1007 | /* BLOCK mode (transfer data on chunks) */ | |
1008 | writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN, | |
1009 | qup->base + QUP_IO_MODE); | |
191424bb | 1010 | writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT); |
f7418793 | 1011 | writel(len, qup->base + QUP_MX_INPUT_CNT); |
191424bb S |
1012 | } |
1013 | } | |
1014 | ||
10c5a842 BA |
1015 | static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg) |
1016 | { | |
1017 | u32 addr, len, val; | |
1018 | ||
0130944b | 1019 | addr = i2c_8bit_addr_from_msg(msg); |
10c5a842 BA |
1020 | |
1021 | /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */ | |
1022 | len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; | |
1023 | ||
1024 | val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr; | |
1025 | writel(val, qup->base + QUP_OUT_FIFO_BASE); | |
1026 | } | |
1027 | ||
1028 | ||
c4f0c5fb | 1029 | static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg) |
10c5a842 | 1030 | { |
10c5a842 BA |
1031 | u32 val = 0; |
1032 | int idx; | |
c4f0c5fb | 1033 | int ret = 0; |
10c5a842 BA |
1034 | |
1035 | for (idx = 0; qup->pos < msg->len; idx++) { | |
1036 | if ((idx & 1) == 0) { | |
1037 | /* Check that FIFO have data */ | |
c4f0c5fb S |
1038 | ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY, |
1039 | SET_BIT, 4 * ONE_BYTE); | |
1040 | if (ret) | |
1041 | return ret; | |
10c5a842 BA |
1042 | |
1043 | /* Reading 2 words at time */ | |
1044 | val = readl(qup->base + QUP_IN_FIFO_BASE); | |
1045 | ||
1046 | msg->buf[qup->pos++] = val & 0xFF; | |
1047 | } else { | |
1048 | msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; | |
1049 | } | |
1050 | } | |
c4f0c5fb S |
1051 | |
1052 | return ret; | |
10c5a842 BA |
1053 | } |
1054 | ||
191424bb S |
1055 | static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup, |
1056 | struct i2c_msg *msg) | |
1057 | { | |
1058 | u32 val; | |
1059 | int idx, pos = 0, ret = 0, total; | |
1060 | ||
1061 | total = qup_i2c_get_data_len(qup); | |
1062 | ||
1063 | /* 2 extra bytes for read tags */ | |
1064 | while (pos < (total + 2)) { | |
1065 | /* Check that FIFO have data */ | |
1066 | ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY, | |
1067 | SET_BIT, 4 * ONE_BYTE); | |
1068 | if (ret) { | |
1069 | dev_err(qup->dev, "timeout for fifo not empty"); | |
1070 | return ret; | |
1071 | } | |
1072 | val = readl(qup->base + QUP_IN_FIFO_BASE); | |
1073 | ||
1074 | for (idx = 0; idx < 4; idx++, val >>= 8, pos++) { | |
1075 | /* first 2 bytes are tag bytes */ | |
1076 | if (pos < 2) | |
1077 | continue; | |
1078 | ||
1079 | if (pos >= (total + 2)) | |
1080 | goto out; | |
1081 | ||
1082 | msg->buf[qup->pos++] = val & 0xff; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | out: | |
1087 | qup->blk.data_len -= total; | |
1088 | ||
1089 | return ret; | |
1090 | } | |
1091 | ||
1092 | static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg) | |
1093 | { | |
1094 | int ret = 0; | |
1095 | ||
1096 | qup->msg = msg; | |
1097 | qup->pos = 0; | |
1098 | enable_irq(qup->irq); | |
1099 | qup_i2c_set_blk_data(qup, msg); | |
1100 | qup_i2c_set_read_mode_v2(qup, msg->len); | |
1101 | ||
1102 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
1103 | if (ret) | |
1104 | goto err; | |
1105 | ||
1106 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
1107 | ||
1108 | do { | |
1109 | ret = qup_i2c_issue_xfer_v2(qup, msg); | |
1110 | if (ret) | |
1111 | goto err; | |
1112 | ||
1113 | ret = qup_i2c_wait_for_complete(qup, msg); | |
1114 | if (ret) | |
1115 | goto err; | |
1116 | ||
1117 | ret = qup_i2c_read_fifo_v2(qup, msg); | |
1118 | if (ret) | |
1119 | goto err; | |
1120 | ||
1121 | qup->blk.pos++; | |
1122 | } while (qup->blk.pos < qup->blk.count); | |
1123 | ||
1124 | err: | |
1125 | disable_irq(qup->irq); | |
1126 | qup->msg = NULL; | |
1127 | ||
1128 | return ret; | |
1129 | } | |
1130 | ||
10c5a842 BA |
1131 | static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg) |
1132 | { | |
10c5a842 BA |
1133 | int ret; |
1134 | ||
10c5a842 BA |
1135 | qup->msg = msg; |
1136 | qup->pos = 0; | |
1137 | ||
1138 | enable_irq(qup->irq); | |
10c5a842 BA |
1139 | qup_i2c_set_read_mode(qup, msg->len); |
1140 | ||
1141 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
1142 | if (ret) | |
1143 | goto err; | |
1144 | ||
1145 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
1146 | ||
1147 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
1148 | if (ret) | |
1149 | goto err; | |
1150 | ||
1151 | qup_i2c_issue_read(qup, msg); | |
1152 | ||
1153 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
1154 | if (ret) | |
1155 | goto err; | |
1156 | ||
1157 | do { | |
191424bb S |
1158 | ret = qup_i2c_wait_for_complete(qup, msg); |
1159 | if (ret) | |
10c5a842 | 1160 | goto err; |
10c5a842 | 1161 | |
c4f0c5fb S |
1162 | ret = qup_i2c_read_fifo(qup, msg); |
1163 | if (ret) | |
1164 | goto err; | |
10c5a842 BA |
1165 | } while (qup->pos < msg->len); |
1166 | ||
1167 | err: | |
1168 | disable_irq(qup->irq); | |
1169 | qup->msg = NULL; | |
1170 | ||
1171 | return ret; | |
1172 | } | |
1173 | ||
1174 | static int qup_i2c_xfer(struct i2c_adapter *adap, | |
1175 | struct i2c_msg msgs[], | |
1176 | int num) | |
1177 | { | |
1178 | struct qup_i2c_dev *qup = i2c_get_adapdata(adap); | |
1179 | int ret, idx; | |
1180 | ||
1181 | ret = pm_runtime_get_sync(qup->dev); | |
fa01d096 | 1182 | if (ret < 0) |
10c5a842 BA |
1183 | goto out; |
1184 | ||
fbf9921f S |
1185 | qup->bus_err = 0; |
1186 | qup->qup_err = 0; | |
1187 | ||
10c5a842 BA |
1188 | writel(1, qup->base + QUP_SW_RESET); |
1189 | ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); | |
1190 | if (ret) | |
1191 | goto out; | |
1192 | ||
1193 | /* Configure QUP as I2C mini core */ | |
1194 | writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); | |
1195 | ||
1196 | for (idx = 0; idx < num; idx++) { | |
1197 | if (msgs[idx].len == 0) { | |
1198 | ret = -EINVAL; | |
1199 | goto out; | |
1200 | } | |
1201 | ||
1202 | if (qup_i2c_poll_state_i2c_master(qup)) { | |
1203 | ret = -EIO; | |
1204 | goto out; | |
1205 | } | |
1206 | ||
1207 | if (msgs[idx].flags & I2C_M_RD) | |
1208 | ret = qup_i2c_read_one(qup, &msgs[idx]); | |
1209 | else | |
1210 | ret = qup_i2c_write_one(qup, &msgs[idx]); | |
1211 | ||
1212 | if (ret) | |
1213 | break; | |
1214 | ||
1215 | ret = qup_i2c_change_state(qup, QUP_RESET_STATE); | |
1216 | if (ret) | |
1217 | break; | |
1218 | } | |
1219 | ||
1220 | if (ret == 0) | |
1221 | ret = num; | |
1222 | out: | |
1223 | ||
1224 | pm_runtime_mark_last_busy(qup->dev); | |
1225 | pm_runtime_put_autosuspend(qup->dev); | |
1226 | ||
1227 | return ret; | |
1228 | } | |
1229 | ||
191424bb S |
1230 | static int qup_i2c_xfer_v2(struct i2c_adapter *adap, |
1231 | struct i2c_msg msgs[], | |
1232 | int num) | |
1233 | { | |
1234 | struct qup_i2c_dev *qup = i2c_get_adapdata(adap); | |
9cedf3b2 | 1235 | int ret, len, idx = 0, use_dma = 0; |
191424bb | 1236 | |
fbf9921f S |
1237 | qup->bus_err = 0; |
1238 | qup->qup_err = 0; | |
1239 | ||
191424bb S |
1240 | ret = pm_runtime_get_sync(qup->dev); |
1241 | if (ret < 0) | |
1242 | goto out; | |
1243 | ||
1244 | writel(1, qup->base + QUP_SW_RESET); | |
1245 | ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); | |
1246 | if (ret) | |
1247 | goto out; | |
1248 | ||
1249 | /* Configure QUP as I2C mini core */ | |
1250 | writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); | |
1251 | writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); | |
1252 | ||
9cedf3b2 S |
1253 | if ((qup->is_dma)) { |
1254 | /* All i2c_msgs should be transferred using either dma or cpu */ | |
1255 | for (idx = 0; idx < num; idx++) { | |
1256 | if (msgs[idx].len == 0) { | |
1257 | ret = -EINVAL; | |
1258 | goto out; | |
1259 | } | |
1260 | ||
1261 | len = (msgs[idx].len > qup->out_fifo_sz) || | |
1262 | (msgs[idx].len > qup->in_fifo_sz); | |
1263 | ||
1264 | if ((!is_vmalloc_addr(msgs[idx].buf)) && len) { | |
1265 | use_dma = 1; | |
1266 | } else { | |
1267 | use_dma = 0; | |
1268 | break; | |
1269 | } | |
1270 | } | |
1271 | } | |
1272 | ||
d4f56c77 S |
1273 | idx = 0; |
1274 | ||
9cedf3b2 | 1275 | do { |
191424bb S |
1276 | if (msgs[idx].len == 0) { |
1277 | ret = -EINVAL; | |
1278 | goto out; | |
1279 | } | |
1280 | ||
1281 | if (qup_i2c_poll_state_i2c_master(qup)) { | |
1282 | ret = -EIO; | |
1283 | goto out; | |
1284 | } | |
1285 | ||
f7418793 S |
1286 | qup->is_last = (idx == (num - 1)); |
1287 | if (idx) | |
1288 | qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN; | |
1289 | else | |
1290 | qup->config_run = 0; | |
1291 | ||
191424bb S |
1292 | reinit_completion(&qup->xfer); |
1293 | ||
9cedf3b2 S |
1294 | if (use_dma) { |
1295 | ret = qup_i2c_bam_xfer(adap, &msgs[idx], num); | |
1296 | } else { | |
1297 | if (msgs[idx].flags & I2C_M_RD) | |
1298 | ret = qup_i2c_read_one_v2(qup, &msgs[idx]); | |
1299 | else | |
1300 | ret = qup_i2c_write_one_v2(qup, &msgs[idx]); | |
1301 | } | |
1302 | } while ((idx++ < (num - 1)) && !use_dma && !ret); | |
191424bb | 1303 | |
f7418793 S |
1304 | if (!ret) |
1305 | ret = qup_i2c_change_state(qup, QUP_RESET_STATE); | |
1306 | ||
191424bb S |
1307 | if (ret == 0) |
1308 | ret = num; | |
1309 | out: | |
1310 | pm_runtime_mark_last_busy(qup->dev); | |
1311 | pm_runtime_put_autosuspend(qup->dev); | |
1312 | ||
1313 | return ret; | |
1314 | } | |
1315 | ||
10c5a842 BA |
1316 | static u32 qup_i2c_func(struct i2c_adapter *adap) |
1317 | { | |
1318 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
1319 | } | |
1320 | ||
1321 | static const struct i2c_algorithm qup_i2c_algo = { | |
1322 | .master_xfer = qup_i2c_xfer, | |
1323 | .functionality = qup_i2c_func, | |
1324 | }; | |
1325 | ||
191424bb S |
1326 | static const struct i2c_algorithm qup_i2c_algo_v2 = { |
1327 | .master_xfer = qup_i2c_xfer_v2, | |
1328 | .functionality = qup_i2c_func, | |
1329 | }; | |
1330 | ||
994647db WS |
1331 | /* |
1332 | * The QUP block will issue a NACK and STOP on the bus when reaching | |
1333 | * the end of the read, the length of the read is specified as one byte | |
1334 | * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. | |
1335 | */ | |
1336 | static struct i2c_adapter_quirks qup_i2c_quirks = { | |
1337 | .max_read_len = QUP_READ_LIMIT, | |
1338 | }; | |
1339 | ||
10c5a842 BA |
1340 | static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) |
1341 | { | |
1342 | clk_prepare_enable(qup->clk); | |
1343 | clk_prepare_enable(qup->pclk); | |
1344 | } | |
1345 | ||
1346 | static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) | |
1347 | { | |
1348 | u32 config; | |
1349 | ||
1350 | qup_i2c_change_state(qup, QUP_RESET_STATE); | |
1351 | clk_disable_unprepare(qup->clk); | |
1352 | config = readl(qup->base + QUP_CONFIG); | |
1353 | config |= QUP_CLOCK_AUTO_GATE; | |
1354 | writel(config, qup->base + QUP_CONFIG); | |
1355 | clk_disable_unprepare(qup->pclk); | |
1356 | } | |
1357 | ||
1358 | static int qup_i2c_probe(struct platform_device *pdev) | |
1359 | { | |
1360 | static const int blk_sizes[] = {4, 16, 32}; | |
1361 | struct device_node *node = pdev->dev.of_node; | |
1362 | struct qup_i2c_dev *qup; | |
1363 | unsigned long one_bit_t; | |
1364 | struct resource *res; | |
1365 | u32 io_mode, hw_ver, size; | |
1366 | int ret, fs_div, hs_div; | |
1367 | int src_clk_freq; | |
cf23e335 | 1368 | u32 clk_freq = 100000; |
9cedf3b2 | 1369 | int blocks; |
10c5a842 BA |
1370 | |
1371 | qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); | |
1372 | if (!qup) | |
1373 | return -ENOMEM; | |
1374 | ||
1375 | qup->dev = &pdev->dev; | |
1376 | init_completion(&qup->xfer); | |
1377 | platform_set_drvdata(pdev, qup); | |
1378 | ||
1379 | of_property_read_u32(node, "clock-frequency", &clk_freq); | |
1380 | ||
191424bb S |
1381 | if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { |
1382 | qup->adap.algo = &qup_i2c_algo; | |
1383 | qup->adap.quirks = &qup_i2c_quirks; | |
1384 | } else { | |
1385 | qup->adap.algo = &qup_i2c_algo_v2; | |
9cedf3b2 S |
1386 | ret = qup_i2c_req_dma(qup); |
1387 | ||
1388 | if (ret == -EPROBE_DEFER) | |
1389 | goto fail_dma; | |
1390 | else if (ret != 0) | |
1391 | goto nodma; | |
1392 | ||
1393 | blocks = (MX_BLOCKS << 1) + 1; | |
1394 | qup->btx.sg = devm_kzalloc(&pdev->dev, | |
1395 | sizeof(*qup->btx.sg) * blocks, | |
1396 | GFP_KERNEL); | |
1397 | if (!qup->btx.sg) { | |
1398 | ret = -ENOMEM; | |
1399 | goto fail_dma; | |
1400 | } | |
1401 | sg_init_table(qup->btx.sg, blocks); | |
1402 | ||
1403 | qup->brx.sg = devm_kzalloc(&pdev->dev, | |
1404 | sizeof(*qup->brx.sg) * blocks, | |
1405 | GFP_KERNEL); | |
1406 | if (!qup->brx.sg) { | |
1407 | ret = -ENOMEM; | |
1408 | goto fail_dma; | |
1409 | } | |
1410 | sg_init_table(qup->brx.sg, blocks); | |
1411 | ||
1412 | /* 2 tag bytes for each block + 5 for start, stop tags */ | |
1413 | size = blocks * 2 + 5; | |
9cedf3b2 | 1414 | |
685983f4 S |
1415 | qup->start_tag.start = devm_kzalloc(&pdev->dev, |
1416 | size, GFP_KERNEL); | |
9cedf3b2 S |
1417 | if (!qup->start_tag.start) { |
1418 | ret = -ENOMEM; | |
1419 | goto fail_dma; | |
1420 | } | |
1421 | ||
685983f4 | 1422 | qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); |
9cedf3b2 S |
1423 | if (!qup->brx.tag.start) { |
1424 | ret = -ENOMEM; | |
1425 | goto fail_dma; | |
1426 | } | |
1427 | ||
685983f4 | 1428 | qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); |
9cedf3b2 S |
1429 | if (!qup->btx.tag.start) { |
1430 | ret = -ENOMEM; | |
1431 | goto fail_dma; | |
1432 | } | |
1433 | qup->is_dma = true; | |
191424bb S |
1434 | } |
1435 | ||
9cedf3b2 | 1436 | nodma: |
10c5a842 BA |
1437 | /* We support frequencies up to FAST Mode (400KHz) */ |
1438 | if (!clk_freq || clk_freq > 400000) { | |
1439 | dev_err(qup->dev, "clock frequency not supported %d\n", | |
1440 | clk_freq); | |
1441 | return -EINVAL; | |
1442 | } | |
1443 | ||
1444 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1445 | qup->base = devm_ioremap_resource(qup->dev, res); | |
1446 | if (IS_ERR(qup->base)) | |
1447 | return PTR_ERR(qup->base); | |
1448 | ||
1449 | qup->irq = platform_get_irq(pdev, 0); | |
1450 | if (qup->irq < 0) { | |
1451 | dev_err(qup->dev, "No IRQ defined\n"); | |
1452 | return qup->irq; | |
1453 | } | |
1454 | ||
1455 | qup->clk = devm_clk_get(qup->dev, "core"); | |
1456 | if (IS_ERR(qup->clk)) { | |
1457 | dev_err(qup->dev, "Could not get core clock\n"); | |
1458 | return PTR_ERR(qup->clk); | |
1459 | } | |
1460 | ||
1461 | qup->pclk = devm_clk_get(qup->dev, "iface"); | |
1462 | if (IS_ERR(qup->pclk)) { | |
1463 | dev_err(qup->dev, "Could not get iface clock\n"); | |
1464 | return PTR_ERR(qup->pclk); | |
1465 | } | |
1466 | ||
1467 | qup_i2c_enable_clocks(qup); | |
1468 | ||
1469 | /* | |
1470 | * Bootloaders might leave a pending interrupt on certain QUP's, | |
1471 | * so we reset the core before registering for interrupts. | |
1472 | */ | |
1473 | writel(1, qup->base + QUP_SW_RESET); | |
1474 | ret = qup_i2c_poll_state_valid(qup); | |
1475 | if (ret) | |
1476 | goto fail; | |
1477 | ||
1478 | ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, | |
1479 | IRQF_TRIGGER_HIGH, "i2c_qup", qup); | |
1480 | if (ret) { | |
1481 | dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); | |
1482 | goto fail; | |
1483 | } | |
1484 | disable_irq(qup->irq); | |
1485 | ||
1486 | hw_ver = readl(qup->base + QUP_HW_VERSION); | |
1487 | dev_dbg(qup->dev, "Revision %x\n", hw_ver); | |
1488 | ||
1489 | io_mode = readl(qup->base + QUP_IO_MODE); | |
1490 | ||
1491 | /* | |
1492 | * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' | |
1493 | * associated with each byte written/received | |
1494 | */ | |
1495 | size = QUP_OUTPUT_BLOCK_SIZE(io_mode); | |
3cf357df PG |
1496 | if (size >= ARRAY_SIZE(blk_sizes)) { |
1497 | ret = -EIO; | |
1498 | goto fail; | |
1499 | } | |
10c5a842 BA |
1500 | qup->out_blk_sz = blk_sizes[size] / 2; |
1501 | ||
1502 | size = QUP_INPUT_BLOCK_SIZE(io_mode); | |
3cf357df PG |
1503 | if (size >= ARRAY_SIZE(blk_sizes)) { |
1504 | ret = -EIO; | |
1505 | goto fail; | |
1506 | } | |
10c5a842 BA |
1507 | qup->in_blk_sz = blk_sizes[size] / 2; |
1508 | ||
1509 | size = QUP_OUTPUT_FIFO_SIZE(io_mode); | |
1510 | qup->out_fifo_sz = qup->out_blk_sz * (2 << size); | |
1511 | ||
1512 | size = QUP_INPUT_FIFO_SIZE(io_mode); | |
1513 | qup->in_fifo_sz = qup->in_blk_sz * (2 << size); | |
1514 | ||
1515 | src_clk_freq = clk_get_rate(qup->clk); | |
1516 | fs_div = ((src_clk_freq / clk_freq) / 2) - 3; | |
1517 | hs_div = 3; | |
1518 | qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); | |
1519 | ||
1520 | /* | |
1521 | * Time it takes for a byte to be clocked out on the bus. | |
1522 | * Each byte takes 9 clock cycles (8 bits + 1 ack). | |
1523 | */ | |
1524 | one_bit_t = (USEC_PER_SEC / clk_freq) + 1; | |
1525 | qup->one_byte_t = one_bit_t * 9; | |
1526 | ||
1527 | dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", | |
1528 | qup->in_blk_sz, qup->in_fifo_sz, | |
1529 | qup->out_blk_sz, qup->out_fifo_sz); | |
1530 | ||
1531 | i2c_set_adapdata(&qup->adap, qup); | |
10c5a842 BA |
1532 | qup->adap.dev.parent = qup->dev; |
1533 | qup->adap.dev.of_node = pdev->dev.of_node; | |
9cedf3b2 | 1534 | qup->is_last = true; |
f7418793 | 1535 | |
10c5a842 BA |
1536 | strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); |
1537 | ||
10c5a842 BA |
1538 | pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); |
1539 | pm_runtime_use_autosuspend(qup->dev); | |
1540 | pm_runtime_set_active(qup->dev); | |
1541 | pm_runtime_enable(qup->dev); | |
86b59bbf AG |
1542 | |
1543 | ret = i2c_add_adapter(&qup->adap); | |
1544 | if (ret) | |
1545 | goto fail_runtime; | |
1546 | ||
10c5a842 BA |
1547 | return 0; |
1548 | ||
86b59bbf AG |
1549 | fail_runtime: |
1550 | pm_runtime_disable(qup->dev); | |
1551 | pm_runtime_set_suspended(qup->dev); | |
10c5a842 BA |
1552 | fail: |
1553 | qup_i2c_disable_clocks(qup); | |
9cedf3b2 S |
1554 | fail_dma: |
1555 | if (qup->btx.dma) | |
1556 | dma_release_channel(qup->btx.dma); | |
1557 | if (qup->brx.dma) | |
1558 | dma_release_channel(qup->brx.dma); | |
10c5a842 BA |
1559 | return ret; |
1560 | } | |
1561 | ||
1562 | static int qup_i2c_remove(struct platform_device *pdev) | |
1563 | { | |
1564 | struct qup_i2c_dev *qup = platform_get_drvdata(pdev); | |
1565 | ||
9cedf3b2 | 1566 | if (qup->is_dma) { |
9cedf3b2 S |
1567 | dma_release_channel(qup->btx.dma); |
1568 | dma_release_channel(qup->brx.dma); | |
1569 | } | |
1570 | ||
10c5a842 BA |
1571 | disable_irq(qup->irq); |
1572 | qup_i2c_disable_clocks(qup); | |
1573 | i2c_del_adapter(&qup->adap); | |
1574 | pm_runtime_disable(qup->dev); | |
1575 | pm_runtime_set_suspended(qup->dev); | |
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | #ifdef CONFIG_PM | |
1580 | static int qup_i2c_pm_suspend_runtime(struct device *device) | |
1581 | { | |
1582 | struct qup_i2c_dev *qup = dev_get_drvdata(device); | |
1583 | ||
1584 | dev_dbg(device, "pm_runtime: suspending...\n"); | |
1585 | qup_i2c_disable_clocks(qup); | |
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | static int qup_i2c_pm_resume_runtime(struct device *device) | |
1590 | { | |
1591 | struct qup_i2c_dev *qup = dev_get_drvdata(device); | |
1592 | ||
1593 | dev_dbg(device, "pm_runtime: resuming...\n"); | |
1594 | qup_i2c_enable_clocks(qup); | |
1595 | return 0; | |
1596 | } | |
1597 | #endif | |
1598 | ||
1599 | #ifdef CONFIG_PM_SLEEP | |
1600 | static int qup_i2c_suspend(struct device *device) | |
1601 | { | |
331dcf42 SH |
1602 | if (!pm_runtime_suspended(device)) |
1603 | return qup_i2c_pm_suspend_runtime(device); | |
10c5a842 BA |
1604 | return 0; |
1605 | } | |
1606 | ||
1607 | static int qup_i2c_resume(struct device *device) | |
1608 | { | |
1609 | qup_i2c_pm_resume_runtime(device); | |
1610 | pm_runtime_mark_last_busy(device); | |
1611 | pm_request_autosuspend(device); | |
1612 | return 0; | |
1613 | } | |
1614 | #endif | |
1615 | ||
1616 | static const struct dev_pm_ops qup_i2c_qup_pm_ops = { | |
1617 | SET_SYSTEM_SLEEP_PM_OPS( | |
1618 | qup_i2c_suspend, | |
1619 | qup_i2c_resume) | |
1620 | SET_RUNTIME_PM_OPS( | |
1621 | qup_i2c_pm_suspend_runtime, | |
1622 | qup_i2c_pm_resume_runtime, | |
1623 | NULL) | |
1624 | }; | |
1625 | ||
1626 | static const struct of_device_id qup_i2c_dt_match[] = { | |
1627 | { .compatible = "qcom,i2c-qup-v1.1.1" }, | |
1628 | { .compatible = "qcom,i2c-qup-v2.1.1" }, | |
1629 | { .compatible = "qcom,i2c-qup-v2.2.1" }, | |
1630 | {} | |
1631 | }; | |
1632 | MODULE_DEVICE_TABLE(of, qup_i2c_dt_match); | |
1633 | ||
1634 | static struct platform_driver qup_i2c_driver = { | |
1635 | .probe = qup_i2c_probe, | |
1636 | .remove = qup_i2c_remove, | |
1637 | .driver = { | |
1638 | .name = "i2c_qup", | |
10c5a842 BA |
1639 | .pm = &qup_i2c_qup_pm_ops, |
1640 | .of_match_table = qup_i2c_dt_match, | |
1641 | }, | |
1642 | }; | |
1643 | ||
1644 | module_platform_driver(qup_i2c_driver); | |
1645 | ||
1646 | MODULE_LICENSE("GPL v2"); | |
1647 | MODULE_ALIAS("platform:i2c_qup"); |