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0668bc44 | 1 | // SPDX-License-Identifier: GPL-2.0 |
10c5a842 | 2 | /* |
0668bc44 | 3 | * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved. |
10c5a842 BA |
4 | * Copyright (c) 2014, Sony Mobile Communications AB. |
5 | * | |
10c5a842 BA |
6 | */ |
7 | ||
515da746 | 8 | #include <linux/acpi.h> |
9cedf3b2 | 9 | #include <linux/atomic.h> |
10c5a842 BA |
10 | #include <linux/clk.h> |
11 | #include <linux/delay.h> | |
9cedf3b2 S |
12 | #include <linux/dmaengine.h> |
13 | #include <linux/dmapool.h> | |
14 | #include <linux/dma-mapping.h> | |
10c5a842 BA |
15 | #include <linux/err.h> |
16 | #include <linux/i2c.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/pm_runtime.h> | |
9cedf3b2 | 23 | #include <linux/scatterlist.h> |
10c5a842 BA |
24 | |
25 | /* QUP Registers */ | |
26 | #define QUP_CONFIG 0x000 | |
27 | #define QUP_STATE 0x004 | |
28 | #define QUP_IO_MODE 0x008 | |
29 | #define QUP_SW_RESET 0x00c | |
30 | #define QUP_OPERATIONAL 0x018 | |
31 | #define QUP_ERROR_FLAGS 0x01c | |
32 | #define QUP_ERROR_FLAGS_EN 0x020 | |
9cedf3b2 | 33 | #define QUP_OPERATIONAL_MASK 0x028 |
10c5a842 BA |
34 | #define QUP_HW_VERSION 0x030 |
35 | #define QUP_MX_OUTPUT_CNT 0x100 | |
36 | #define QUP_OUT_FIFO_BASE 0x110 | |
37 | #define QUP_MX_WRITE_CNT 0x150 | |
38 | #define QUP_MX_INPUT_CNT 0x200 | |
39 | #define QUP_MX_READ_CNT 0x208 | |
40 | #define QUP_IN_FIFO_BASE 0x218 | |
41 | #define QUP_I2C_CLK_CTL 0x400 | |
42 | #define QUP_I2C_STATUS 0x404 | |
191424bb | 43 | #define QUP_I2C_MASTER_GEN 0x408 |
10c5a842 BA |
44 | |
45 | /* QUP States and reset values */ | |
46 | #define QUP_RESET_STATE 0 | |
47 | #define QUP_RUN_STATE 1 | |
48 | #define QUP_PAUSE_STATE 3 | |
49 | #define QUP_STATE_MASK 3 | |
50 | ||
51 | #define QUP_STATE_VALID BIT(2) | |
52 | #define QUP_I2C_MAST_GEN BIT(4) | |
9cedf3b2 | 53 | #define QUP_I2C_FLUSH BIT(6) |
10c5a842 BA |
54 | |
55 | #define QUP_OPERATIONAL_RESET 0x000ff0 | |
56 | #define QUP_I2C_STATUS_RESET 0xfffffc | |
57 | ||
58 | /* QUP OPERATIONAL FLAGS */ | |
59 | #define QUP_I2C_NACK_FLAG BIT(3) | |
60 | #define QUP_OUT_NOT_EMPTY BIT(4) | |
61 | #define QUP_IN_NOT_EMPTY BIT(5) | |
62 | #define QUP_OUT_FULL BIT(6) | |
63 | #define QUP_OUT_SVC_FLAG BIT(8) | |
64 | #define QUP_IN_SVC_FLAG BIT(9) | |
65 | #define QUP_MX_OUTPUT_DONE BIT(10) | |
66 | #define QUP_MX_INPUT_DONE BIT(11) | |
fbfab1ab AS |
67 | #define OUT_BLOCK_WRITE_REQ BIT(12) |
68 | #define IN_BLOCK_READ_REQ BIT(13) | |
10c5a842 BA |
69 | |
70 | /* I2C mini core related values */ | |
fbfab1ab | 71 | #define QUP_NO_INPUT BIT(7) |
10c5a842 BA |
72 | #define QUP_CLOCK_AUTO_GATE BIT(13) |
73 | #define I2C_MINI_CORE (2 << 8) | |
74 | #define I2C_N_VAL 15 | |
191424bb S |
75 | #define I2C_N_VAL_V2 7 |
76 | ||
10c5a842 BA |
77 | /* Most significant word offset in FIFO port */ |
78 | #define QUP_MSW_SHIFT (I2C_N_VAL + 1) | |
79 | ||
80 | /* Packing/Unpacking words in FIFOs, and IO modes */ | |
81 | #define QUP_OUTPUT_BLK_MODE (1 << 10) | |
9cedf3b2 | 82 | #define QUP_OUTPUT_BAM_MODE (3 << 10) |
10c5a842 | 83 | #define QUP_INPUT_BLK_MODE (1 << 12) |
9cedf3b2 S |
84 | #define QUP_INPUT_BAM_MODE (3 << 12) |
85 | #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE) | |
10c5a842 BA |
86 | #define QUP_UNPACK_EN BIT(14) |
87 | #define QUP_PACK_EN BIT(15) | |
88 | ||
89 | #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN) | |
191424bb | 90 | #define QUP_V2_TAGS_EN 1 |
10c5a842 BA |
91 | |
92 | #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03) | |
93 | #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07) | |
94 | #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03) | |
95 | #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07) | |
96 | ||
97 | /* QUP tags */ | |
98 | #define QUP_TAG_START (1 << 8) | |
99 | #define QUP_TAG_DATA (2 << 8) | |
100 | #define QUP_TAG_STOP (3 << 8) | |
101 | #define QUP_TAG_REC (4 << 8) | |
9cedf3b2 S |
102 | #define QUP_BAM_INPUT_EOT 0x93 |
103 | #define QUP_BAM_FLUSH_STOP 0x96 | |
10c5a842 | 104 | |
191424bb S |
105 | /* QUP v2 tags */ |
106 | #define QUP_TAG_V2_START 0x81 | |
107 | #define QUP_TAG_V2_DATAWR 0x82 | |
108 | #define QUP_TAG_V2_DATAWR_STOP 0x83 | |
109 | #define QUP_TAG_V2_DATARD 0x85 | |
f7714b4e | 110 | #define QUP_TAG_V2_DATARD_NACK 0x86 |
191424bb S |
111 | #define QUP_TAG_V2_DATARD_STOP 0x87 |
112 | ||
10c5a842 BA |
113 | /* Status, Error flags */ |
114 | #define I2C_STATUS_WR_BUFFER_FULL BIT(0) | |
115 | #define I2C_STATUS_BUS_ACTIVE BIT(8) | |
116 | #define I2C_STATUS_ERROR_MASK 0x38000fc | |
117 | #define QUP_STATUS_ERROR_FLAGS 0x7c | |
118 | ||
119 | #define QUP_READ_LIMIT 256 | |
c4f0c5fb S |
120 | #define SET_BIT 0x1 |
121 | #define RESET_BIT 0x0 | |
122 | #define ONE_BYTE 0x1 | |
f7418793 | 123 | #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) |
10c5a842 | 124 | |
6f2f0f64 | 125 | /* Maximum transfer length for single DMA descriptor */ |
9cedf3b2 S |
126 | #define MX_TX_RX_LEN SZ_64K |
127 | #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT) | |
6f2f0f64 AS |
128 | /* Maximum transfer length for all DMA descriptors */ |
129 | #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN) | |
130 | #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT) | |
9cedf3b2 | 131 | |
ecb6e1e5 AS |
132 | /* |
133 | * Minimum transfer timeout for i2c transfers in seconds. It will be added on | |
134 | * the top of maximum transfer time calculated from i2c bus speed to compensate | |
135 | * the overheads. | |
136 | */ | |
137 | #define TOUT_MIN 2 | |
9cedf3b2 | 138 | |
515da746 NK |
139 | /* Default values. Use these if FW query fails */ |
140 | #define DEFAULT_CLK_FREQ 100000 | |
141 | #define DEFAULT_SRC_CLK 20000000 | |
142 | ||
7545c7db AS |
143 | /* |
144 | * Max tags length (start, stop and maximum 2 bytes address) for each QUP | |
145 | * data transfer | |
146 | */ | |
147 | #define QUP_MAX_TAGS_LEN 4 | |
148 | /* Max data length for each DATARD tags */ | |
149 | #define RECV_MAX_DATA_LEN 254 | |
150 | /* TAG length for DATA READ in RX FIFO */ | |
151 | #define READ_RX_TAGS_LEN 2 | |
152 | ||
fbfab1ab AS |
153 | /* |
154 | * count: no of blocks | |
155 | * pos: current block number | |
156 | * tx_tag_len: tx tag length for current block | |
157 | * rx_tag_len: rx tag length for current block | |
158 | * data_len: remaining data length for current message | |
7545c7db | 159 | * cur_blk_len: data length for current block |
fbfab1ab AS |
160 | * total_tx_len: total tx length including tag bytes for current QUP transfer |
161 | * total_rx_len: total rx length including tag bytes for current QUP transfer | |
7545c7db | 162 | * tx_fifo_data_pos: current byte number in TX FIFO word |
fbfab1ab | 163 | * tx_fifo_free: number of free bytes in current QUP block write. |
7545c7db | 164 | * rx_fifo_data_pos: current byte number in RX FIFO word |
fbfab1ab AS |
165 | * fifo_available: number of available bytes in RX FIFO for current |
166 | * QUP block read | |
7545c7db AS |
167 | * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write |
168 | * to TX FIFO will be appended in this data and will be written to | |
169 | * TX FIFO when all the 4 bytes are available. | |
170 | * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will | |
171 | * contains the 4 bytes of RX data. | |
172 | * cur_data: pointer to tell cur data position for current message | |
173 | * cur_tx_tags: pointer to tell cur position in tags | |
174 | * tx_tags_sent: all tx tag bytes have been written in FIFO word | |
175 | * send_last_word: for tx FIFO, last word send is pending in current block | |
fbfab1ab | 176 | * rx_bytes_read: if all the bytes have been read from rx FIFO. |
7545c7db | 177 | * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word |
fbfab1ab AS |
178 | * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer. |
179 | * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer. | |
180 | * tags: contains tx tag bytes for current QUP transfer | |
181 | */ | |
191424bb | 182 | struct qup_i2c_block { |
fbfab1ab AS |
183 | int count; |
184 | int pos; | |
185 | int tx_tag_len; | |
186 | int rx_tag_len; | |
187 | int data_len; | |
7545c7db | 188 | int cur_blk_len; |
fbfab1ab AS |
189 | int total_tx_len; |
190 | int total_rx_len; | |
7545c7db | 191 | int tx_fifo_data_pos; |
fbfab1ab | 192 | int tx_fifo_free; |
7545c7db | 193 | int rx_fifo_data_pos; |
fbfab1ab | 194 | int fifo_available; |
7545c7db AS |
195 | u32 tx_fifo_data; |
196 | u32 rx_fifo_data; | |
197 | u8 *cur_data; | |
198 | u8 *cur_tx_tags; | |
199 | bool tx_tags_sent; | |
200 | bool send_last_word; | |
201 | bool rx_tags_fetched; | |
fbfab1ab AS |
202 | bool rx_bytes_read; |
203 | bool is_tx_blk_mode; | |
204 | bool is_rx_blk_mode; | |
205 | u8 tags[6]; | |
191424bb S |
206 | }; |
207 | ||
9cedf3b2 S |
208 | struct qup_i2c_tag { |
209 | u8 *start; | |
210 | dma_addr_t addr; | |
211 | }; | |
212 | ||
213 | struct qup_i2c_bam { | |
214 | struct qup_i2c_tag tag; | |
215 | struct dma_chan *dma; | |
216 | struct scatterlist *sg; | |
6f2f0f64 | 217 | unsigned int sg_cnt; |
9cedf3b2 S |
218 | }; |
219 | ||
10c5a842 BA |
220 | struct qup_i2c_dev { |
221 | struct device *dev; | |
222 | void __iomem *base; | |
223 | int irq; | |
224 | struct clk *clk; | |
225 | struct clk *pclk; | |
226 | struct i2c_adapter adap; | |
227 | ||
228 | int clk_ctl; | |
229 | int out_fifo_sz; | |
230 | int in_fifo_sz; | |
231 | int out_blk_sz; | |
232 | int in_blk_sz; | |
233 | ||
7545c7db | 234 | int blk_xfer_limit; |
10c5a842 | 235 | unsigned long one_byte_t; |
ecb6e1e5 | 236 | unsigned long xfer_timeout; |
191424bb | 237 | struct qup_i2c_block blk; |
10c5a842 BA |
238 | |
239 | struct i2c_msg *msg; | |
240 | /* Current posion in user message buffer */ | |
241 | int pos; | |
242 | /* I2C protocol errors */ | |
243 | u32 bus_err; | |
244 | /* QUP core errors */ | |
245 | u32 qup_err; | |
246 | ||
f7418793 S |
247 | /* To check if this is the last msg */ |
248 | bool is_last; | |
7545c7db | 249 | bool is_smbus_read; |
f7418793 S |
250 | |
251 | /* To configure when bus is in run state */ | |
7545c7db | 252 | u32 config_run; |
f7418793 | 253 | |
9cedf3b2 S |
254 | /* dma parameters */ |
255 | bool is_dma; | |
eb422b53 AS |
256 | /* To check if the current transfer is using DMA */ |
257 | bool use_dma; | |
6f2f0f64 AS |
258 | unsigned int max_xfer_sg_len; |
259 | unsigned int tag_buf_pos; | |
7545c7db AS |
260 | /* The threshold length above which block mode will be used */ |
261 | unsigned int blk_mode_threshold; | |
9cedf3b2 S |
262 | struct dma_pool *dpool; |
263 | struct qup_i2c_tag start_tag; | |
264 | struct qup_i2c_bam brx; | |
265 | struct qup_i2c_bam btx; | |
266 | ||
10c5a842 | 267 | struct completion xfer; |
fbfab1ab AS |
268 | /* function to write data in tx fifo */ |
269 | void (*write_tx_fifo)(struct qup_i2c_dev *qup); | |
270 | /* function to read data from rx fifo */ | |
271 | void (*read_rx_fifo)(struct qup_i2c_dev *qup); | |
272 | /* function to write tags in tx fifo for i2c read transfer */ | |
273 | void (*write_rx_tags)(struct qup_i2c_dev *qup); | |
10c5a842 BA |
274 | }; |
275 | ||
276 | static irqreturn_t qup_i2c_interrupt(int irq, void *dev) | |
277 | { | |
278 | struct qup_i2c_dev *qup = dev; | |
fbfab1ab | 279 | struct qup_i2c_block *blk = &qup->blk; |
10c5a842 BA |
280 | u32 bus_err; |
281 | u32 qup_err; | |
282 | u32 opflags; | |
283 | ||
284 | bus_err = readl(qup->base + QUP_I2C_STATUS); | |
285 | qup_err = readl(qup->base + QUP_ERROR_FLAGS); | |
286 | opflags = readl(qup->base + QUP_OPERATIONAL); | |
287 | ||
288 | if (!qup->msg) { | |
289 | /* Clear Error interrupt */ | |
290 | writel(QUP_RESET_STATE, qup->base + QUP_STATE); | |
291 | return IRQ_HANDLED; | |
292 | } | |
293 | ||
294 | bus_err &= I2C_STATUS_ERROR_MASK; | |
295 | qup_err &= QUP_STATUS_ERROR_FLAGS; | |
296 | ||
2b84a4dd AS |
297 | /* Clear the error bits in QUP_ERROR_FLAGS */ |
298 | if (qup_err) | |
10c5a842 | 299 | writel(qup_err, qup->base + QUP_ERROR_FLAGS); |
10c5a842 | 300 | |
2b84a4dd AS |
301 | /* Clear the error bits in QUP_I2C_STATUS */ |
302 | if (bus_err) | |
303 | writel(bus_err, qup->base + QUP_I2C_STATUS); | |
304 | ||
3f450d3e AS |
305 | /* |
306 | * Check for BAM mode and returns if already error has come for current | |
307 | * transfer. In Error case, sometimes, QUP generates more than one | |
308 | * interrupt. | |
309 | */ | |
310 | if (qup->use_dma && (qup->qup_err || qup->bus_err)) | |
311 | return IRQ_HANDLED; | |
312 | ||
2b84a4dd AS |
313 | /* Reset the QUP State in case of error */ |
314 | if (qup_err || bus_err) { | |
3f450d3e AS |
315 | /* |
316 | * Don’t reset the QUP state in case of BAM mode. The BAM | |
317 | * flush operation needs to be scheduled in transfer function | |
318 | * which will clear the remaining schedule descriptors in BAM | |
319 | * HW FIFO and generates the BAM interrupt. | |
320 | */ | |
321 | if (!qup->use_dma) | |
322 | writel(QUP_RESET_STATE, qup->base + QUP_STATE); | |
10c5a842 BA |
323 | goto done; |
324 | } | |
325 | ||
fbfab1ab | 326 | if (opflags & QUP_OUT_SVC_FLAG) { |
10c5a842 BA |
327 | writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); |
328 | ||
fbfab1ab AS |
329 | if (opflags & OUT_BLOCK_WRITE_REQ) { |
330 | blk->tx_fifo_free += qup->out_blk_sz; | |
331 | if (qup->msg->flags & I2C_M_RD) | |
332 | qup->write_rx_tags(qup); | |
333 | else | |
334 | qup->write_tx_fifo(qup); | |
335 | } | |
336 | } | |
337 | ||
338 | if (opflags & QUP_IN_SVC_FLAG) { | |
339 | writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); | |
340 | ||
341 | if (!blk->is_rx_blk_mode) { | |
342 | blk->fifo_available += qup->in_fifo_sz; | |
343 | qup->read_rx_fifo(qup); | |
344 | } else if (opflags & IN_BLOCK_READ_REQ) { | |
345 | blk->fifo_available += qup->in_blk_sz; | |
346 | qup->read_rx_fifo(qup); | |
347 | } | |
348 | } | |
349 | ||
350 | if (qup->msg->flags & I2C_M_RD) { | |
351 | if (!blk->rx_bytes_read) | |
352 | return IRQ_HANDLED; | |
353 | } else { | |
354 | /* | |
355 | * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked | |
356 | * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags | |
357 | * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason | |
358 | * of interrupt for write message in FIFO mode is | |
359 | * QUP_MAX_OUTPUT_DONE_FLAG condition. | |
360 | */ | |
361 | if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) | |
362 | return IRQ_HANDLED; | |
363 | } | |
364 | ||
10c5a842 BA |
365 | done: |
366 | qup->qup_err = qup_err; | |
367 | qup->bus_err = bus_err; | |
368 | complete(&qup->xfer); | |
369 | return IRQ_HANDLED; | |
370 | } | |
371 | ||
372 | static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, | |
373 | u32 req_state, u32 req_mask) | |
374 | { | |
375 | int retries = 1; | |
376 | u32 state; | |
377 | ||
378 | /* | |
379 | * State transition takes 3 AHB clocks cycles + 3 I2C master clock | |
380 | * cycles. So retry once after a 1uS delay. | |
381 | */ | |
382 | do { | |
383 | state = readl(qup->base + QUP_STATE); | |
384 | ||
385 | if (state & QUP_STATE_VALID && | |
386 | (state & req_mask) == req_state) | |
387 | return 0; | |
388 | ||
389 | udelay(1); | |
390 | } while (retries--); | |
391 | ||
392 | return -ETIMEDOUT; | |
393 | } | |
394 | ||
395 | static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) | |
396 | { | |
397 | return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); | |
398 | } | |
399 | ||
9cedf3b2 S |
400 | static void qup_i2c_flush(struct qup_i2c_dev *qup) |
401 | { | |
402 | u32 val = readl(qup->base + QUP_STATE); | |
403 | ||
404 | val |= QUP_I2C_FLUSH; | |
405 | writel(val, qup->base + QUP_STATE); | |
406 | } | |
407 | ||
10c5a842 BA |
408 | static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) |
409 | { | |
410 | return qup_i2c_poll_state_mask(qup, 0, 0); | |
411 | } | |
412 | ||
413 | static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) | |
414 | { | |
415 | return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); | |
416 | } | |
417 | ||
418 | static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) | |
419 | { | |
420 | if (qup_i2c_poll_state_valid(qup) != 0) | |
421 | return -EIO; | |
422 | ||
423 | writel(state, qup->base + QUP_STATE); | |
424 | ||
425 | if (qup_i2c_poll_state(qup, state) != 0) | |
426 | return -EIO; | |
427 | return 0; | |
428 | } | |
429 | ||
fbfab1ab AS |
430 | /* Check if I2C bus returns to IDLE state */ |
431 | static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len) | |
432 | { | |
433 | unsigned long timeout; | |
434 | u32 status; | |
435 | int ret = 0; | |
436 | ||
437 | timeout = jiffies + len * 4; | |
438 | for (;;) { | |
439 | status = readl(qup->base + QUP_I2C_STATUS); | |
440 | if (!(status & I2C_STATUS_BUS_ACTIVE)) | |
441 | break; | |
442 | ||
443 | if (time_after(jiffies, timeout)) | |
444 | ret = -ETIMEDOUT; | |
445 | ||
446 | usleep_range(len, len * 2); | |
447 | } | |
448 | ||
449 | return ret; | |
450 | } | |
451 | ||
fbfab1ab | 452 | static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup) |
10c5a842 | 453 | { |
fbfab1ab AS |
454 | struct qup_i2c_block *blk = &qup->blk; |
455 | struct i2c_msg *msg = qup->msg; | |
10c5a842 BA |
456 | u32 addr = msg->addr << 1; |
457 | u32 qup_tag; | |
10c5a842 BA |
458 | int idx; |
459 | u32 val; | |
460 | ||
461 | if (qup->pos == 0) { | |
462 | val = QUP_TAG_START | addr; | |
463 | idx = 1; | |
fbfab1ab | 464 | blk->tx_fifo_free--; |
10c5a842 BA |
465 | } else { |
466 | val = 0; | |
467 | idx = 0; | |
468 | } | |
469 | ||
fbfab1ab | 470 | while (blk->tx_fifo_free && qup->pos < msg->len) { |
10c5a842 BA |
471 | if (qup->pos == msg->len - 1) |
472 | qup_tag = QUP_TAG_STOP; | |
473 | else | |
474 | qup_tag = QUP_TAG_DATA; | |
475 | ||
476 | if (idx & 1) | |
477 | val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; | |
478 | else | |
479 | val = qup_tag | msg->buf[qup->pos]; | |
480 | ||
481 | /* Write out the pair and the last odd value */ | |
482 | if (idx & 1 || qup->pos == msg->len - 1) | |
483 | writel(val, qup->base + QUP_OUT_FIFO_BASE); | |
484 | ||
485 | qup->pos++; | |
486 | idx++; | |
fbfab1ab | 487 | blk->tx_fifo_free--; |
10c5a842 BA |
488 | } |
489 | } | |
490 | ||
191424bb S |
491 | static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, |
492 | struct i2c_msg *msg) | |
493 | { | |
7545c7db | 494 | qup->blk.pos = 0; |
191424bb | 495 | qup->blk.data_len = msg->len; |
7545c7db | 496 | qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); |
191424bb S |
497 | } |
498 | ||
499 | static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) | |
500 | { | |
501 | int data_len; | |
502 | ||
7545c7db AS |
503 | if (qup->blk.data_len > qup->blk_xfer_limit) |
504 | data_len = qup->blk_xfer_limit; | |
191424bb S |
505 | else |
506 | data_len = qup->blk.data_len; | |
507 | ||
508 | return data_len; | |
509 | } | |
510 | ||
cc9086e7 NK |
511 | static bool qup_i2c_check_msg_len(struct i2c_msg *msg) |
512 | { | |
513 | return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); | |
514 | } | |
515 | ||
516 | static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup, | |
517 | struct i2c_msg *msg) | |
518 | { | |
519 | int len = 0; | |
520 | ||
7545c7db | 521 | if (qup->is_smbus_read) { |
cc9086e7 | 522 | tags[len++] = QUP_TAG_V2_DATARD_STOP; |
7545c7db | 523 | tags[len++] = qup_i2c_get_data_len(qup); |
cc9086e7 NK |
524 | } else { |
525 | tags[len++] = QUP_TAG_V2_START; | |
526 | tags[len++] = addr & 0xff; | |
527 | ||
528 | if (msg->flags & I2C_M_TEN) | |
529 | tags[len++] = addr >> 8; | |
530 | ||
531 | tags[len++] = QUP_TAG_V2_DATARD; | |
532 | /* Read 1 byte indicating the length of the SMBus message */ | |
533 | tags[len++] = 1; | |
534 | } | |
535 | return len; | |
536 | } | |
537 | ||
191424bb | 538 | static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, |
c5adc0fa | 539 | struct i2c_msg *msg) |
191424bb | 540 | { |
e3c60f3d | 541 | u16 addr = i2c_8bit_addr_from_msg(msg); |
191424bb S |
542 | int len = 0; |
543 | int data_len; | |
544 | ||
9cedf3b2 S |
545 | int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); |
546 | ||
cc9086e7 NK |
547 | /* Handle tags for SMBus block read */ |
548 | if (qup_i2c_check_msg_len(msg)) | |
549 | return qup_i2c_set_tags_smb(addr, tags, qup, msg); | |
550 | ||
191424bb S |
551 | if (qup->blk.pos == 0) { |
552 | tags[len++] = QUP_TAG_V2_START; | |
553 | tags[len++] = addr & 0xff; | |
554 | ||
555 | if (msg->flags & I2C_M_TEN) | |
556 | tags[len++] = addr >> 8; | |
557 | } | |
558 | ||
559 | /* Send _STOP commands for the last block */ | |
9cedf3b2 | 560 | if (last) { |
191424bb S |
561 | if (msg->flags & I2C_M_RD) |
562 | tags[len++] = QUP_TAG_V2_DATARD_STOP; | |
563 | else | |
564 | tags[len++] = QUP_TAG_V2_DATAWR_STOP; | |
565 | } else { | |
566 | if (msg->flags & I2C_M_RD) | |
f7714b4e AS |
567 | tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? |
568 | QUP_TAG_V2_DATARD_NACK : | |
569 | QUP_TAG_V2_DATARD; | |
191424bb S |
570 | else |
571 | tags[len++] = QUP_TAG_V2_DATAWR; | |
572 | } | |
573 | ||
574 | data_len = qup_i2c_get_data_len(qup); | |
575 | ||
576 | /* 0 implies 256 bytes */ | |
577 | if (data_len == QUP_READ_LIMIT) | |
578 | tags[len++] = 0; | |
579 | else | |
580 | tags[len++] = data_len; | |
581 | ||
582 | return len; | |
583 | } | |
584 | ||
191424bb | 585 | |
9cedf3b2 S |
586 | static void qup_i2c_bam_cb(void *data) |
587 | { | |
588 | struct qup_i2c_dev *qup = data; | |
589 | ||
590 | complete(&qup->xfer); | |
591 | } | |
592 | ||
593 | static int qup_sg_set_buf(struct scatterlist *sg, void *buf, | |
685983f4 S |
594 | unsigned int buflen, struct qup_i2c_dev *qup, |
595 | int dir) | |
9cedf3b2 S |
596 | { |
597 | int ret; | |
598 | ||
599 | sg_set_buf(sg, buf, buflen); | |
600 | ret = dma_map_sg(qup->dev, sg, 1, dir); | |
601 | if (!ret) | |
602 | return -EINVAL; | |
603 | ||
9cedf3b2 S |
604 | return 0; |
605 | } | |
606 | ||
607 | static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) | |
608 | { | |
609 | if (qup->btx.dma) | |
610 | dma_release_channel(qup->btx.dma); | |
611 | if (qup->brx.dma) | |
612 | dma_release_channel(qup->brx.dma); | |
613 | qup->btx.dma = NULL; | |
614 | qup->brx.dma = NULL; | |
615 | } | |
616 | ||
617 | static int qup_i2c_req_dma(struct qup_i2c_dev *qup) | |
618 | { | |
619 | int err; | |
620 | ||
621 | if (!qup->btx.dma) { | |
622 | qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx"); | |
623 | if (IS_ERR(qup->btx.dma)) { | |
624 | err = PTR_ERR(qup->btx.dma); | |
625 | qup->btx.dma = NULL; | |
626 | dev_err(qup->dev, "\n tx channel not available"); | |
627 | return err; | |
628 | } | |
629 | } | |
630 | ||
631 | if (!qup->brx.dma) { | |
632 | qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx"); | |
633 | if (IS_ERR(qup->brx.dma)) { | |
634 | dev_err(qup->dev, "\n rx channel not available"); | |
635 | err = PTR_ERR(qup->brx.dma); | |
636 | qup->brx.dma = NULL; | |
637 | qup_i2c_rel_dma(qup); | |
638 | return err; | |
639 | } | |
640 | } | |
641 | return 0; | |
642 | } | |
643 | ||
6f2f0f64 | 644 | static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg) |
9cedf3b2 | 645 | { |
6f2f0f64 AS |
646 | int ret = 0, limit = QUP_READ_LIMIT; |
647 | u32 len = 0, blocks, rem; | |
648 | u32 i = 0, tlen, tx_len = 0; | |
9cedf3b2 S |
649 | u8 *tags; |
650 | ||
7545c7db | 651 | qup->blk_xfer_limit = QUP_READ_LIMIT; |
6f2f0f64 | 652 | qup_i2c_set_blk_data(qup, msg); |
9cedf3b2 | 653 | |
6f2f0f64 AS |
654 | blocks = qup->blk.count; |
655 | rem = msg->len - (blocks - 1) * limit; | |
9cedf3b2 | 656 | |
6f2f0f64 AS |
657 | if (msg->flags & I2C_M_RD) { |
658 | while (qup->blk.pos < blocks) { | |
659 | tlen = (i == (blocks - 1)) ? rem : limit; | |
660 | tags = &qup->start_tag.start[qup->tag_buf_pos + len]; | |
661 | len += qup_i2c_set_tags(tags, qup, msg); | |
662 | qup->blk.data_len -= tlen; | |
5c135e15 | 663 | |
6f2f0f64 AS |
664 | /* scratch buf to read the start and len tags */ |
665 | ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], | |
666 | &qup->brx.tag.start[0], | |
667 | 2, qup, DMA_FROM_DEVICE); | |
9cedf3b2 | 668 | |
6f2f0f64 AS |
669 | if (ret) |
670 | return ret; | |
9cedf3b2 | 671 | |
6f2f0f64 AS |
672 | ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], |
673 | &msg->buf[limit * i], | |
674 | tlen, qup, | |
675 | DMA_FROM_DEVICE); | |
676 | if (ret) | |
677 | return ret; | |
9cedf3b2 | 678 | |
6f2f0f64 AS |
679 | i++; |
680 | qup->blk.pos = i; | |
681 | } | |
682 | ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], | |
683 | &qup->start_tag.start[qup->tag_buf_pos], | |
684 | len, qup, DMA_TO_DEVICE); | |
685 | if (ret) | |
686 | return ret; | |
9cedf3b2 | 687 | |
6f2f0f64 AS |
688 | qup->tag_buf_pos += len; |
689 | } else { | |
690 | while (qup->blk.pos < blocks) { | |
691 | tlen = (i == (blocks - 1)) ? rem : limit; | |
692 | tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; | |
693 | len = qup_i2c_set_tags(tags, qup, msg); | |
694 | qup->blk.data_len -= tlen; | |
695 | ||
696 | ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], | |
697 | tags, len, | |
698 | qup, DMA_TO_DEVICE); | |
9cedf3b2 S |
699 | if (ret) |
700 | return ret; | |
701 | ||
6f2f0f64 AS |
702 | tx_len += len; |
703 | ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], | |
704 | &msg->buf[limit * i], | |
705 | tlen, qup, DMA_TO_DEVICE); | |
706 | if (ret) | |
707 | return ret; | |
708 | i++; | |
709 | qup->blk.pos = i; | |
9cedf3b2 | 710 | } |
6f2f0f64 AS |
711 | |
712 | qup->tag_buf_pos += tx_len; | |
9cedf3b2 S |
713 | } |
714 | ||
6f2f0f64 AS |
715 | return 0; |
716 | } | |
717 | ||
718 | static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup) | |
719 | { | |
720 | struct dma_async_tx_descriptor *txd, *rxd = NULL; | |
721 | int ret = 0; | |
722 | dma_cookie_t cookie_rx, cookie_tx; | |
723 | u32 len = 0; | |
724 | u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; | |
725 | ||
c5adc0fa AS |
726 | /* schedule the EOT and FLUSH I2C tags */ |
727 | len = 1; | |
728 | if (rx_cnt) { | |
729 | qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; | |
730 | len++; | |
731 | ||
7e6c35fe | 732 | /* scratch buf to read the BAM EOT FLUSH tags */ |
c5adc0fa AS |
733 | ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], |
734 | &qup->brx.tag.start[0], | |
7e6c35fe | 735 | 1, qup, DMA_FROM_DEVICE); |
c5adc0fa AS |
736 | if (ret) |
737 | return ret; | |
738 | } | |
739 | ||
740 | qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; | |
741 | ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], | |
742 | len, qup, DMA_TO_DEVICE); | |
743 | if (ret) | |
744 | return ret; | |
745 | ||
6d5f37f1 | 746 | txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, |
9cedf3b2 S |
747 | DMA_MEM_TO_DEV, |
748 | DMA_PREP_INTERRUPT | DMA_PREP_FENCE); | |
749 | if (!txd) { | |
750 | dev_err(qup->dev, "failed to get tx desc\n"); | |
751 | ret = -EINVAL; | |
752 | goto desc_err; | |
753 | } | |
754 | ||
6d5f37f1 | 755 | if (!rx_cnt) { |
9cedf3b2 S |
756 | txd->callback = qup_i2c_bam_cb; |
757 | txd->callback_param = qup; | |
758 | } | |
759 | ||
760 | cookie_tx = dmaengine_submit(txd); | |
761 | if (dma_submit_error(cookie_tx)) { | |
762 | ret = -EINVAL; | |
763 | goto desc_err; | |
764 | } | |
765 | ||
766 | dma_async_issue_pending(qup->btx.dma); | |
767 | ||
6d5f37f1 | 768 | if (rx_cnt) { |
9cedf3b2 | 769 | rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, |
6d5f37f1 | 770 | rx_cnt, DMA_DEV_TO_MEM, |
9cedf3b2 S |
771 | DMA_PREP_INTERRUPT); |
772 | if (!rxd) { | |
773 | dev_err(qup->dev, "failed to get rx desc\n"); | |
774 | ret = -EINVAL; | |
775 | ||
776 | /* abort TX descriptors */ | |
777 | dmaengine_terminate_all(qup->btx.dma); | |
778 | goto desc_err; | |
779 | } | |
780 | ||
781 | rxd->callback = qup_i2c_bam_cb; | |
782 | rxd->callback_param = qup; | |
783 | cookie_rx = dmaengine_submit(rxd); | |
784 | if (dma_submit_error(cookie_rx)) { | |
785 | ret = -EINVAL; | |
786 | goto desc_err; | |
787 | } | |
788 | ||
789 | dma_async_issue_pending(qup->brx.dma); | |
790 | } | |
791 | ||
ecb6e1e5 | 792 | if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) { |
9cedf3b2 S |
793 | dev_err(qup->dev, "normal trans timed out\n"); |
794 | ret = -ETIMEDOUT; | |
795 | } | |
796 | ||
797 | if (ret || qup->bus_err || qup->qup_err) { | |
7239872f AS |
798 | reinit_completion(&qup->xfer); |
799 | ||
fbf9921f S |
800 | if (qup_i2c_change_state(qup, QUP_RUN_STATE)) { |
801 | dev_err(qup->dev, "change to run state timed out"); | |
802 | goto desc_err; | |
803 | } | |
9cedf3b2 | 804 | |
fbf9921f | 805 | qup_i2c_flush(qup); |
9cedf3b2 | 806 | |
fbf9921f S |
807 | /* wait for remaining interrupts to occur */ |
808 | if (!wait_for_completion_timeout(&qup->xfer, HZ)) | |
809 | dev_err(qup->dev, "flush timed out\n"); | |
9cedf3b2 | 810 | |
fbf9921f | 811 | ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; |
9cedf3b2 S |
812 | } |
813 | ||
fbf9921f | 814 | desc_err: |
6d5f37f1 | 815 | dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); |
9cedf3b2 | 816 | |
6d5f37f1 AS |
817 | if (rx_cnt) |
818 | dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, | |
9cedf3b2 | 819 | DMA_FROM_DEVICE); |
fbf9921f | 820 | |
9cedf3b2 S |
821 | return ret; |
822 | } | |
823 | ||
6f2f0f64 AS |
824 | static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup) |
825 | { | |
826 | qup->btx.sg_cnt = 0; | |
827 | qup->brx.sg_cnt = 0; | |
828 | qup->tag_buf_pos = 0; | |
829 | } | |
830 | ||
9cedf3b2 S |
831 | static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, |
832 | int num) | |
833 | { | |
834 | struct qup_i2c_dev *qup = i2c_get_adapdata(adap); | |
835 | int ret = 0; | |
6f2f0f64 | 836 | int idx = 0; |
9cedf3b2 S |
837 | |
838 | enable_irq(qup->irq); | |
839 | ret = qup_i2c_req_dma(qup); | |
840 | ||
841 | if (ret) | |
842 | goto out; | |
843 | ||
9cedf3b2 S |
844 | writel(0, qup->base + QUP_MX_INPUT_CNT); |
845 | writel(0, qup->base + QUP_MX_OUTPUT_CNT); | |
846 | ||
847 | /* set BAM mode */ | |
848 | writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); | |
849 | ||
850 | /* mask fifo irqs */ | |
851 | writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); | |
852 | ||
853 | /* set RUN STATE */ | |
854 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
855 | if (ret) | |
856 | goto out; | |
857 | ||
858 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
6f2f0f64 AS |
859 | qup_i2c_bam_clear_tag_buffers(qup); |
860 | ||
861 | for (idx = 0; idx < num; idx++) { | |
862 | qup->msg = msg + idx; | |
863 | qup->is_last = idx == (num - 1); | |
864 | ||
865 | ret = qup_i2c_bam_make_desc(qup, qup->msg); | |
866 | if (ret) | |
867 | break; | |
868 | ||
869 | /* | |
870 | * Make DMA descriptor and schedule the BAM transfer if its | |
871 | * already crossed the maximum length. Since the memory for all | |
872 | * tags buffers have been taken for 2 maximum possible | |
873 | * transfers length so it will never cross the buffer actual | |
874 | * length. | |
875 | */ | |
876 | if (qup->btx.sg_cnt > qup->max_xfer_sg_len || | |
877 | qup->brx.sg_cnt > qup->max_xfer_sg_len || | |
878 | qup->is_last) { | |
879 | ret = qup_i2c_bam_schedule_desc(qup); | |
880 | if (ret) | |
881 | break; | |
882 | ||
883 | qup_i2c_bam_clear_tag_buffers(qup); | |
884 | } | |
885 | } | |
9cedf3b2 | 886 | |
9cedf3b2 S |
887 | out: |
888 | disable_irq(qup->irq); | |
889 | ||
890 | qup->msg = NULL; | |
891 | return ret; | |
892 | } | |
893 | ||
191424bb S |
894 | static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, |
895 | struct i2c_msg *msg) | |
10c5a842 BA |
896 | { |
897 | unsigned long left; | |
191424bb S |
898 | int ret = 0; |
899 | ||
7545c7db | 900 | left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); |
191424bb S |
901 | if (!left) { |
902 | writel(1, qup->base + QUP_SW_RESET); | |
903 | ret = -ETIMEDOUT; | |
904 | } | |
905 | ||
fbf9921f S |
906 | if (qup->bus_err || qup->qup_err) |
907 | ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; | |
191424bb S |
908 | |
909 | return ret; | |
910 | } | |
911 | ||
fbfab1ab | 912 | static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup) |
10c5a842 | 913 | { |
fbfab1ab AS |
914 | struct qup_i2c_block *blk = &qup->blk; |
915 | struct i2c_msg *msg = qup->msg; | |
10c5a842 | 916 | u32 val = 0; |
fbfab1ab | 917 | int idx = 0; |
10c5a842 | 918 | |
fbfab1ab | 919 | while (blk->fifo_available && qup->pos < msg->len) { |
10c5a842 | 920 | if ((idx & 1) == 0) { |
10c5a842 BA |
921 | /* Reading 2 words at time */ |
922 | val = readl(qup->base + QUP_IN_FIFO_BASE); | |
10c5a842 BA |
923 | msg->buf[qup->pos++] = val & 0xFF; |
924 | } else { | |
925 | msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; | |
926 | } | |
fbfab1ab AS |
927 | idx++; |
928 | blk->fifo_available--; | |
10c5a842 | 929 | } |
c4f0c5fb | 930 | |
fbfab1ab AS |
931 | if (qup->pos == msg->len) |
932 | blk->rx_bytes_read = true; | |
10c5a842 BA |
933 | } |
934 | ||
fbfab1ab | 935 | static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup) |
10c5a842 | 936 | { |
fbfab1ab AS |
937 | struct i2c_msg *msg = qup->msg; |
938 | u32 addr, len, val; | |
10c5a842 | 939 | |
fbfab1ab | 940 | addr = i2c_8bit_addr_from_msg(msg); |
10c5a842 | 941 | |
fbfab1ab AS |
942 | /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */ |
943 | len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; | |
944 | ||
945 | val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr; | |
946 | writel(val, qup->base + QUP_OUT_FIFO_BASE); | |
947 | } | |
948 | ||
949 | static void qup_i2c_conf_v1(struct qup_i2c_dev *qup) | |
950 | { | |
951 | struct qup_i2c_block *blk = &qup->blk; | |
952 | u32 qup_config = I2C_MINI_CORE | I2C_N_VAL; | |
953 | u32 io_mode = QUP_REPACK_EN; | |
954 | ||
955 | blk->is_tx_blk_mode = | |
956 | blk->total_tx_len > qup->out_fifo_sz ? true : false; | |
957 | blk->is_rx_blk_mode = | |
958 | blk->total_rx_len > qup->in_fifo_sz ? true : false; | |
959 | ||
960 | if (blk->is_tx_blk_mode) { | |
961 | io_mode |= QUP_OUTPUT_BLK_MODE; | |
962 | writel(0, qup->base + QUP_MX_WRITE_CNT); | |
963 | writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); | |
964 | } else { | |
965 | writel(0, qup->base + QUP_MX_OUTPUT_CNT); | |
966 | writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); | |
967 | } | |
968 | ||
969 | if (blk->total_rx_len) { | |
970 | if (blk->is_rx_blk_mode) { | |
971 | io_mode |= QUP_INPUT_BLK_MODE; | |
972 | writel(0, qup->base + QUP_MX_READ_CNT); | |
973 | writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); | |
974 | } else { | |
975 | writel(0, qup->base + QUP_MX_INPUT_CNT); | |
976 | writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); | |
977 | } | |
978 | } else { | |
979 | qup_config |= QUP_NO_INPUT; | |
980 | } | |
981 | ||
982 | writel(qup_config, qup->base + QUP_CONFIG); | |
983 | writel(io_mode, qup->base + QUP_IO_MODE); | |
984 | } | |
10c5a842 | 985 | |
fbfab1ab AS |
986 | static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk) |
987 | { | |
988 | blk->tx_fifo_free = 0; | |
989 | blk->fifo_available = 0; | |
990 | blk->rx_bytes_read = false; | |
991 | } | |
992 | ||
993 | static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx) | |
994 | { | |
995 | struct qup_i2c_block *blk = &qup->blk; | |
996 | int ret; | |
997 | ||
998 | qup_i2c_clear_blk_v1(blk); | |
999 | qup_i2c_conf_v1(qup); | |
10c5a842 BA |
1000 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); |
1001 | if (ret) | |
fbfab1ab | 1002 | return ret; |
10c5a842 BA |
1003 | |
1004 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
1005 | ||
1006 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
1007 | if (ret) | |
fbfab1ab AS |
1008 | return ret; |
1009 | ||
1010 | reinit_completion(&qup->xfer); | |
1011 | enable_irq(qup->irq); | |
1012 | if (!blk->is_tx_blk_mode) { | |
1013 | blk->tx_fifo_free = qup->out_fifo_sz; | |
10c5a842 | 1014 | |
fbfab1ab AS |
1015 | if (is_rx) |
1016 | qup_i2c_write_rx_tags_v1(qup); | |
1017 | else | |
1018 | qup_i2c_write_tx_fifo_v1(qup); | |
1019 | } | |
10c5a842 BA |
1020 | |
1021 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
1022 | if (ret) | |
1023 | goto err; | |
1024 | ||
fbfab1ab AS |
1025 | ret = qup_i2c_wait_for_complete(qup, qup->msg); |
1026 | if (ret) | |
1027 | goto err; | |
10c5a842 | 1028 | |
fbfab1ab | 1029 | ret = qup_i2c_bus_active(qup, ONE_BYTE); |
10c5a842 BA |
1030 | |
1031 | err: | |
1032 | disable_irq(qup->irq); | |
10c5a842 BA |
1033 | return ret; |
1034 | } | |
1035 | ||
fbfab1ab AS |
1036 | static int qup_i2c_write_one(struct qup_i2c_dev *qup) |
1037 | { | |
1038 | struct i2c_msg *msg = qup->msg; | |
1039 | struct qup_i2c_block *blk = &qup->blk; | |
1040 | ||
1041 | qup->pos = 0; | |
1042 | blk->total_tx_len = msg->len + 1; | |
1043 | blk->total_rx_len = 0; | |
1044 | ||
1045 | return qup_i2c_conf_xfer_v1(qup, false); | |
1046 | } | |
1047 | ||
1048 | static int qup_i2c_read_one(struct qup_i2c_dev *qup) | |
1049 | { | |
1050 | struct qup_i2c_block *blk = &qup->blk; | |
1051 | ||
1052 | qup->pos = 0; | |
1053 | blk->total_tx_len = 2; | |
1054 | blk->total_rx_len = qup->msg->len; | |
1055 | ||
1056 | return qup_i2c_conf_xfer_v1(qup, true); | |
1057 | } | |
1058 | ||
10c5a842 BA |
1059 | static int qup_i2c_xfer(struct i2c_adapter *adap, |
1060 | struct i2c_msg msgs[], | |
1061 | int num) | |
1062 | { | |
1063 | struct qup_i2c_dev *qup = i2c_get_adapdata(adap); | |
1064 | int ret, idx; | |
1065 | ||
1066 | ret = pm_runtime_get_sync(qup->dev); | |
fa01d096 | 1067 | if (ret < 0) |
10c5a842 BA |
1068 | goto out; |
1069 | ||
fbf9921f S |
1070 | qup->bus_err = 0; |
1071 | qup->qup_err = 0; | |
1072 | ||
10c5a842 BA |
1073 | writel(1, qup->base + QUP_SW_RESET); |
1074 | ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); | |
1075 | if (ret) | |
1076 | goto out; | |
1077 | ||
1078 | /* Configure QUP as I2C mini core */ | |
1079 | writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); | |
1080 | ||
1081 | for (idx = 0; idx < num; idx++) { | |
1082 | if (msgs[idx].len == 0) { | |
1083 | ret = -EINVAL; | |
1084 | goto out; | |
1085 | } | |
1086 | ||
1087 | if (qup_i2c_poll_state_i2c_master(qup)) { | |
1088 | ret = -EIO; | |
1089 | goto out; | |
1090 | } | |
1091 | ||
cc9086e7 NK |
1092 | if (qup_i2c_check_msg_len(&msgs[idx])) { |
1093 | ret = -EINVAL; | |
1094 | goto out; | |
1095 | } | |
1096 | ||
fbfab1ab | 1097 | qup->msg = &msgs[idx]; |
10c5a842 | 1098 | if (msgs[idx].flags & I2C_M_RD) |
fbfab1ab | 1099 | ret = qup_i2c_read_one(qup); |
10c5a842 | 1100 | else |
fbfab1ab | 1101 | ret = qup_i2c_write_one(qup); |
10c5a842 BA |
1102 | |
1103 | if (ret) | |
1104 | break; | |
1105 | ||
1106 | ret = qup_i2c_change_state(qup, QUP_RESET_STATE); | |
1107 | if (ret) | |
1108 | break; | |
1109 | } | |
1110 | ||
1111 | if (ret == 0) | |
1112 | ret = num; | |
1113 | out: | |
1114 | ||
1115 | pm_runtime_mark_last_busy(qup->dev); | |
1116 | pm_runtime_put_autosuspend(qup->dev); | |
1117 | ||
1118 | return ret; | |
1119 | } | |
1120 | ||
7545c7db AS |
1121 | /* |
1122 | * Configure registers related with reconfiguration during run and call it | |
1123 | * before each i2c sub transfer. | |
1124 | */ | |
1125 | static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup) | |
1126 | { | |
1127 | struct qup_i2c_block *blk = &qup->blk; | |
1128 | u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2; | |
1129 | ||
1130 | if (blk->is_tx_blk_mode) | |
1131 | writel(qup->config_run | blk->total_tx_len, | |
1132 | qup->base + QUP_MX_OUTPUT_CNT); | |
1133 | else | |
1134 | writel(qup->config_run | blk->total_tx_len, | |
1135 | qup->base + QUP_MX_WRITE_CNT); | |
1136 | ||
1137 | if (blk->total_rx_len) { | |
1138 | if (blk->is_rx_blk_mode) | |
1139 | writel(qup->config_run | blk->total_rx_len, | |
1140 | qup->base + QUP_MX_INPUT_CNT); | |
1141 | else | |
1142 | writel(qup->config_run | blk->total_rx_len, | |
1143 | qup->base + QUP_MX_READ_CNT); | |
1144 | } else { | |
1145 | qup_config |= QUP_NO_INPUT; | |
1146 | } | |
1147 | ||
1148 | writel(qup_config, qup->base + QUP_CONFIG); | |
1149 | } | |
1150 | ||
1151 | /* | |
1152 | * Configure registers related with transfer mode (FIFO/Block) | |
1153 | * before starting of i2c transfer. It will be called only once in | |
1154 | * QUP RESET state. | |
1155 | */ | |
1156 | static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup) | |
1157 | { | |
1158 | struct qup_i2c_block *blk = &qup->blk; | |
1159 | u32 io_mode = QUP_REPACK_EN; | |
1160 | ||
1161 | if (blk->is_tx_blk_mode) { | |
1162 | io_mode |= QUP_OUTPUT_BLK_MODE; | |
1163 | writel(0, qup->base + QUP_MX_WRITE_CNT); | |
1164 | } else { | |
1165 | writel(0, qup->base + QUP_MX_OUTPUT_CNT); | |
1166 | } | |
1167 | ||
1168 | if (blk->is_rx_blk_mode) { | |
1169 | io_mode |= QUP_INPUT_BLK_MODE; | |
1170 | writel(0, qup->base + QUP_MX_READ_CNT); | |
1171 | } else { | |
1172 | writel(0, qup->base + QUP_MX_INPUT_CNT); | |
1173 | } | |
1174 | ||
1175 | writel(io_mode, qup->base + QUP_IO_MODE); | |
1176 | } | |
1177 | ||
1178 | /* Clear required variables before starting of any QUP v2 sub transfer. */ | |
1179 | static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk) | |
1180 | { | |
1181 | blk->send_last_word = false; | |
1182 | blk->tx_tags_sent = false; | |
1183 | blk->tx_fifo_data = 0; | |
1184 | blk->tx_fifo_data_pos = 0; | |
1185 | blk->tx_fifo_free = 0; | |
1186 | ||
1187 | blk->rx_tags_fetched = false; | |
1188 | blk->rx_bytes_read = false; | |
1189 | blk->rx_fifo_data = 0; | |
1190 | blk->rx_fifo_data_pos = 0; | |
1191 | blk->fifo_available = 0; | |
1192 | } | |
1193 | ||
1194 | /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */ | |
1195 | static void qup_i2c_recv_data(struct qup_i2c_dev *qup) | |
1196 | { | |
1197 | struct qup_i2c_block *blk = &qup->blk; | |
1198 | int j; | |
1199 | ||
1200 | for (j = blk->rx_fifo_data_pos; | |
1201 | blk->cur_blk_len && blk->fifo_available; | |
1202 | blk->cur_blk_len--, blk->fifo_available--) { | |
1203 | if (j == 0) | |
1204 | blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); | |
1205 | ||
1206 | *(blk->cur_data++) = blk->rx_fifo_data; | |
1207 | blk->rx_fifo_data >>= 8; | |
1208 | ||
1209 | if (j == 3) | |
1210 | j = 0; | |
1211 | else | |
1212 | j++; | |
1213 | } | |
1214 | ||
1215 | blk->rx_fifo_data_pos = j; | |
1216 | } | |
1217 | ||
1218 | /* Receive tags for read message in QUP v2 i2c transfer. */ | |
1219 | static void qup_i2c_recv_tags(struct qup_i2c_dev *qup) | |
1220 | { | |
1221 | struct qup_i2c_block *blk = &qup->blk; | |
1222 | ||
1223 | blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); | |
1224 | blk->rx_fifo_data >>= blk->rx_tag_len * 8; | |
1225 | blk->rx_fifo_data_pos = blk->rx_tag_len; | |
1226 | blk->fifo_available -= blk->rx_tag_len; | |
1227 | } | |
1228 | ||
1229 | /* | |
1230 | * Read the data and tags from RX FIFO. Since in read case, the tags will be | |
1231 | * preceded by received data bytes so | |
1232 | * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive | |
1233 | * all tag bytes and discard that. | |
1234 | * 2. Read the data from RX FIFO. When all the data bytes have been read then | |
1235 | * set rx_bytes_read to true. | |
1236 | */ | |
1237 | static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup) | |
1238 | { | |
1239 | struct qup_i2c_block *blk = &qup->blk; | |
1240 | ||
1241 | if (!blk->rx_tags_fetched) { | |
1242 | qup_i2c_recv_tags(qup); | |
1243 | blk->rx_tags_fetched = true; | |
1244 | } | |
1245 | ||
1246 | qup_i2c_recv_data(qup); | |
1247 | if (!blk->cur_blk_len) | |
1248 | blk->rx_bytes_read = true; | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO | |
1253 | * write works on word basis (4 bytes). Append new data byte write for TX FIFO | |
1254 | * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present. | |
1255 | */ | |
1256 | static void | |
1257 | qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len) | |
1258 | { | |
1259 | struct qup_i2c_block *blk = &qup->blk; | |
1260 | unsigned int j; | |
1261 | ||
1262 | for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; | |
1263 | (*len)--, blk->tx_fifo_free--) { | |
1264 | blk->tx_fifo_data |= *(*data)++ << (j * 8); | |
1265 | if (j == 3) { | |
1266 | writel(blk->tx_fifo_data, | |
1267 | qup->base + QUP_OUT_FIFO_BASE); | |
1268 | blk->tx_fifo_data = 0x0; | |
1269 | j = 0; | |
1270 | } else { | |
1271 | j++; | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | blk->tx_fifo_data_pos = j; | |
1276 | } | |
1277 | ||
1278 | /* Transfer tags for read message in QUP v2 i2c transfer. */ | |
1279 | static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup) | |
1280 | { | |
1281 | struct qup_i2c_block *blk = &qup->blk; | |
1282 | ||
1283 | qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); | |
1284 | if (blk->tx_fifo_data_pos) | |
1285 | writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * Write the data and tags in TX FIFO. Since in write case, both tags and data | |
1290 | * need to be written and QUP write tags can have maximum 256 data length, so | |
1291 | * | |
1292 | * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the | |
1293 | * tags to TX FIFO and set tx_tags_sent to true. | |
1294 | * 2. Check if send_last_word is true. It will be set when last few data bytes | |
1295 | * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO | |
1296 | * space. All this data bytes are available in tx_fifo_data so write this | |
1297 | * in FIFO. | |
1298 | * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero | |
1299 | * then more data is pending otherwise following 3 cases can be possible | |
1300 | * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block | |
1301 | * have been written in TX FIFO so nothing else is required. | |
1302 | * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data | |
1303 | * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write | |
1304 | * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free | |
1305 | * will be always greater than or equal to 4 bytes. | |
1306 | * c. tx_fifo_free is zero. In this case, last few bytes (less than 4 | |
1307 | * bytes) are copied to tx_fifo_data but couldn't be sent because of | |
1308 | * FIFO full so make send_last_word true. | |
1309 | */ | |
1310 | static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup) | |
1311 | { | |
1312 | struct qup_i2c_block *blk = &qup->blk; | |
1313 | ||
1314 | if (!blk->tx_tags_sent) { | |
1315 | qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, | |
1316 | &blk->tx_tag_len); | |
1317 | blk->tx_tags_sent = true; | |
1318 | } | |
1319 | ||
1320 | if (blk->send_last_word) | |
1321 | goto send_last_word; | |
1322 | ||
1323 | qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); | |
1324 | if (!blk->cur_blk_len) { | |
1325 | if (!blk->tx_fifo_data_pos) | |
1326 | return; | |
1327 | ||
1328 | if (blk->tx_fifo_free) | |
1329 | goto send_last_word; | |
1330 | ||
1331 | blk->send_last_word = true; | |
1332 | } | |
1333 | ||
1334 | return; | |
1335 | ||
1336 | send_last_word: | |
1337 | writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); | |
1338 | } | |
1339 | ||
1340 | /* | |
1341 | * Main transfer function which read or write i2c data. | |
1342 | * The QUP v2 supports reconfiguration during run in which multiple i2c sub | |
1343 | * transfers can be scheduled. | |
1344 | */ | |
1345 | static int | |
1346 | qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first, | |
1347 | bool change_pause_state) | |
1348 | { | |
1349 | struct qup_i2c_block *blk = &qup->blk; | |
1350 | struct i2c_msg *msg = qup->msg; | |
1351 | int ret; | |
1352 | ||
1353 | /* | |
1354 | * Check if its SMBus Block read for which the top level read will be | |
1355 | * done into 2 QUP reads. One with message length 1 while other one is | |
1356 | * with actual length. | |
1357 | */ | |
1358 | if (qup_i2c_check_msg_len(msg)) { | |
1359 | if (qup->is_smbus_read) { | |
1360 | /* | |
1361 | * If the message length is already read in | |
1362 | * the first byte of the buffer, account for | |
1363 | * that by setting the offset | |
1364 | */ | |
1365 | blk->cur_data += 1; | |
1366 | is_first = false; | |
1367 | } else { | |
1368 | change_pause_state = false; | |
1369 | } | |
1370 | } | |
1371 | ||
1372 | qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; | |
1373 | ||
1374 | qup_i2c_clear_blk_v2(blk); | |
1375 | qup_i2c_conf_count_v2(qup); | |
1376 | ||
1377 | /* If it is first sub transfer, then configure i2c bus clocks */ | |
1378 | if (is_first) { | |
1379 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
1380 | if (ret) | |
1381 | return ret; | |
1382 | ||
1383 | writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); | |
1384 | ||
1385 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
1386 | if (ret) | |
1387 | return ret; | |
1388 | } | |
1389 | ||
1390 | reinit_completion(&qup->xfer); | |
1391 | enable_irq(qup->irq); | |
1392 | /* | |
1393 | * In FIFO mode, tx FIFO can be written directly while in block mode the | |
1394 | * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt | |
1395 | */ | |
1396 | if (!blk->is_tx_blk_mode) { | |
1397 | blk->tx_fifo_free = qup->out_fifo_sz; | |
1398 | ||
1399 | if (is_rx) | |
1400 | qup_i2c_write_rx_tags_v2(qup); | |
1401 | else | |
1402 | qup_i2c_write_tx_fifo_v2(qup); | |
1403 | } | |
1404 | ||
1405 | ret = qup_i2c_change_state(qup, QUP_RUN_STATE); | |
1406 | if (ret) | |
1407 | goto err; | |
1408 | ||
1409 | ret = qup_i2c_wait_for_complete(qup, msg); | |
1410 | if (ret) | |
1411 | goto err; | |
1412 | ||
1413 | /* Move to pause state for all the transfers, except last one */ | |
1414 | if (change_pause_state) { | |
1415 | ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); | |
1416 | if (ret) | |
1417 | goto err; | |
1418 | } | |
1419 | ||
1420 | err: | |
1421 | disable_irq(qup->irq); | |
1422 | return ret; | |
1423 | } | |
1424 | ||
1425 | /* | |
1426 | * Transfer one read/write message in i2c transfer. It splits the message into | |
1427 | * multiple of blk_xfer_limit data length blocks and schedule each | |
1428 | * QUP block individually. | |
1429 | */ | |
1430 | static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx) | |
1431 | { | |
1432 | int ret = 0; | |
1433 | unsigned int data_len, i; | |
1434 | struct i2c_msg *msg = qup->msg; | |
1435 | struct qup_i2c_block *blk = &qup->blk; | |
1436 | u8 *msg_buf = msg->buf; | |
1437 | ||
1438 | qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; | |
1439 | qup_i2c_set_blk_data(qup, msg); | |
1440 | ||
1441 | for (i = 0; i < blk->count; i++) { | |
1442 | data_len = qup_i2c_get_data_len(qup); | |
1443 | blk->pos = i; | |
1444 | blk->cur_tx_tags = blk->tags; | |
1445 | blk->cur_blk_len = data_len; | |
1446 | blk->tx_tag_len = | |
1447 | qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); | |
1448 | ||
1449 | blk->cur_data = msg_buf; | |
1450 | ||
1451 | if (is_rx) { | |
1452 | blk->total_tx_len = blk->tx_tag_len; | |
1453 | blk->rx_tag_len = 2; | |
1454 | blk->total_rx_len = blk->rx_tag_len + data_len; | |
1455 | } else { | |
1456 | blk->total_tx_len = blk->tx_tag_len + data_len; | |
1457 | blk->total_rx_len = 0; | |
1458 | } | |
1459 | ||
1460 | ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i, | |
1461 | !qup->is_last || i < blk->count - 1); | |
1462 | if (ret) | |
1463 | return ret; | |
1464 | ||
1465 | /* Handle SMBus block read length */ | |
1466 | if (qup_i2c_check_msg_len(msg) && msg->len == 1 && | |
1467 | !qup->is_smbus_read) { | |
1468 | if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) | |
1469 | return -EPROTO; | |
1470 | ||
1471 | msg->len = msg->buf[0]; | |
1472 | qup->is_smbus_read = true; | |
1473 | ret = qup_i2c_xfer_v2_msg(qup, msg_id, true); | |
1474 | qup->is_smbus_read = false; | |
1475 | if (ret) | |
1476 | return ret; | |
1477 | ||
1478 | msg->len += 1; | |
1479 | } | |
1480 | ||
1481 | msg_buf += data_len; | |
1482 | blk->data_len -= qup->blk_xfer_limit; | |
1483 | } | |
1484 | ||
1485 | return ret; | |
1486 | } | |
1487 | ||
1488 | /* | |
1489 | * QUP v2 supports 3 modes | |
1490 | * Programmed IO using FIFO mode : Less than FIFO size | |
1491 | * Programmed IO using Block mode : Greater than FIFO size | |
1492 | * DMA using BAM : Appropriate for any transaction size but the address should | |
1493 | * be DMA applicable | |
1494 | * | |
1495 | * This function determines the mode which will be used for this transfer. An | |
1496 | * i2c transfer contains multiple message. Following are the rules to determine | |
1497 | * the mode used. | |
1498 | * 1. Determine complete length, maximum tx and rx length for complete transfer. | |
1499 | * 2. If complete transfer length is greater than fifo size then use the DMA | |
1500 | * mode. | |
1501 | * 3. In FIFO or block mode, tx and rx can operate in different mode so check | |
1502 | * for maximum tx and rx length to determine mode. | |
1503 | */ | |
1504 | static int | |
1505 | qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup, | |
1506 | struct i2c_msg msgs[], int num) | |
1507 | { | |
1508 | int idx; | |
1509 | bool no_dma = false; | |
1510 | unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0; | |
1511 | ||
1512 | /* All i2c_msgs should be transferred using either dma or cpu */ | |
1513 | for (idx = 0; idx < num; idx++) { | |
1514 | if (msgs[idx].len == 0) | |
1515 | return -EINVAL; | |
1516 | ||
1517 | if (msgs[idx].flags & I2C_M_RD) | |
1518 | max_rx_len = max_t(unsigned int, max_rx_len, | |
1519 | msgs[idx].len); | |
1520 | else | |
1521 | max_tx_len = max_t(unsigned int, max_tx_len, | |
1522 | msgs[idx].len); | |
1523 | ||
1524 | if (is_vmalloc_addr(msgs[idx].buf)) | |
1525 | no_dma = true; | |
1526 | ||
1527 | total_len += msgs[idx].len; | |
1528 | } | |
1529 | ||
1530 | if (!no_dma && qup->is_dma && | |
1531 | (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { | |
1532 | qup->use_dma = true; | |
1533 | } else { | |
1534 | qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - | |
1535 | QUP_MAX_TAGS_LEN ? true : false; | |
1536 | qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - | |
1537 | READ_RX_TAGS_LEN ? true : false; | |
1538 | } | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
191424bb S |
1543 | static int qup_i2c_xfer_v2(struct i2c_adapter *adap, |
1544 | struct i2c_msg msgs[], | |
1545 | int num) | |
1546 | { | |
1547 | struct qup_i2c_dev *qup = i2c_get_adapdata(adap); | |
08f15963 | 1548 | int ret, idx = 0; |
191424bb | 1549 | |
fbf9921f S |
1550 | qup->bus_err = 0; |
1551 | qup->qup_err = 0; | |
1552 | ||
191424bb S |
1553 | ret = pm_runtime_get_sync(qup->dev); |
1554 | if (ret < 0) | |
1555 | goto out; | |
1556 | ||
7545c7db AS |
1557 | ret = qup_i2c_determine_mode_v2(qup, msgs, num); |
1558 | if (ret) | |
1559 | goto out; | |
1560 | ||
191424bb S |
1561 | writel(1, qup->base + QUP_SW_RESET); |
1562 | ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); | |
1563 | if (ret) | |
1564 | goto out; | |
1565 | ||
1566 | /* Configure QUP as I2C mini core */ | |
1567 | writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); | |
1568 | writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); | |
1569 | ||
7545c7db AS |
1570 | if (qup_i2c_poll_state_i2c_master(qup)) { |
1571 | ret = -EIO; | |
1572 | goto out; | |
9cedf3b2 S |
1573 | } |
1574 | ||
7545c7db AS |
1575 | if (qup->use_dma) { |
1576 | reinit_completion(&qup->xfer); | |
1577 | ret = qup_i2c_bam_xfer(adap, &msgs[0], num); | |
1578 | qup->use_dma = false; | |
1579 | } else { | |
1580 | qup_i2c_conf_mode_v2(qup); | |
d4f56c77 | 1581 | |
7545c7db AS |
1582 | for (idx = 0; idx < num; idx++) { |
1583 | qup->msg = &msgs[idx]; | |
1584 | qup->is_last = idx == (num - 1); | |
191424bb | 1585 | |
7545c7db AS |
1586 | ret = qup_i2c_xfer_v2_msg(qup, idx, |
1587 | !!(msgs[idx].flags & I2C_M_RD)); | |
1588 | if (ret) | |
1589 | break; | |
191424bb | 1590 | } |
7545c7db AS |
1591 | qup->msg = NULL; |
1592 | } | |
191424bb | 1593 | |
7545c7db AS |
1594 | if (!ret) |
1595 | ret = qup_i2c_bus_active(qup, ONE_BYTE); | |
191424bb | 1596 | |
f7418793 | 1597 | if (!ret) |
7545c7db | 1598 | qup_i2c_change_state(qup, QUP_RESET_STATE); |
f7418793 | 1599 | |
191424bb S |
1600 | if (ret == 0) |
1601 | ret = num; | |
1602 | out: | |
1603 | pm_runtime_mark_last_busy(qup->dev); | |
1604 | pm_runtime_put_autosuspend(qup->dev); | |
1605 | ||
1606 | return ret; | |
1607 | } | |
1608 | ||
10c5a842 BA |
1609 | static u32 qup_i2c_func(struct i2c_adapter *adap) |
1610 | { | |
1611 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
1612 | } | |
1613 | ||
1614 | static const struct i2c_algorithm qup_i2c_algo = { | |
1615 | .master_xfer = qup_i2c_xfer, | |
1616 | .functionality = qup_i2c_func, | |
1617 | }; | |
1618 | ||
191424bb S |
1619 | static const struct i2c_algorithm qup_i2c_algo_v2 = { |
1620 | .master_xfer = qup_i2c_xfer_v2, | |
1621 | .functionality = qup_i2c_func, | |
1622 | }; | |
1623 | ||
994647db WS |
1624 | /* |
1625 | * The QUP block will issue a NACK and STOP on the bus when reaching | |
1626 | * the end of the read, the length of the read is specified as one byte | |
1627 | * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. | |
1628 | */ | |
ae3923a2 | 1629 | static const struct i2c_adapter_quirks qup_i2c_quirks = { |
994647db WS |
1630 | .max_read_len = QUP_READ_LIMIT, |
1631 | }; | |
1632 | ||
10c5a842 BA |
1633 | static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) |
1634 | { | |
1635 | clk_prepare_enable(qup->clk); | |
1636 | clk_prepare_enable(qup->pclk); | |
1637 | } | |
1638 | ||
1639 | static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) | |
1640 | { | |
1641 | u32 config; | |
1642 | ||
1643 | qup_i2c_change_state(qup, QUP_RESET_STATE); | |
1644 | clk_disable_unprepare(qup->clk); | |
1645 | config = readl(qup->base + QUP_CONFIG); | |
1646 | config |= QUP_CLOCK_AUTO_GATE; | |
1647 | writel(config, qup->base + QUP_CONFIG); | |
1648 | clk_disable_unprepare(qup->pclk); | |
1649 | } | |
1650 | ||
1651 | static int qup_i2c_probe(struct platform_device *pdev) | |
1652 | { | |
1653 | static const int blk_sizes[] = {4, 16, 32}; | |
10c5a842 BA |
1654 | struct qup_i2c_dev *qup; |
1655 | unsigned long one_bit_t; | |
1656 | struct resource *res; | |
1657 | u32 io_mode, hw_ver, size; | |
1658 | int ret, fs_div, hs_div; | |
515da746 NK |
1659 | u32 src_clk_freq = DEFAULT_SRC_CLK; |
1660 | u32 clk_freq = DEFAULT_CLK_FREQ; | |
9cedf3b2 | 1661 | int blocks; |
7545c7db | 1662 | bool is_qup_v1; |
10c5a842 BA |
1663 | |
1664 | qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); | |
1665 | if (!qup) | |
1666 | return -ENOMEM; | |
1667 | ||
1668 | qup->dev = &pdev->dev; | |
1669 | init_completion(&qup->xfer); | |
1670 | platform_set_drvdata(pdev, qup); | |
1671 | ||
515da746 NK |
1672 | ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); |
1673 | if (ret) { | |
1674 | dev_notice(qup->dev, "using default clock-frequency %d", | |
1675 | DEFAULT_CLK_FREQ); | |
1676 | } | |
10c5a842 | 1677 | |
191424bb S |
1678 | if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { |
1679 | qup->adap.algo = &qup_i2c_algo; | |
1680 | qup->adap.quirks = &qup_i2c_quirks; | |
7545c7db | 1681 | is_qup_v1 = true; |
191424bb S |
1682 | } else { |
1683 | qup->adap.algo = &qup_i2c_algo_v2; | |
7545c7db | 1684 | is_qup_v1 = false; |
9cedf3b2 S |
1685 | ret = qup_i2c_req_dma(qup); |
1686 | ||
1687 | if (ret == -EPROBE_DEFER) | |
1688 | goto fail_dma; | |
1689 | else if (ret != 0) | |
1690 | goto nodma; | |
1691 | ||
6f2f0f64 AS |
1692 | qup->max_xfer_sg_len = (MX_BLOCKS << 1); |
1693 | blocks = (MX_DMA_BLOCKS << 1) + 1; | |
a86854d0 KC |
1694 | qup->btx.sg = devm_kcalloc(&pdev->dev, |
1695 | blocks, sizeof(*qup->btx.sg), | |
9cedf3b2 S |
1696 | GFP_KERNEL); |
1697 | if (!qup->btx.sg) { | |
1698 | ret = -ENOMEM; | |
1699 | goto fail_dma; | |
1700 | } | |
1701 | sg_init_table(qup->btx.sg, blocks); | |
1702 | ||
a86854d0 KC |
1703 | qup->brx.sg = devm_kcalloc(&pdev->dev, |
1704 | blocks, sizeof(*qup->brx.sg), | |
9cedf3b2 S |
1705 | GFP_KERNEL); |
1706 | if (!qup->brx.sg) { | |
1707 | ret = -ENOMEM; | |
1708 | goto fail_dma; | |
1709 | } | |
1710 | sg_init_table(qup->brx.sg, blocks); | |
1711 | ||
1712 | /* 2 tag bytes for each block + 5 for start, stop tags */ | |
1713 | size = blocks * 2 + 5; | |
9cedf3b2 | 1714 | |
685983f4 S |
1715 | qup->start_tag.start = devm_kzalloc(&pdev->dev, |
1716 | size, GFP_KERNEL); | |
9cedf3b2 S |
1717 | if (!qup->start_tag.start) { |
1718 | ret = -ENOMEM; | |
1719 | goto fail_dma; | |
1720 | } | |
1721 | ||
685983f4 | 1722 | qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); |
9cedf3b2 S |
1723 | if (!qup->brx.tag.start) { |
1724 | ret = -ENOMEM; | |
1725 | goto fail_dma; | |
1726 | } | |
1727 | ||
685983f4 | 1728 | qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); |
9cedf3b2 S |
1729 | if (!qup->btx.tag.start) { |
1730 | ret = -ENOMEM; | |
1731 | goto fail_dma; | |
1732 | } | |
1733 | qup->is_dma = true; | |
191424bb S |
1734 | } |
1735 | ||
9cedf3b2 | 1736 | nodma: |
10c5a842 BA |
1737 | /* We support frequencies up to FAST Mode (400KHz) */ |
1738 | if (!clk_freq || clk_freq > 400000) { | |
1739 | dev_err(qup->dev, "clock frequency not supported %d\n", | |
1740 | clk_freq); | |
1741 | return -EINVAL; | |
1742 | } | |
1743 | ||
1744 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1745 | qup->base = devm_ioremap_resource(qup->dev, res); | |
1746 | if (IS_ERR(qup->base)) | |
1747 | return PTR_ERR(qup->base); | |
1748 | ||
1749 | qup->irq = platform_get_irq(pdev, 0); | |
1750 | if (qup->irq < 0) { | |
1751 | dev_err(qup->dev, "No IRQ defined\n"); | |
1752 | return qup->irq; | |
1753 | } | |
1754 | ||
515da746 NK |
1755 | if (has_acpi_companion(qup->dev)) { |
1756 | ret = device_property_read_u32(qup->dev, | |
1757 | "src-clock-hz", &src_clk_freq); | |
1758 | if (ret) { | |
1759 | dev_notice(qup->dev, "using default src-clock-hz %d", | |
1760 | DEFAULT_SRC_CLK); | |
1761 | } | |
1762 | ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); | |
1763 | } else { | |
1764 | qup->clk = devm_clk_get(qup->dev, "core"); | |
1765 | if (IS_ERR(qup->clk)) { | |
1766 | dev_err(qup->dev, "Could not get core clock\n"); | |
1767 | return PTR_ERR(qup->clk); | |
1768 | } | |
10c5a842 | 1769 | |
515da746 NK |
1770 | qup->pclk = devm_clk_get(qup->dev, "iface"); |
1771 | if (IS_ERR(qup->pclk)) { | |
1772 | dev_err(qup->dev, "Could not get iface clock\n"); | |
1773 | return PTR_ERR(qup->pclk); | |
1774 | } | |
1775 | qup_i2c_enable_clocks(qup); | |
1776 | src_clk_freq = clk_get_rate(qup->clk); | |
10c5a842 BA |
1777 | } |
1778 | ||
10c5a842 BA |
1779 | /* |
1780 | * Bootloaders might leave a pending interrupt on certain QUP's, | |
1781 | * so we reset the core before registering for interrupts. | |
1782 | */ | |
1783 | writel(1, qup->base + QUP_SW_RESET); | |
1784 | ret = qup_i2c_poll_state_valid(qup); | |
1785 | if (ret) | |
1786 | goto fail; | |
1787 | ||
1788 | ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, | |
1789 | IRQF_TRIGGER_HIGH, "i2c_qup", qup); | |
1790 | if (ret) { | |
1791 | dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); | |
1792 | goto fail; | |
1793 | } | |
1794 | disable_irq(qup->irq); | |
1795 | ||
1796 | hw_ver = readl(qup->base + QUP_HW_VERSION); | |
1797 | dev_dbg(qup->dev, "Revision %x\n", hw_ver); | |
1798 | ||
1799 | io_mode = readl(qup->base + QUP_IO_MODE); | |
1800 | ||
1801 | /* | |
1802 | * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' | |
1803 | * associated with each byte written/received | |
1804 | */ | |
1805 | size = QUP_OUTPUT_BLOCK_SIZE(io_mode); | |
3cf357df PG |
1806 | if (size >= ARRAY_SIZE(blk_sizes)) { |
1807 | ret = -EIO; | |
1808 | goto fail; | |
1809 | } | |
7545c7db | 1810 | qup->out_blk_sz = blk_sizes[size]; |
10c5a842 BA |
1811 | |
1812 | size = QUP_INPUT_BLOCK_SIZE(io_mode); | |
3cf357df PG |
1813 | if (size >= ARRAY_SIZE(blk_sizes)) { |
1814 | ret = -EIO; | |
1815 | goto fail; | |
1816 | } | |
7545c7db AS |
1817 | qup->in_blk_sz = blk_sizes[size]; |
1818 | ||
1819 | if (is_qup_v1) { | |
1820 | /* | |
1821 | * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a | |
1822 | * single transfer but the block size is in bytes so divide the | |
1823 | * in_blk_sz and out_blk_sz by 2 | |
1824 | */ | |
1825 | qup->in_blk_sz /= 2; | |
1826 | qup->out_blk_sz /= 2; | |
1827 | qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; | |
1828 | qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; | |
1829 | qup->write_rx_tags = qup_i2c_write_rx_tags_v1; | |
1830 | } else { | |
1831 | qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; | |
1832 | qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; | |
1833 | qup->write_rx_tags = qup_i2c_write_rx_tags_v2; | |
1834 | } | |
10c5a842 BA |
1835 | |
1836 | size = QUP_OUTPUT_FIFO_SIZE(io_mode); | |
1837 | qup->out_fifo_sz = qup->out_blk_sz * (2 << size); | |
1838 | ||
1839 | size = QUP_INPUT_FIFO_SIZE(io_mode); | |
1840 | qup->in_fifo_sz = qup->in_blk_sz * (2 << size); | |
1841 | ||
10c5a842 BA |
1842 | fs_div = ((src_clk_freq / clk_freq) / 2) - 3; |
1843 | hs_div = 3; | |
1844 | qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); | |
1845 | ||
1846 | /* | |
1847 | * Time it takes for a byte to be clocked out on the bus. | |
1848 | * Each byte takes 9 clock cycles (8 bits + 1 ack). | |
1849 | */ | |
1850 | one_bit_t = (USEC_PER_SEC / clk_freq) + 1; | |
1851 | qup->one_byte_t = one_bit_t * 9; | |
ecb6e1e5 | 1852 | qup->xfer_timeout = TOUT_MIN * HZ + |
6f2f0f64 | 1853 | usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); |
10c5a842 BA |
1854 | |
1855 | dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", | |
1856 | qup->in_blk_sz, qup->in_fifo_sz, | |
1857 | qup->out_blk_sz, qup->out_fifo_sz); | |
1858 | ||
1859 | i2c_set_adapdata(&qup->adap, qup); | |
10c5a842 BA |
1860 | qup->adap.dev.parent = qup->dev; |
1861 | qup->adap.dev.of_node = pdev->dev.of_node; | |
9cedf3b2 | 1862 | qup->is_last = true; |
f7418793 | 1863 | |
10c5a842 BA |
1864 | strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); |
1865 | ||
10c5a842 BA |
1866 | pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); |
1867 | pm_runtime_use_autosuspend(qup->dev); | |
1868 | pm_runtime_set_active(qup->dev); | |
1869 | pm_runtime_enable(qup->dev); | |
86b59bbf AG |
1870 | |
1871 | ret = i2c_add_adapter(&qup->adap); | |
1872 | if (ret) | |
1873 | goto fail_runtime; | |
1874 | ||
10c5a842 BA |
1875 | return 0; |
1876 | ||
86b59bbf AG |
1877 | fail_runtime: |
1878 | pm_runtime_disable(qup->dev); | |
1879 | pm_runtime_set_suspended(qup->dev); | |
10c5a842 BA |
1880 | fail: |
1881 | qup_i2c_disable_clocks(qup); | |
9cedf3b2 S |
1882 | fail_dma: |
1883 | if (qup->btx.dma) | |
1884 | dma_release_channel(qup->btx.dma); | |
1885 | if (qup->brx.dma) | |
1886 | dma_release_channel(qup->brx.dma); | |
10c5a842 BA |
1887 | return ret; |
1888 | } | |
1889 | ||
1890 | static int qup_i2c_remove(struct platform_device *pdev) | |
1891 | { | |
1892 | struct qup_i2c_dev *qup = platform_get_drvdata(pdev); | |
1893 | ||
9cedf3b2 | 1894 | if (qup->is_dma) { |
9cedf3b2 S |
1895 | dma_release_channel(qup->btx.dma); |
1896 | dma_release_channel(qup->brx.dma); | |
1897 | } | |
1898 | ||
10c5a842 BA |
1899 | disable_irq(qup->irq); |
1900 | qup_i2c_disable_clocks(qup); | |
1901 | i2c_del_adapter(&qup->adap); | |
1902 | pm_runtime_disable(qup->dev); | |
1903 | pm_runtime_set_suspended(qup->dev); | |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | #ifdef CONFIG_PM | |
1908 | static int qup_i2c_pm_suspend_runtime(struct device *device) | |
1909 | { | |
1910 | struct qup_i2c_dev *qup = dev_get_drvdata(device); | |
1911 | ||
1912 | dev_dbg(device, "pm_runtime: suspending...\n"); | |
1913 | qup_i2c_disable_clocks(qup); | |
1914 | return 0; | |
1915 | } | |
1916 | ||
1917 | static int qup_i2c_pm_resume_runtime(struct device *device) | |
1918 | { | |
1919 | struct qup_i2c_dev *qup = dev_get_drvdata(device); | |
1920 | ||
1921 | dev_dbg(device, "pm_runtime: resuming...\n"); | |
1922 | qup_i2c_enable_clocks(qup); | |
1923 | return 0; | |
1924 | } | |
1925 | #endif | |
1926 | ||
1927 | #ifdef CONFIG_PM_SLEEP | |
1928 | static int qup_i2c_suspend(struct device *device) | |
1929 | { | |
331dcf42 SH |
1930 | if (!pm_runtime_suspended(device)) |
1931 | return qup_i2c_pm_suspend_runtime(device); | |
10c5a842 BA |
1932 | return 0; |
1933 | } | |
1934 | ||
1935 | static int qup_i2c_resume(struct device *device) | |
1936 | { | |
1937 | qup_i2c_pm_resume_runtime(device); | |
1938 | pm_runtime_mark_last_busy(device); | |
1939 | pm_request_autosuspend(device); | |
1940 | return 0; | |
1941 | } | |
1942 | #endif | |
1943 | ||
1944 | static const struct dev_pm_ops qup_i2c_qup_pm_ops = { | |
1945 | SET_SYSTEM_SLEEP_PM_OPS( | |
1946 | qup_i2c_suspend, | |
1947 | qup_i2c_resume) | |
1948 | SET_RUNTIME_PM_OPS( | |
1949 | qup_i2c_pm_suspend_runtime, | |
1950 | qup_i2c_pm_resume_runtime, | |
1951 | NULL) | |
1952 | }; | |
1953 | ||
1954 | static const struct of_device_id qup_i2c_dt_match[] = { | |
1955 | { .compatible = "qcom,i2c-qup-v1.1.1" }, | |
1956 | { .compatible = "qcom,i2c-qup-v2.1.1" }, | |
1957 | { .compatible = "qcom,i2c-qup-v2.2.1" }, | |
1958 | {} | |
1959 | }; | |
1960 | MODULE_DEVICE_TABLE(of, qup_i2c_dt_match); | |
1961 | ||
515da746 NK |
1962 | #if IS_ENABLED(CONFIG_ACPI) |
1963 | static const struct acpi_device_id qup_i2c_acpi_match[] = { | |
1964 | { "QCOM8010"}, | |
1965 | { }, | |
1966 | }; | |
1967 | MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match); | |
1968 | #endif | |
1969 | ||
10c5a842 BA |
1970 | static struct platform_driver qup_i2c_driver = { |
1971 | .probe = qup_i2c_probe, | |
1972 | .remove = qup_i2c_remove, | |
1973 | .driver = { | |
1974 | .name = "i2c_qup", | |
10c5a842 BA |
1975 | .pm = &qup_i2c_qup_pm_ops, |
1976 | .of_match_table = qup_i2c_dt_match, | |
515da746 | 1977 | .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match), |
10c5a842 BA |
1978 | }, |
1979 | }; | |
1980 | ||
1981 | module_platform_driver(qup_i2c_driver); | |
1982 | ||
1983 | MODULE_LICENSE("GPL v2"); | |
1984 | MODULE_ALIAS("platform:i2c_qup"); |