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Commit | Line | Data |
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6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
3c2b1ff3 WS |
4 | * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> |
5 | * Copyright (C) 2011-2015 Renesas Electronics Corporation | |
3d99beab WS |
6 | * |
7 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
8 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
9 | * | |
10 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
11 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
12 | * | |
6ccbe607 KM |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 15 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
16 | * |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
6ccbe607 KM |
21 | */ |
22 | #include <linux/clk.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
6ccbe607 KM |
25 | #include <linux/interrupt.h> |
26 | #include <linux/io.h> | |
27 | #include <linux/i2c.h> | |
6ccbe607 KM |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
7679c0e1 | 30 | #include <linux/of_device.h> |
6ccbe607 KM |
31 | #include <linux/platform_device.h> |
32 | #include <linux/pm_runtime.h> | |
33 | #include <linux/slab.h> | |
6ccbe607 KM |
34 | |
35 | /* register offsets */ | |
36 | #define ICSCR 0x00 /* slave ctrl */ | |
37 | #define ICMCR 0x04 /* master ctrl */ | |
38 | #define ICSSR 0x08 /* slave status */ | |
39 | #define ICMSR 0x0C /* master status */ | |
40 | #define ICSIER 0x10 /* slave irq enable */ | |
41 | #define ICMIER 0x14 /* master irq enable */ | |
42 | #define ICCCR 0x18 /* clock dividers */ | |
43 | #define ICSAR 0x1C /* slave address */ | |
44 | #define ICMAR 0x20 /* master address */ | |
45 | #define ICRXTX 0x24 /* data port */ | |
46 | ||
de20d185 WS |
47 | /* ICSCR */ |
48 | #define SDBS (1 << 3) /* slave data buffer select */ | |
49 | #define SIE (1 << 2) /* slave interface enable */ | |
50 | #define GCAE (1 << 1) /* general call address enable */ | |
51 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
52 | ||
6ccbe607 KM |
53 | /* ICMCR */ |
54 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
55 | #define FSCL (1 << 6) /* override SCL pin */ | |
56 | #define FSDA (1 << 5) /* override SDA pin */ | |
57 | #define OBPC (1 << 4) /* override pins */ | |
58 | #define MIE (1 << 3) /* master if enable */ | |
59 | #define TSBE (1 << 2) | |
60 | #define FSB (1 << 1) /* force stop bit */ | |
61 | #define ESG (1 << 0) /* en startbit gen */ | |
62 | ||
de20d185 WS |
63 | /* ICSSR (also for ICSIER) */ |
64 | #define GCAR (1 << 6) /* general call received */ | |
65 | #define STM (1 << 5) /* slave transmit mode */ | |
66 | #define SSR (1 << 4) /* stop received */ | |
67 | #define SDE (1 << 3) /* slave data empty */ | |
68 | #define SDT (1 << 2) /* slave data transmitted */ | |
69 | #define SDR (1 << 1) /* slave data received */ | |
70 | #define SAR (1 << 0) /* slave addr received */ | |
71 | ||
3e3aabac | 72 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
73 | #define MNR (1 << 6) /* nack received */ |
74 | #define MAL (1 << 5) /* arbitration lost */ | |
75 | #define MST (1 << 4) /* sent a stop */ | |
76 | #define MDE (1 << 3) | |
77 | #define MDT (1 << 2) | |
78 | #define MDR (1 << 1) | |
79 | #define MAT (1 << 0) /* slave addr xfer done */ | |
80 | ||
6ccbe607 | 81 | |
4f443a8a WS |
82 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
83 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
52df445f | 84 | #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) |
4f443a8a | 85 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) |
6ccbe607 | 86 | |
3e3aabac WS |
87 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
88 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
89 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 90 | |
938916fb SS |
91 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
92 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 93 | |
6ccbe607 | 94 | #define ID_LAST_MSG (1 << 0) |
e49865d1 | 95 | #define ID_FIRST_MSG (1 << 1) |
6ccbe607 KM |
96 | #define ID_DONE (1 << 2) |
97 | #define ID_ARBLOST (1 << 3) | |
98 | #define ID_NACK (1 << 4) | |
7ee24eb5 WS |
99 | /* persistent flags */ |
100 | #define ID_P_PM_BLOCKED (1 << 31) | |
101 | #define ID_P_MASK ID_P_PM_BLOCKED | |
6ccbe607 | 102 | |
b720423a | 103 | enum rcar_i2c_type { |
043a3f11 KM |
104 | I2C_RCAR_GEN1, |
105 | I2C_RCAR_GEN2, | |
e7db0d34 | 106 | I2C_RCAR_GEN3, |
b720423a NVD |
107 | }; |
108 | ||
6ccbe607 KM |
109 | struct rcar_i2c_priv { |
110 | void __iomem *io; | |
111 | struct i2c_adapter adap; | |
b9d0684c WS |
112 | struct i2c_msg *msg; |
113 | int msgs_left; | |
bc8120f1 | 114 | struct clk *clk; |
6ccbe607 | 115 | |
6ccbe607 KM |
116 | wait_queue_head_t wait; |
117 | ||
118 | int pos; | |
6ccbe607 KM |
119 | u32 icccr; |
120 | u32 flags; | |
51371cdc | 121 | enum rcar_i2c_type devtype; |
de20d185 | 122 | struct i2c_client *slave; |
6ccbe607 KM |
123 | }; |
124 | ||
125 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
126 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
127 | ||
6ccbe607 KM |
128 | #define LOOP_TIMEOUT 1024 |
129 | ||
51371cdc | 130 | |
6ccbe607 KM |
131 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
132 | { | |
133 | writel(val, priv->io + reg); | |
134 | } | |
135 | ||
136 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
137 | { | |
138 | return readl(priv->io + reg); | |
139 | } | |
140 | ||
141 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
142 | { | |
6ccbe607 KM |
143 | /* reset master mode */ |
144 | rcar_i2c_write(priv, ICMIER, 0); | |
2c78cdc1 | 145 | rcar_i2c_write(priv, ICMCR, MDBS); |
6ccbe607 | 146 | rcar_i2c_write(priv, ICMSR, 0); |
2c78cdc1 WS |
147 | /* start clock */ |
148 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 KM |
149 | } |
150 | ||
6ccbe607 KM |
151 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
152 | { | |
153 | int i; | |
154 | ||
155 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
156 | /* make sure that bus is not busy */ | |
157 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
158 | return 0; | |
159 | udelay(1); | |
160 | } | |
161 | ||
162 | return -EBUSY; | |
163 | } | |
164 | ||
c7881871 | 165 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) |
6ccbe607 | 166 | { |
ca68eade | 167 | u32 scgd, cdf, round, ick, sum, scl, cdf_width; |
8d049403 | 168 | unsigned long rate; |
f9c9d31b | 169 | struct device *dev = rcar_i2c_priv_to_dev(priv); |
6ccbe607 | 170 | |
c7881871 WS |
171 | /* Fall back to previously used values if not supplied */ |
172 | t->bus_freq_hz = t->bus_freq_hz ?: 100000; | |
ca68eade WS |
173 | t->scl_fall_ns = t->scl_fall_ns ?: 35; |
174 | t->scl_rise_ns = t->scl_rise_ns ?: 200; | |
175 | t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; | |
6ccbe607 | 176 | |
b720423a | 177 | switch (priv->devtype) { |
043a3f11 | 178 | case I2C_RCAR_GEN1: |
b720423a NVD |
179 | cdf_width = 2; |
180 | break; | |
043a3f11 | 181 | case I2C_RCAR_GEN2: |
e7db0d34 | 182 | case I2C_RCAR_GEN3: |
b720423a NVD |
183 | cdf_width = 3; |
184 | break; | |
185 | default: | |
186 | dev_err(dev, "device type error\n"); | |
187 | return -EIO; | |
188 | } | |
189 | ||
6ccbe607 KM |
190 | /* |
191 | * calculate SCL clock | |
192 | * see | |
193 | * ICCCR | |
194 | * | |
195 | * ick = clkp / (1 + CDF) | |
196 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
197 | * | |
198 | * ick : I2C internal clock < 20 MHz | |
ca68eade WS |
199 | * ticf : I2C SCL falling time |
200 | * tr : I2C SCL rising time | |
201 | * intd : LSI internal delay | |
6ccbe607 KM |
202 | * clkp : peripheral_clk |
203 | * F[] : integer up-valuation | |
204 | */ | |
bc8120f1 | 205 | rate = clk_get_rate(priv->clk); |
8d049403 | 206 | cdf = rate / 20000000; |
22762ccb | 207 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
208 | dev_err(dev, "Input clock %lu too high\n", rate); |
209 | return -EIO; | |
6ccbe607 | 210 | } |
8d049403 | 211 | ick = rate / (cdf + 1); |
6ccbe607 | 212 | |
6ccbe607 KM |
213 | /* |
214 | * it is impossible to calculate large scale | |
215 | * number on u32. separate it | |
216 | * | |
ca68eade WS |
217 | * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) |
218 | * = F[sum * ick / 1000000000] | |
219 | * = F[(ick / 1000000) * sum / 1000] | |
6ccbe607 | 220 | */ |
ca68eade WS |
221 | sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; |
222 | round = (ick + 500000) / 1000000 * sum; | |
6ccbe607 KM |
223 | round = (round + 500) / 1000; |
224 | ||
225 | /* | |
226 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
227 | * | |
228 | * Calculation result (= SCL) should be less than | |
229 | * bus_speed for hardware safety | |
8d049403 GL |
230 | * |
231 | * We could use something along the lines of | |
232 | * div = ick / (bus_speed + 1) + 1; | |
233 | * scgd = (div - 20 - round + 7) / 8; | |
234 | * scl = ick / (20 + (scgd * 8) + round); | |
235 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
236 | */ |
237 | for (scgd = 0; scgd < 0x40; scgd++) { | |
238 | scl = ick / (20 + (scgd * 8) + round); | |
c7881871 | 239 | if (scl <= t->bus_freq_hz) |
6ccbe607 KM |
240 | goto scgd_find; |
241 | } | |
242 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
243 | return -EIO; | |
244 | ||
245 | scgd_find: | |
246 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
c7881871 | 247 | scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 | 248 | |
3c2b1ff3 | 249 | /* keep icccr value */ |
14d32f17 | 250 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
7c7117ff | 255 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 256 | { |
386babf8 | 257 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 258 | |
b9d0684c | 259 | priv->pos = 0; |
b9d0684c | 260 | if (priv->msgs_left == 1) |
42c0783b | 261 | priv->flags |= ID_LAST_MSG; |
b9d0684c | 262 | |
386babf8 | 263 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
e49865d1 WS |
264 | /* |
265 | * We don't have a testcase but the HW engineers say that the write order | |
266 | * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since | |
267 | * it didn't cause a drawback for me, let's rather be safe than sorry. | |
268 | */ | |
42c0783b | 269 | if (priv->flags & ID_FIRST_MSG) { |
e49865d1 WS |
270 | rcar_i2c_write(priv, ICMSR, 0); |
271 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
272 | } else { | |
273 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
274 | rcar_i2c_write(priv, ICMSR, 0); | |
275 | } | |
386babf8 | 276 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
277 | } |
278 | ||
cc21d0b4 WS |
279 | static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) |
280 | { | |
281 | priv->msg++; | |
282 | priv->msgs_left--; | |
7ee24eb5 | 283 | priv->flags &= ID_P_MASK; |
cc21d0b4 WS |
284 | rcar_i2c_prepare_msg(priv); |
285 | } | |
286 | ||
6ccbe607 KM |
287 | /* |
288 | * interrupt functions | |
289 | */ | |
cc21d0b4 | 290 | static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
291 | { |
292 | struct i2c_msg *msg = priv->msg; | |
293 | ||
3c2b1ff3 | 294 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 295 | if (!(msr & MDE)) |
cc21d0b4 | 296 | return; |
6ccbe607 KM |
297 | |
298 | if (priv->pos < msg->len) { | |
299 | /* | |
300 | * Prepare next data to ICRXTX register. | |
301 | * This data will go to _SHIFT_ register. | |
302 | * | |
303 | * * | |
304 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
305 | */ | |
306 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
307 | priv->pos++; | |
308 | ||
309 | } else { | |
310 | /* | |
311 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
312 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
313 | * | |
314 | * * | |
315 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
316 | */ | |
317 | ||
cc21d0b4 | 318 | if (priv->flags & ID_LAST_MSG) { |
6ccbe607 KM |
319 | /* |
320 | * If current msg is the _LAST_ msg, | |
321 | * prepare stop condition here. | |
322 | * ID_DONE will be set on STOP irq. | |
323 | */ | |
4f443a8a | 324 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
cc21d0b4 WS |
325 | } else { |
326 | rcar_i2c_next_msg(priv); | |
327 | return; | |
328 | } | |
6ccbe607 KM |
329 | } |
330 | ||
3c95de67 | 331 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
332 | } |
333 | ||
cc21d0b4 | 334 | static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
335 | { |
336 | struct i2c_msg *msg = priv->msg; | |
337 | ||
3c2b1ff3 | 338 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 339 | if (!(msr & MDR)) |
cc21d0b4 | 340 | return; |
6ccbe607 KM |
341 | |
342 | if (msr & MAT) { | |
52df445f | 343 | /* Address transfer phase finished, but no data at this point. */ |
6ccbe607 | 344 | } else if (priv->pos < msg->len) { |
3c2b1ff3 | 345 | /* get received data */ |
6ccbe607 KM |
346 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); |
347 | priv->pos++; | |
348 | } | |
349 | ||
350 | /* | |
3c2b1ff3 WS |
351 | * If next received data is the _LAST_, go to STOP phase. Might be |
352 | * overwritten by REP START when setting up a new msg. Not elegant | |
353 | * but the only stable sequence for REP START I have found so far. | |
6ccbe607 KM |
354 | */ |
355 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 356 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 357 | |
cc21d0b4 WS |
358 | if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) |
359 | rcar_i2c_next_msg(priv); | |
360 | else | |
361 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); | |
6ccbe607 KM |
362 | } |
363 | ||
de20d185 WS |
364 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
365 | { | |
366 | u32 ssr_raw, ssr_filtered; | |
367 | u8 value; | |
368 | ||
369 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
370 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
371 | ||
372 | if (!ssr_filtered) | |
373 | return false; | |
374 | ||
375 | /* address detected */ | |
376 | if (ssr_filtered & SAR) { | |
377 | /* read or write request */ | |
378 | if (ssr_raw & STM) { | |
5b77d162 | 379 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
380 | rcar_i2c_write(priv, ICRXTX, value); |
381 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
382 | } else { | |
5b77d162 | 383 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
384 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
385 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
386 | } | |
387 | ||
388 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
389 | } | |
390 | ||
391 | /* master sent stop */ | |
392 | if (ssr_filtered & SSR) { | |
393 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
394 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
395 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
396 | } | |
397 | ||
398 | /* master wants to write to us */ | |
399 | if (ssr_filtered & SDR) { | |
400 | int ret; | |
401 | ||
402 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 403 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
404 | /* Send NACK in case of error */ |
405 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
406 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
407 | } | |
408 | ||
409 | /* master wants to read from us */ | |
410 | if (ssr_filtered & SDE) { | |
5b77d162 | 411 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
412 | rcar_i2c_write(priv, ICRXTX, value); |
413 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
414 | } | |
415 | ||
416 | return true; | |
417 | } | |
418 | ||
6ccbe607 KM |
419 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
420 | { | |
421 | struct rcar_i2c_priv *priv = ptr; | |
52df445f | 422 | u32 msr, val; |
91bfe298 | 423 | |
52df445f WS |
424 | /* Clear START or STOP as soon as we can */ |
425 | val = rcar_i2c_read(priv, ICMCR); | |
426 | rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); | |
de20d185 | 427 | |
1c176d53 | 428 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 429 | |
dd318b0d SS |
430 | /* Only handle interrupts that are currently enabled */ |
431 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 | 432 | if (!msr) { |
c3be0af1 WS |
433 | if (rcar_i2c_slave_irq(priv)) |
434 | return IRQ_HANDLED; | |
435 | ||
436 | return IRQ_NONE; | |
aa5beaf6 | 437 | } |
dd318b0d | 438 | |
51371cdc | 439 | /* Arbitration lost */ |
6ccbe607 | 440 | if (msr & MAL) { |
42c0783b | 441 | priv->flags |= ID_DONE | ID_ARBLOST; |
6ccbe607 KM |
442 | goto out; |
443 | } | |
444 | ||
51371cdc | 445 | /* Nack */ |
6ccbe607 | 446 | if (msr & MNR) { |
d89667b1 | 447 | /* HW automatically sends STOP after received NACK */ |
f2382249 | 448 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
42c0783b | 449 | priv->flags |= ID_NACK; |
6ccbe607 KM |
450 | goto out; |
451 | } | |
452 | ||
dd318b0d SS |
453 | /* Stop */ |
454 | if (msr & MST) { | |
cc21d0b4 | 455 | priv->msgs_left--; /* The last message also made it */ |
42c0783b | 456 | priv->flags |= ID_DONE; |
dd318b0d SS |
457 | goto out; |
458 | } | |
459 | ||
6ccbe607 | 460 | if (rcar_i2c_is_recv(priv)) |
cc21d0b4 | 461 | rcar_i2c_irq_recv(priv, msr); |
6ccbe607 | 462 | else |
cc21d0b4 | 463 | rcar_i2c_irq_send(priv, msr); |
6ccbe607 KM |
464 | |
465 | out: | |
42c0783b | 466 | if (priv->flags & ID_DONE) { |
f2382249 | 467 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 468 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
469 | wake_up(&priv->wait); |
470 | } | |
471 | ||
c3be0af1 | 472 | return IRQ_HANDLED; |
6ccbe607 KM |
473 | } |
474 | ||
475 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
476 | struct i2c_msg *msgs, | |
477 | int num) | |
478 | { | |
479 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
480 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
b6763d0d | 481 | int i, ret; |
ff2316b8 | 482 | long time_left; |
6ccbe607 KM |
483 | |
484 | pm_runtime_get_sync(dev); | |
485 | ||
3f7de22e WS |
486 | ret = rcar_i2c_bus_barrier(priv); |
487 | if (ret < 0) | |
488 | goto out; | |
489 | ||
6ccbe607 | 490 | for (i = 0; i < num; i++) { |
d7653964 WS |
491 | /* This HW can't send STOP after address phase */ |
492 | if (msgs[i].len == 0) { | |
493 | ret = -EOPNOTSUPP; | |
cc21d0b4 | 494 | goto out; |
6ccbe607 | 495 | } |
cc21d0b4 | 496 | } |
6ccbe607 | 497 | |
e49865d1 | 498 | /* init first message */ |
cc21d0b4 WS |
499 | priv->msg = msgs; |
500 | priv->msgs_left = num; | |
7ee24eb5 | 501 | priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; |
cc21d0b4 WS |
502 | rcar_i2c_prepare_msg(priv); |
503 | ||
42c0783b | 504 | time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, |
cc21d0b4 WS |
505 | num * adap->timeout); |
506 | if (!time_left) { | |
507 | rcar_i2c_init(priv); | |
508 | ret = -ETIMEDOUT; | |
42c0783b | 509 | } else if (priv->flags & ID_NACK) { |
cc21d0b4 | 510 | ret = -ENXIO; |
42c0783b | 511 | } else if (priv->flags & ID_ARBLOST) { |
cc21d0b4 WS |
512 | ret = -EAGAIN; |
513 | } else { | |
514 | ret = num - priv->msgs_left; /* The number of transfer */ | |
6ccbe607 | 515 | } |
3f7de22e | 516 | out: |
6ccbe607 KM |
517 | pm_runtime_put(dev); |
518 | ||
6ff4b105 | 519 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
520 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
521 | ||
522 | return ret; | |
523 | } | |
524 | ||
de20d185 WS |
525 | static int rcar_reg_slave(struct i2c_client *slave) |
526 | { | |
527 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
528 | ||
529 | if (priv->slave) | |
530 | return -EBUSY; | |
531 | ||
532 | if (slave->flags & I2C_CLIENT_TEN) | |
533 | return -EAFNOSUPPORT; | |
534 | ||
b4cd08aa | 535 | pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
536 | |
537 | priv->slave = slave; | |
538 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
539 | rcar_i2c_write(priv, ICSSR, 0); | |
540 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
541 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static int rcar_unreg_slave(struct i2c_client *slave) | |
547 | { | |
548 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
549 | ||
550 | WARN_ON(!priv->slave); | |
551 | ||
552 | rcar_i2c_write(priv, ICSIER, 0); | |
553 | rcar_i2c_write(priv, ICSCR, 0); | |
554 | ||
555 | priv->slave = NULL; | |
556 | ||
b4cd08aa | 557 | pm_runtime_put(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
558 | |
559 | return 0; | |
560 | } | |
561 | ||
6ccbe607 KM |
562 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
563 | { | |
d7653964 | 564 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
1fb2ad95 WS |
565 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
566 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
567 | } |
568 | ||
569 | static const struct i2c_algorithm rcar_i2c_algo = { | |
570 | .master_xfer = rcar_i2c_master_xfer, | |
571 | .functionality = rcar_i2c_func, | |
de20d185 WS |
572 | .reg_slave = rcar_reg_slave, |
573 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
574 | }; |
575 | ||
7679c0e1 | 576 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
577 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
578 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
579 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
580 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 581 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
582 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
583 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
584 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 585 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
7679c0e1 GL |
586 | {}, |
587 | }; | |
588 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
589 | ||
0b255e92 | 590 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 591 | { |
6ccbe607 KM |
592 | struct rcar_i2c_priv *priv; |
593 | struct i2c_adapter *adap; | |
594 | struct resource *res; | |
595 | struct device *dev = &pdev->dev; | |
c7881871 | 596 | struct i2c_timings i2c_t; |
93e953d3 | 597 | int irq, ret; |
6ccbe607 | 598 | |
6ccbe607 | 599 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 600 | if (!priv) |
6ccbe607 | 601 | return -ENOMEM; |
6ccbe607 | 602 | |
bc8120f1 BD |
603 | priv->clk = devm_clk_get(dev, NULL); |
604 | if (IS_ERR(priv->clk)) { | |
605 | dev_err(dev, "cannot get clock\n"); | |
606 | return PTR_ERR(priv->clk); | |
607 | } | |
608 | ||
3cc2d009 | 609 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
610 | priv->io = devm_ioremap_resource(dev, res); |
611 | if (IS_ERR(priv->io)) | |
612 | return PTR_ERR(priv->io); | |
6ccbe607 | 613 | |
69e558fa | 614 | priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); |
6ccbe607 | 615 | init_waitqueue_head(&priv->wait); |
6ccbe607 | 616 | |
929e3aba WS |
617 | adap = &priv->adap; |
618 | adap->nr = pdev->id; | |
619 | adap->algo = &rcar_i2c_algo; | |
620 | adap->class = I2C_CLASS_DEPRECATED; | |
621 | adap->retries = 3; | |
622 | adap->dev.parent = dev; | |
623 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
624 | i2c_set_adapdata(adap, priv); |
625 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
626 | ||
c7881871 | 627 | i2c_parse_fw_timings(dev, &i2c_t, false); |
f9c9d31b WS |
628 | |
629 | pm_runtime_enable(dev); | |
630 | pm_runtime_get_sync(dev); | |
c7881871 | 631 | ret = rcar_i2c_clock_calculate(priv, &i2c_t); |
f9c9d31b WS |
632 | if (ret < 0) |
633 | goto out_pm_put; | |
634 | ||
635 | rcar_i2c_init(priv); | |
7ee24eb5 WS |
636 | |
637 | /* Don't suspend when multi-master to keep arbitration working */ | |
638 | if (of_property_read_bool(dev->of_node, "multi-master")) | |
639 | priv->flags |= ID_P_PM_BLOCKED; | |
640 | else | |
641 | pm_runtime_put(dev); | |
642 | ||
f9c9d31b WS |
643 | |
644 | irq = platform_get_irq(pdev, 0); | |
645 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); | |
6ccbe607 | 646 | if (ret < 0) { |
93e953d3 | 647 | dev_err(dev, "cannot get irq %d\n", irq); |
e43e0df1 | 648 | goto out_pm_disable; |
6ccbe607 KM |
649 | } |
650 | ||
4f7effdd WS |
651 | platform_set_drvdata(pdev, priv); |
652 | ||
6ccbe607 KM |
653 | ret = i2c_add_numbered_adapter(adap); |
654 | if (ret < 0) { | |
655 | dev_err(dev, "reg adap failed: %d\n", ret); | |
e43e0df1 | 656 | goto out_pm_disable; |
6ccbe607 KM |
657 | } |
658 | ||
6ccbe607 KM |
659 | dev_info(dev, "probed\n"); |
660 | ||
661 | return 0; | |
e43e0df1 WS |
662 | |
663 | out_pm_put: | |
664 | pm_runtime_put(dev); | |
665 | out_pm_disable: | |
666 | pm_runtime_disable(dev); | |
667 | return ret; | |
6ccbe607 KM |
668 | } |
669 | ||
0b255e92 | 670 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
671 | { |
672 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
673 | struct device *dev = &pdev->dev; | |
674 | ||
675 | i2c_del_adapter(&priv->adap); | |
7ee24eb5 WS |
676 | if (priv->flags & ID_P_PM_BLOCKED) |
677 | pm_runtime_put(dev); | |
6ccbe607 KM |
678 | pm_runtime_disable(dev); |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
45fd5e4a | 683 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
684 | .driver = { |
685 | .name = "i2c-rcar", | |
7679c0e1 | 686 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
687 | }, |
688 | .probe = rcar_i2c_probe, | |
0b255e92 | 689 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
690 | }; |
691 | ||
45fd5e4a | 692 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 693 | |
3d99beab | 694 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
695 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
696 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |