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Commit | Line | Data |
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6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
3d99beab WS |
4 | * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> |
5 | * | |
6 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
7 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
8 | * | |
9 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
10 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
11 | * | |
12 | * This file used out-of-tree driver i2c-rcar.c | |
13 | * Copyright (C) 2011-2012 Renesas Electronics Corporation | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 17 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
18 | * |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
6ccbe607 KM |
23 | */ |
24 | #include <linux/clk.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/err.h> | |
6ccbe607 KM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/i2c.h> | |
6ccbe607 KM |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
7679c0e1 | 32 | #include <linux/of_device.h> |
6ccbe607 KM |
33 | #include <linux/platform_device.h> |
34 | #include <linux/pm_runtime.h> | |
35 | #include <linux/slab.h> | |
91bfe298 | 36 | #include <linux/spinlock.h> |
6ccbe607 KM |
37 | |
38 | /* register offsets */ | |
39 | #define ICSCR 0x00 /* slave ctrl */ | |
40 | #define ICMCR 0x04 /* master ctrl */ | |
41 | #define ICSSR 0x08 /* slave status */ | |
42 | #define ICMSR 0x0C /* master status */ | |
43 | #define ICSIER 0x10 /* slave irq enable */ | |
44 | #define ICMIER 0x14 /* master irq enable */ | |
45 | #define ICCCR 0x18 /* clock dividers */ | |
46 | #define ICSAR 0x1C /* slave address */ | |
47 | #define ICMAR 0x20 /* master address */ | |
48 | #define ICRXTX 0x24 /* data port */ | |
49 | ||
de20d185 WS |
50 | /* ICSCR */ |
51 | #define SDBS (1 << 3) /* slave data buffer select */ | |
52 | #define SIE (1 << 2) /* slave interface enable */ | |
53 | #define GCAE (1 << 1) /* general call address enable */ | |
54 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
55 | ||
6ccbe607 KM |
56 | /* ICMCR */ |
57 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
58 | #define FSCL (1 << 6) /* override SCL pin */ | |
59 | #define FSDA (1 << 5) /* override SDA pin */ | |
60 | #define OBPC (1 << 4) /* override pins */ | |
61 | #define MIE (1 << 3) /* master if enable */ | |
62 | #define TSBE (1 << 2) | |
63 | #define FSB (1 << 1) /* force stop bit */ | |
64 | #define ESG (1 << 0) /* en startbit gen */ | |
65 | ||
de20d185 WS |
66 | /* ICSSR (also for ICSIER) */ |
67 | #define GCAR (1 << 6) /* general call received */ | |
68 | #define STM (1 << 5) /* slave transmit mode */ | |
69 | #define SSR (1 << 4) /* stop received */ | |
70 | #define SDE (1 << 3) /* slave data empty */ | |
71 | #define SDT (1 << 2) /* slave data transmitted */ | |
72 | #define SDR (1 << 1) /* slave data received */ | |
73 | #define SAR (1 << 0) /* slave addr received */ | |
74 | ||
3e3aabac | 75 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
76 | #define MNR (1 << 6) /* nack received */ |
77 | #define MAL (1 << 5) /* arbitration lost */ | |
78 | #define MST (1 << 4) /* sent a stop */ | |
79 | #define MDE (1 << 3) | |
80 | #define MDT (1 << 2) | |
81 | #define MDR (1 << 1) | |
82 | #define MAT (1 << 0) /* slave addr xfer done */ | |
83 | ||
6ccbe607 | 84 | |
4f443a8a WS |
85 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
86 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
87 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) | |
6ccbe607 | 88 | |
3e3aabac WS |
89 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
90 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
91 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 92 | |
938916fb SS |
93 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
94 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 95 | |
6ccbe607 KM |
96 | #define ID_LAST_MSG (1 << 0) |
97 | #define ID_IOERROR (1 << 1) | |
98 | #define ID_DONE (1 << 2) | |
99 | #define ID_ARBLOST (1 << 3) | |
100 | #define ID_NACK (1 << 4) | |
101 | ||
b720423a | 102 | enum rcar_i2c_type { |
043a3f11 KM |
103 | I2C_RCAR_GEN1, |
104 | I2C_RCAR_GEN2, | |
e7db0d34 | 105 | I2C_RCAR_GEN3, |
b720423a NVD |
106 | }; |
107 | ||
6ccbe607 KM |
108 | struct rcar_i2c_priv { |
109 | void __iomem *io; | |
110 | struct i2c_adapter adap; | |
111 | struct i2c_msg *msg; | |
bc8120f1 | 112 | struct clk *clk; |
6ccbe607 | 113 | |
91bfe298 | 114 | spinlock_t lock; |
6ccbe607 KM |
115 | wait_queue_head_t wait; |
116 | ||
117 | int pos; | |
6ccbe607 KM |
118 | u32 icccr; |
119 | u32 flags; | |
51371cdc | 120 | enum rcar_i2c_type devtype; |
de20d185 | 121 | struct i2c_client *slave; |
6ccbe607 KM |
122 | }; |
123 | ||
124 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
125 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
126 | ||
127 | #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) | |
128 | #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) | |
129 | ||
130 | #define LOOP_TIMEOUT 1024 | |
131 | ||
51371cdc | 132 | |
6ccbe607 KM |
133 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
134 | { | |
135 | writel(val, priv->io + reg); | |
136 | } | |
137 | ||
138 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
139 | { | |
140 | return readl(priv->io + reg); | |
141 | } | |
142 | ||
143 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
144 | { | |
6ccbe607 KM |
145 | /* reset master mode */ |
146 | rcar_i2c_write(priv, ICMIER, 0); | |
147 | rcar_i2c_write(priv, ICMCR, 0); | |
148 | rcar_i2c_write(priv, ICMSR, 0); | |
149 | rcar_i2c_write(priv, ICMAR, 0); | |
150 | } | |
151 | ||
6ccbe607 KM |
152 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
153 | { | |
154 | int i; | |
155 | ||
156 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
157 | /* make sure that bus is not busy */ | |
158 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
159 | return 0; | |
160 | udelay(1); | |
161 | } | |
162 | ||
163 | return -EBUSY; | |
164 | } | |
165 | ||
6ccbe607 KM |
166 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, |
167 | u32 bus_speed, | |
168 | struct device *dev) | |
169 | { | |
6ccbe607 KM |
170 | u32 scgd, cdf; |
171 | u32 round, ick; | |
172 | u32 scl; | |
b720423a | 173 | u32 cdf_width; |
8d049403 | 174 | unsigned long rate; |
6ccbe607 | 175 | |
b720423a | 176 | switch (priv->devtype) { |
043a3f11 | 177 | case I2C_RCAR_GEN1: |
b720423a NVD |
178 | cdf_width = 2; |
179 | break; | |
043a3f11 | 180 | case I2C_RCAR_GEN2: |
e7db0d34 | 181 | case I2C_RCAR_GEN3: |
b720423a NVD |
182 | cdf_width = 3; |
183 | break; | |
184 | default: | |
185 | dev_err(dev, "device type error\n"); | |
186 | return -EIO; | |
187 | } | |
188 | ||
6ccbe607 KM |
189 | /* |
190 | * calculate SCL clock | |
191 | * see | |
192 | * ICCCR | |
193 | * | |
194 | * ick = clkp / (1 + CDF) | |
195 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
196 | * | |
197 | * ick : I2C internal clock < 20 MHz | |
198 | * ticf : I2C SCL falling time = 35 ns here | |
199 | * tr : I2C SCL rising time = 200 ns here | |
200 | * intd : LSI internal delay = 50 ns here | |
201 | * clkp : peripheral_clk | |
202 | * F[] : integer up-valuation | |
203 | */ | |
bc8120f1 | 204 | rate = clk_get_rate(priv->clk); |
8d049403 | 205 | cdf = rate / 20000000; |
22762ccb | 206 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
207 | dev_err(dev, "Input clock %lu too high\n", rate); |
208 | return -EIO; | |
6ccbe607 | 209 | } |
8d049403 | 210 | ick = rate / (cdf + 1); |
6ccbe607 | 211 | |
6ccbe607 KM |
212 | /* |
213 | * it is impossible to calculate large scale | |
214 | * number on u32. separate it | |
215 | * | |
216 | * F[(ticf + tr + intd) * ick] | |
217 | * = F[(35 + 200 + 50)ns * ick] | |
218 | * = F[285 * ick / 1000000000] | |
219 | * = F[(ick / 1000000) * 285 / 1000] | |
220 | */ | |
221 | round = (ick + 500000) / 1000000 * 285; | |
222 | round = (round + 500) / 1000; | |
223 | ||
224 | /* | |
225 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
226 | * | |
227 | * Calculation result (= SCL) should be less than | |
228 | * bus_speed for hardware safety | |
8d049403 GL |
229 | * |
230 | * We could use something along the lines of | |
231 | * div = ick / (bus_speed + 1) + 1; | |
232 | * scgd = (div - 20 - round + 7) / 8; | |
233 | * scl = ick / (20 + (scgd * 8) + round); | |
234 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
235 | */ |
236 | for (scgd = 0; scgd < 0x40; scgd++) { | |
237 | scl = ick / (20 + (scgd * 8) + round); | |
238 | if (scl <= bus_speed) | |
239 | goto scgd_find; | |
240 | } | |
241 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
242 | return -EIO; | |
243 | ||
244 | scgd_find: | |
245 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
bc8120f1 | 246 | scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 KM |
247 | |
248 | /* | |
249 | * keep icccr value | |
250 | */ | |
14d32f17 | 251 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
252 | |
253 | return 0; | |
254 | } | |
255 | ||
7c7117ff | 256 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 257 | { |
386babf8 | 258 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 259 | |
386babf8 | 260 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
3c95de67 | 261 | rcar_i2c_write(priv, ICMSR, 0); |
4f443a8a | 262 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); |
386babf8 | 263 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
264 | } |
265 | ||
6ccbe607 KM |
266 | /* |
267 | * interrupt functions | |
268 | */ | |
269 | static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |
270 | { | |
271 | struct i2c_msg *msg = priv->msg; | |
272 | ||
273 | /* | |
274 | * FIXME | |
275 | * sometimes, unknown interrupt happened. | |
276 | * Do nothing | |
277 | */ | |
278 | if (!(msr & MDE)) | |
279 | return 0; | |
280 | ||
281 | /* | |
282 | * If address transfer phase finished, | |
283 | * goto data phase. | |
284 | */ | |
285 | if (msr & MAT) | |
4f443a8a | 286 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
6ccbe607 KM |
287 | |
288 | if (priv->pos < msg->len) { | |
289 | /* | |
290 | * Prepare next data to ICRXTX register. | |
291 | * This data will go to _SHIFT_ register. | |
292 | * | |
293 | * * | |
294 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
295 | */ | |
296 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
297 | priv->pos++; | |
298 | ||
299 | } else { | |
300 | /* | |
301 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
302 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
303 | * | |
304 | * * | |
305 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
306 | */ | |
307 | ||
308 | if (priv->flags & ID_LAST_MSG) | |
309 | /* | |
310 | * If current msg is the _LAST_ msg, | |
311 | * prepare stop condition here. | |
312 | * ID_DONE will be set on STOP irq. | |
313 | */ | |
4f443a8a | 314 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 KM |
315 | else |
316 | /* | |
317 | * If current msg is _NOT_ last msg, | |
318 | * it doesn't call stop phase. | |
319 | * thus, there is no STOP irq. | |
320 | * return ID_DONE here. | |
321 | */ | |
322 | return ID_DONE; | |
323 | } | |
324 | ||
3c95de67 | 325 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
330 | static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |
331 | { | |
332 | struct i2c_msg *msg = priv->msg; | |
333 | ||
334 | /* | |
335 | * FIXME | |
336 | * sometimes, unknown interrupt happened. | |
337 | * Do nothing | |
338 | */ | |
339 | if (!(msr & MDR)) | |
340 | return 0; | |
341 | ||
342 | if (msr & MAT) { | |
343 | /* | |
344 | * Address transfer phase finished, | |
345 | * but, there is no data at this point. | |
346 | * Do nothing. | |
347 | */ | |
348 | } else if (priv->pos < msg->len) { | |
349 | /* | |
350 | * get received data | |
351 | */ | |
352 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); | |
353 | priv->pos++; | |
354 | } | |
355 | ||
356 | /* | |
357 | * If next received data is the _LAST_, | |
358 | * go to STOP phase, | |
359 | * otherwise, go to DATA phase. | |
360 | */ | |
361 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 362 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 363 | else |
4f443a8a | 364 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
6ccbe607 | 365 | |
3c95de67 | 366 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); |
6ccbe607 KM |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
de20d185 WS |
371 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
372 | { | |
373 | u32 ssr_raw, ssr_filtered; | |
374 | u8 value; | |
375 | ||
376 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
377 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
378 | ||
379 | if (!ssr_filtered) | |
380 | return false; | |
381 | ||
382 | /* address detected */ | |
383 | if (ssr_filtered & SAR) { | |
384 | /* read or write request */ | |
385 | if (ssr_raw & STM) { | |
5b77d162 | 386 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
387 | rcar_i2c_write(priv, ICRXTX, value); |
388 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
389 | } else { | |
5b77d162 | 390 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
391 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
392 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
393 | } | |
394 | ||
395 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
396 | } | |
397 | ||
398 | /* master sent stop */ | |
399 | if (ssr_filtered & SSR) { | |
400 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
401 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
402 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
403 | } | |
404 | ||
405 | /* master wants to write to us */ | |
406 | if (ssr_filtered & SDR) { | |
407 | int ret; | |
408 | ||
409 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 410 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
411 | /* Send NACK in case of error */ |
412 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
413 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
414 | } | |
415 | ||
416 | /* master wants to read from us */ | |
417 | if (ssr_filtered & SDE) { | |
5b77d162 | 418 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
419 | rcar_i2c_write(priv, ICRXTX, value); |
420 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
421 | } | |
422 | ||
423 | return true; | |
424 | } | |
425 | ||
6ccbe607 KM |
426 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
427 | { | |
428 | struct rcar_i2c_priv *priv = ptr; | |
aa5beaf6 | 429 | irqreturn_t result = IRQ_HANDLED; |
6ccbe607 KM |
430 | u32 msr; |
431 | ||
91bfe298 SS |
432 | /*-------------- spin lock -----------------*/ |
433 | spin_lock(&priv->lock); | |
434 | ||
de20d185 WS |
435 | if (rcar_i2c_slave_irq(priv)) |
436 | goto exit; | |
437 | ||
1c176d53 | 438 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 439 | |
dd318b0d SS |
440 | /* Only handle interrupts that are currently enabled */ |
441 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 SS |
442 | if (!msr) { |
443 | result = IRQ_NONE; | |
444 | goto exit; | |
445 | } | |
dd318b0d | 446 | |
51371cdc | 447 | /* Arbitration lost */ |
6ccbe607 | 448 | if (msr & MAL) { |
6ccbe607 KM |
449 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); |
450 | goto out; | |
451 | } | |
452 | ||
51371cdc | 453 | /* Nack */ |
6ccbe607 | 454 | if (msr & MNR) { |
6ccbe607 | 455 | /* go to stop phase */ |
4f443a8a | 456 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
f2382249 | 457 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
6ccbe607 KM |
458 | rcar_i2c_flags_set(priv, ID_NACK); |
459 | goto out; | |
460 | } | |
461 | ||
dd318b0d SS |
462 | /* Stop */ |
463 | if (msr & MST) { | |
464 | rcar_i2c_flags_set(priv, ID_DONE); | |
465 | goto out; | |
466 | } | |
467 | ||
6ccbe607 KM |
468 | if (rcar_i2c_is_recv(priv)) |
469 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); | |
470 | else | |
471 | rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); | |
472 | ||
473 | out: | |
474 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | |
f2382249 | 475 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 476 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
477 | wake_up(&priv->wait); |
478 | } | |
479 | ||
aa5beaf6 | 480 | exit: |
91bfe298 SS |
481 | spin_unlock(&priv->lock); |
482 | /*-------------- spin unlock -----------------*/ | |
483 | ||
aa5beaf6 | 484 | return result; |
6ccbe607 KM |
485 | } |
486 | ||
487 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
488 | struct i2c_msg *msgs, | |
489 | int num) | |
490 | { | |
491 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
492 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
91bfe298 | 493 | unsigned long flags; |
b6763d0d WS |
494 | int i, ret; |
495 | long timeout; | |
6ccbe607 KM |
496 | |
497 | pm_runtime_get_sync(dev); | |
498 | ||
91bfe298 SS |
499 | /*-------------- spin lock -----------------*/ |
500 | spin_lock_irqsave(&priv->lock, flags); | |
501 | ||
6ccbe607 | 502 | rcar_i2c_init(priv); |
1c176d53 WS |
503 | /* start clock */ |
504 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 | 505 | |
91bfe298 SS |
506 | spin_unlock_irqrestore(&priv->lock, flags); |
507 | /*-------------- spin unlock -----------------*/ | |
508 | ||
3f7de22e WS |
509 | ret = rcar_i2c_bus_barrier(priv); |
510 | if (ret < 0) | |
511 | goto out; | |
512 | ||
6ccbe607 | 513 | for (i = 0; i < num; i++) { |
d7653964 WS |
514 | /* This HW can't send STOP after address phase */ |
515 | if (msgs[i].len == 0) { | |
516 | ret = -EOPNOTSUPP; | |
517 | break; | |
518 | } | |
519 | ||
91bfe298 SS |
520 | /*-------------- spin lock -----------------*/ |
521 | spin_lock_irqsave(&priv->lock, flags); | |
522 | ||
6ccbe607 KM |
523 | /* init each data */ |
524 | priv->msg = &msgs[i]; | |
525 | priv->pos = 0; | |
526 | priv->flags = 0; | |
c30d7662 | 527 | if (i == num - 1) |
6ccbe607 KM |
528 | rcar_i2c_flags_set(priv, ID_LAST_MSG); |
529 | ||
7c7117ff | 530 | rcar_i2c_prepare_msg(priv); |
6ccbe607 | 531 | |
91bfe298 SS |
532 | spin_unlock_irqrestore(&priv->lock, flags); |
533 | /*-------------- spin unlock -----------------*/ | |
534 | ||
6ccbe607 KM |
535 | timeout = wait_event_timeout(priv->wait, |
536 | rcar_i2c_flags_has(priv, ID_DONE), | |
efd2c611 | 537 | adap->timeout); |
6ccbe607 KM |
538 | if (!timeout) { |
539 | ret = -ETIMEDOUT; | |
540 | break; | |
541 | } | |
542 | ||
6ccbe607 | 543 | if (rcar_i2c_flags_has(priv, ID_NACK)) { |
6ff4b105 | 544 | ret = -ENXIO; |
6ccbe607 KM |
545 | break; |
546 | } | |
547 | ||
548 | if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { | |
549 | ret = -EAGAIN; | |
550 | break; | |
551 | } | |
552 | ||
553 | if (rcar_i2c_flags_has(priv, ID_IOERROR)) { | |
554 | ret = -EIO; | |
555 | break; | |
556 | } | |
557 | ||
558 | ret = i + 1; /* The number of transfer */ | |
559 | } | |
3f7de22e | 560 | out: |
6ccbe607 KM |
561 | pm_runtime_put(dev); |
562 | ||
6ff4b105 | 563 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
564 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
565 | ||
566 | return ret; | |
567 | } | |
568 | ||
de20d185 WS |
569 | static int rcar_reg_slave(struct i2c_client *slave) |
570 | { | |
571 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
572 | ||
573 | if (priv->slave) | |
574 | return -EBUSY; | |
575 | ||
576 | if (slave->flags & I2C_CLIENT_TEN) | |
577 | return -EAFNOSUPPORT; | |
578 | ||
b4cd08aa | 579 | pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
580 | |
581 | priv->slave = slave; | |
582 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
583 | rcar_i2c_write(priv, ICSSR, 0); | |
584 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
585 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int rcar_unreg_slave(struct i2c_client *slave) | |
591 | { | |
592 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
593 | ||
594 | WARN_ON(!priv->slave); | |
595 | ||
596 | rcar_i2c_write(priv, ICSIER, 0); | |
597 | rcar_i2c_write(priv, ICSCR, 0); | |
598 | ||
599 | priv->slave = NULL; | |
600 | ||
b4cd08aa | 601 | pm_runtime_put(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
602 | |
603 | return 0; | |
604 | } | |
605 | ||
6ccbe607 KM |
606 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
607 | { | |
d7653964 | 608 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
1fb2ad95 WS |
609 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
610 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
611 | } |
612 | ||
613 | static const struct i2c_algorithm rcar_i2c_algo = { | |
614 | .master_xfer = rcar_i2c_master_xfer, | |
615 | .functionality = rcar_i2c_func, | |
de20d185 WS |
616 | .reg_slave = rcar_reg_slave, |
617 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
618 | }; |
619 | ||
7679c0e1 | 620 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
621 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
622 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
623 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
624 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 625 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
626 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
627 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
628 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 629 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
7679c0e1 GL |
630 | {}, |
631 | }; | |
632 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
633 | ||
0b255e92 | 634 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 635 | { |
6ccbe607 KM |
636 | struct rcar_i2c_priv *priv; |
637 | struct i2c_adapter *adap; | |
638 | struct resource *res; | |
639 | struct device *dev = &pdev->dev; | |
640 | u32 bus_speed; | |
93e953d3 | 641 | int irq, ret; |
6ccbe607 | 642 | |
6ccbe607 | 643 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 644 | if (!priv) |
6ccbe607 | 645 | return -ENOMEM; |
6ccbe607 | 646 | |
bc8120f1 BD |
647 | priv->clk = devm_clk_get(dev, NULL); |
648 | if (IS_ERR(priv->clk)) { | |
649 | dev_err(dev, "cannot get clock\n"); | |
650 | return PTR_ERR(priv->clk); | |
651 | } | |
652 | ||
6ccbe607 | 653 | bus_speed = 100000; /* default 100 kHz */ |
c6f18913 | 654 | of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); |
b720423a | 655 | |
c6f18913 | 656 | priv->devtype = (enum rcar_i2c_type)of_match_device(rcar_i2c_dt_ids, dev)->data; |
b720423a | 657 | |
6ccbe607 KM |
658 | ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); |
659 | if (ret < 0) | |
660 | return ret; | |
661 | ||
3cc2d009 | 662 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
663 | priv->io = devm_ioremap_resource(dev, res); |
664 | if (IS_ERR(priv->io)) | |
665 | return PTR_ERR(priv->io); | |
6ccbe607 | 666 | |
93e953d3 | 667 | irq = platform_get_irq(pdev, 0); |
6ccbe607 | 668 | init_waitqueue_head(&priv->wait); |
91bfe298 | 669 | spin_lock_init(&priv->lock); |
6ccbe607 | 670 | |
929e3aba WS |
671 | adap = &priv->adap; |
672 | adap->nr = pdev->id; | |
673 | adap->algo = &rcar_i2c_algo; | |
674 | adap->class = I2C_CLASS_DEPRECATED; | |
675 | adap->retries = 3; | |
676 | adap->dev.parent = dev; | |
677 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
678 | i2c_set_adapdata(adap, priv); |
679 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
680 | ||
93e953d3 | 681 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, |
6ccbe607 KM |
682 | dev_name(dev), priv); |
683 | if (ret < 0) { | |
93e953d3 | 684 | dev_err(dev, "cannot get irq %d\n", irq); |
6ccbe607 KM |
685 | return ret; |
686 | } | |
687 | ||
4f7effdd WS |
688 | pm_runtime_enable(dev); |
689 | platform_set_drvdata(pdev, priv); | |
690 | ||
6ccbe607 KM |
691 | ret = i2c_add_numbered_adapter(adap); |
692 | if (ret < 0) { | |
693 | dev_err(dev, "reg adap failed: %d\n", ret); | |
4f7effdd | 694 | pm_runtime_disable(dev); |
6ccbe607 KM |
695 | return ret; |
696 | } | |
697 | ||
6ccbe607 KM |
698 | dev_info(dev, "probed\n"); |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
0b255e92 | 703 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
704 | { |
705 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
706 | struct device *dev = &pdev->dev; | |
707 | ||
708 | i2c_del_adapter(&priv->adap); | |
709 | pm_runtime_disable(dev); | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
45fd5e4a | 714 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
715 | .driver = { |
716 | .name = "i2c-rcar", | |
7679c0e1 | 717 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
718 | }, |
719 | .probe = rcar_i2c_probe, | |
0b255e92 | 720 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
721 | }; |
722 | ||
45fd5e4a | 723 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 724 | |
3d99beab | 725 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
726 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
727 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |