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Commit | Line | Data |
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6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
708ca408 WS |
4 | * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> |
5 | * Copyright (C) 2011-2015 Renesas Electronics Corporation | |
3d99beab WS |
6 | * |
7 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
8 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
9 | * | |
10 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
11 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
12 | * | |
6ccbe607 KM |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 15 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
16 | * |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
6ccbe607 KM |
21 | */ |
22 | #include <linux/clk.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
6ccbe607 KM |
25 | #include <linux/interrupt.h> |
26 | #include <linux/io.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/i2c/i2c-rcar.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
7679c0e1 | 31 | #include <linux/of_device.h> |
6ccbe607 KM |
32 | #include <linux/platform_device.h> |
33 | #include <linux/pm_runtime.h> | |
34 | #include <linux/slab.h> | |
6ccbe607 KM |
35 | |
36 | /* register offsets */ | |
37 | #define ICSCR 0x00 /* slave ctrl */ | |
38 | #define ICMCR 0x04 /* master ctrl */ | |
39 | #define ICSSR 0x08 /* slave status */ | |
40 | #define ICMSR 0x0C /* master status */ | |
41 | #define ICSIER 0x10 /* slave irq enable */ | |
42 | #define ICMIER 0x14 /* master irq enable */ | |
43 | #define ICCCR 0x18 /* clock dividers */ | |
44 | #define ICSAR 0x1C /* slave address */ | |
45 | #define ICMAR 0x20 /* master address */ | |
46 | #define ICRXTX 0x24 /* data port */ | |
47 | ||
de20d185 WS |
48 | /* ICSCR */ |
49 | #define SDBS (1 << 3) /* slave data buffer select */ | |
50 | #define SIE (1 << 2) /* slave interface enable */ | |
51 | #define GCAE (1 << 1) /* general call address enable */ | |
52 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
53 | ||
6ccbe607 KM |
54 | /* ICMCR */ |
55 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
56 | #define FSCL (1 << 6) /* override SCL pin */ | |
57 | #define FSDA (1 << 5) /* override SDA pin */ | |
58 | #define OBPC (1 << 4) /* override pins */ | |
59 | #define MIE (1 << 3) /* master if enable */ | |
60 | #define TSBE (1 << 2) | |
61 | #define FSB (1 << 1) /* force stop bit */ | |
62 | #define ESG (1 << 0) /* en startbit gen */ | |
63 | ||
de20d185 WS |
64 | /* ICSSR (also for ICSIER) */ |
65 | #define GCAR (1 << 6) /* general call received */ | |
66 | #define STM (1 << 5) /* slave transmit mode */ | |
67 | #define SSR (1 << 4) /* stop received */ | |
68 | #define SDE (1 << 3) /* slave data empty */ | |
69 | #define SDT (1 << 2) /* slave data transmitted */ | |
70 | #define SDR (1 << 1) /* slave data received */ | |
71 | #define SAR (1 << 0) /* slave addr received */ | |
72 | ||
3e3aabac | 73 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
74 | #define MNR (1 << 6) /* nack received */ |
75 | #define MAL (1 << 5) /* arbitration lost */ | |
76 | #define MST (1 << 4) /* sent a stop */ | |
77 | #define MDE (1 << 3) | |
78 | #define MDT (1 << 2) | |
79 | #define MDR (1 << 1) | |
80 | #define MAT (1 << 0) /* slave addr xfer done */ | |
81 | ||
6ccbe607 | 82 | |
4f443a8a WS |
83 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
84 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
e5a7effa | 85 | #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) |
4f443a8a | 86 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) |
6ccbe607 | 87 | |
3e3aabac WS |
88 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
89 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
90 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 91 | |
938916fb SS |
92 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
93 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 94 | |
6ccbe607 | 95 | #define ID_LAST_MSG (1 << 0) |
6ccbe607 KM |
96 | #define ID_DONE (1 << 2) |
97 | #define ID_ARBLOST (1 << 3) | |
98 | #define ID_NACK (1 << 4) | |
99 | ||
b720423a | 100 | enum rcar_i2c_type { |
043a3f11 KM |
101 | I2C_RCAR_GEN1, |
102 | I2C_RCAR_GEN2, | |
e7db0d34 | 103 | I2C_RCAR_GEN3, |
b720423a NVD |
104 | }; |
105 | ||
6ccbe607 KM |
106 | struct rcar_i2c_priv { |
107 | void __iomem *io; | |
108 | struct i2c_adapter adap; | |
344beeb2 WS |
109 | struct i2c_msg *msg; |
110 | int msgs_left; | |
bc8120f1 | 111 | struct clk *clk; |
6ccbe607 | 112 | |
6ccbe607 KM |
113 | wait_queue_head_t wait; |
114 | ||
115 | int pos; | |
6ccbe607 KM |
116 | u32 icccr; |
117 | u32 flags; | |
51371cdc | 118 | enum rcar_i2c_type devtype; |
de20d185 | 119 | struct i2c_client *slave; |
6ccbe607 KM |
120 | }; |
121 | ||
122 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
123 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
124 | ||
125 | #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) | |
126 | #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) | |
127 | ||
128 | #define LOOP_TIMEOUT 1024 | |
129 | ||
51371cdc | 130 | |
6ccbe607 KM |
131 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
132 | { | |
133 | writel(val, priv->io + reg); | |
134 | } | |
135 | ||
136 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
137 | { | |
138 | return readl(priv->io + reg); | |
139 | } | |
140 | ||
141 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
142 | { | |
6ccbe607 KM |
143 | /* reset master mode */ |
144 | rcar_i2c_write(priv, ICMIER, 0); | |
93c659d8 | 145 | rcar_i2c_write(priv, ICMCR, MDBS); |
6ccbe607 | 146 | rcar_i2c_write(priv, ICMSR, 0); |
93c659d8 WS |
147 | /* start clock */ |
148 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 KM |
149 | } |
150 | ||
6ccbe607 KM |
151 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
152 | { | |
153 | int i; | |
154 | ||
155 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
156 | /* make sure that bus is not busy */ | |
157 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
158 | return 0; | |
159 | udelay(1); | |
160 | } | |
161 | ||
162 | return -EBUSY; | |
163 | } | |
164 | ||
6ccbe607 KM |
165 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, |
166 | u32 bus_speed, | |
167 | struct device *dev) | |
168 | { | |
6ccbe607 KM |
169 | u32 scgd, cdf; |
170 | u32 round, ick; | |
171 | u32 scl; | |
b720423a | 172 | u32 cdf_width; |
8d049403 | 173 | unsigned long rate; |
6ccbe607 | 174 | |
b720423a | 175 | switch (priv->devtype) { |
043a3f11 | 176 | case I2C_RCAR_GEN1: |
b720423a NVD |
177 | cdf_width = 2; |
178 | break; | |
043a3f11 | 179 | case I2C_RCAR_GEN2: |
e7db0d34 | 180 | case I2C_RCAR_GEN3: |
b720423a NVD |
181 | cdf_width = 3; |
182 | break; | |
183 | default: | |
184 | dev_err(dev, "device type error\n"); | |
185 | return -EIO; | |
186 | } | |
187 | ||
6ccbe607 KM |
188 | /* |
189 | * calculate SCL clock | |
190 | * see | |
191 | * ICCCR | |
192 | * | |
193 | * ick = clkp / (1 + CDF) | |
194 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
195 | * | |
196 | * ick : I2C internal clock < 20 MHz | |
197 | * ticf : I2C SCL falling time = 35 ns here | |
198 | * tr : I2C SCL rising time = 200 ns here | |
199 | * intd : LSI internal delay = 50 ns here | |
200 | * clkp : peripheral_clk | |
201 | * F[] : integer up-valuation | |
202 | */ | |
bc8120f1 | 203 | rate = clk_get_rate(priv->clk); |
8d049403 | 204 | cdf = rate / 20000000; |
22762ccb | 205 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
206 | dev_err(dev, "Input clock %lu too high\n", rate); |
207 | return -EIO; | |
6ccbe607 | 208 | } |
8d049403 | 209 | ick = rate / (cdf + 1); |
6ccbe607 | 210 | |
6ccbe607 KM |
211 | /* |
212 | * it is impossible to calculate large scale | |
213 | * number on u32. separate it | |
214 | * | |
215 | * F[(ticf + tr + intd) * ick] | |
216 | * = F[(35 + 200 + 50)ns * ick] | |
217 | * = F[285 * ick / 1000000000] | |
218 | * = F[(ick / 1000000) * 285 / 1000] | |
219 | */ | |
220 | round = (ick + 500000) / 1000000 * 285; | |
221 | round = (round + 500) / 1000; | |
222 | ||
223 | /* | |
224 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
225 | * | |
226 | * Calculation result (= SCL) should be less than | |
227 | * bus_speed for hardware safety | |
8d049403 GL |
228 | * |
229 | * We could use something along the lines of | |
230 | * div = ick / (bus_speed + 1) + 1; | |
231 | * scgd = (div - 20 - round + 7) / 8; | |
232 | * scl = ick / (20 + (scgd * 8) + round); | |
233 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
234 | */ |
235 | for (scgd = 0; scgd < 0x40; scgd++) { | |
236 | scl = ick / (20 + (scgd * 8) + round); | |
237 | if (scl <= bus_speed) | |
238 | goto scgd_find; | |
239 | } | |
240 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
241 | return -EIO; | |
242 | ||
243 | scgd_find: | |
244 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
bc8120f1 | 245 | scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 | 246 | |
708ca408 | 247 | /* keep icccr value */ |
14d32f17 | 248 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
249 | |
250 | return 0; | |
251 | } | |
252 | ||
7c7117ff | 253 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 254 | { |
386babf8 | 255 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 256 | |
344beeb2 WS |
257 | priv->pos = 0; |
258 | priv->flags = 0; | |
259 | if (priv->msgs_left == 1) | |
260 | rcar_i2c_flags_set(priv, ID_LAST_MSG); | |
261 | ||
386babf8 | 262 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
3c95de67 | 263 | rcar_i2c_write(priv, ICMSR, 0); |
4f443a8a | 264 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); |
386babf8 | 265 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
266 | } |
267 | ||
2bc3c5a8 WS |
268 | static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) |
269 | { | |
270 | priv->msg++; | |
271 | priv->msgs_left--; | |
272 | rcar_i2c_prepare_msg(priv); | |
273 | } | |
274 | ||
6ccbe607 KM |
275 | /* |
276 | * interrupt functions | |
277 | */ | |
278 | static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |
279 | { | |
280 | struct i2c_msg *msg = priv->msg; | |
281 | ||
708ca408 | 282 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 KM |
283 | if (!(msr & MDE)) |
284 | return 0; | |
285 | ||
6ccbe607 KM |
286 | if (priv->pos < msg->len) { |
287 | /* | |
288 | * Prepare next data to ICRXTX register. | |
289 | * This data will go to _SHIFT_ register. | |
290 | * | |
291 | * * | |
292 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
293 | */ | |
294 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
295 | priv->pos++; | |
296 | ||
297 | } else { | |
298 | /* | |
299 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
300 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
301 | * | |
302 | * * | |
303 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
304 | */ | |
305 | ||
2bc3c5a8 | 306 | if (priv->flags & ID_LAST_MSG) { |
6ccbe607 KM |
307 | /* |
308 | * If current msg is the _LAST_ msg, | |
309 | * prepare stop condition here. | |
310 | * ID_DONE will be set on STOP irq. | |
311 | */ | |
4f443a8a | 312 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
2bc3c5a8 WS |
313 | } else { |
314 | rcar_i2c_next_msg(priv); | |
315 | return 0; | |
316 | } | |
6ccbe607 KM |
317 | } |
318 | ||
3c95de67 | 319 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
324 | static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |
325 | { | |
326 | struct i2c_msg *msg = priv->msg; | |
327 | ||
708ca408 | 328 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 KM |
329 | if (!(msr & MDR)) |
330 | return 0; | |
331 | ||
332 | if (msr & MAT) { | |
e5a7effa | 333 | /* Address transfer phase finished, but no data at this point. */ |
6ccbe607 | 334 | } else if (priv->pos < msg->len) { |
708ca408 | 335 | /* get received data */ |
6ccbe607 KM |
336 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); |
337 | priv->pos++; | |
338 | } | |
339 | ||
340 | /* | |
708ca408 WS |
341 | * If next received data is the _LAST_, go to STOP phase. Might be |
342 | * overwritten by REP START when setting up a new msg. Not elegant | |
343 | * but the only stable sequence for REP START I have found so far. | |
6ccbe607 KM |
344 | */ |
345 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 346 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 347 | |
2bc3c5a8 WS |
348 | if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) |
349 | rcar_i2c_next_msg(priv); | |
350 | else | |
351 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); | |
6ccbe607 KM |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
de20d185 WS |
356 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
357 | { | |
358 | u32 ssr_raw, ssr_filtered; | |
359 | u8 value; | |
360 | ||
361 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
362 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
363 | ||
364 | if (!ssr_filtered) | |
365 | return false; | |
366 | ||
367 | /* address detected */ | |
368 | if (ssr_filtered & SAR) { | |
369 | /* read or write request */ | |
370 | if (ssr_raw & STM) { | |
5b77d162 | 371 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
372 | rcar_i2c_write(priv, ICRXTX, value); |
373 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
374 | } else { | |
5b77d162 | 375 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
376 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
377 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
378 | } | |
379 | ||
380 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
381 | } | |
382 | ||
383 | /* master sent stop */ | |
384 | if (ssr_filtered & SSR) { | |
385 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
386 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
387 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
388 | } | |
389 | ||
390 | /* master wants to write to us */ | |
391 | if (ssr_filtered & SDR) { | |
392 | int ret; | |
393 | ||
394 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 395 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
396 | /* Send NACK in case of error */ |
397 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
398 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
399 | } | |
400 | ||
401 | /* master wants to read from us */ | |
402 | if (ssr_filtered & SDE) { | |
5b77d162 | 403 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
404 | rcar_i2c_write(priv, ICRXTX, value); |
405 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
406 | } | |
407 | ||
408 | return true; | |
409 | } | |
410 | ||
6ccbe607 KM |
411 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
412 | { | |
413 | struct rcar_i2c_priv *priv = ptr; | |
e5a7effa WS |
414 | u32 msr, val; |
415 | ||
416 | /* Clear START or STOP as soon as we can */ | |
417 | val = rcar_i2c_read(priv, ICMCR); | |
418 | rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); | |
6ccbe607 | 419 | |
1c176d53 | 420 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 421 | |
dd318b0d SS |
422 | /* Only handle interrupts that are currently enabled */ |
423 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 | 424 | if (!msr) { |
2151ba75 WS |
425 | if (rcar_i2c_slave_irq(priv)) |
426 | return IRQ_HANDLED; | |
427 | ||
428 | return IRQ_NONE; | |
aa5beaf6 | 429 | } |
dd318b0d | 430 | |
51371cdc | 431 | /* Arbitration lost */ |
6ccbe607 | 432 | if (msr & MAL) { |
6ccbe607 KM |
433 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); |
434 | goto out; | |
435 | } | |
436 | ||
51371cdc | 437 | /* Nack */ |
6ccbe607 | 438 | if (msr & MNR) { |
315a1736 | 439 | /* HW automatically sends STOP after received NACK */ |
f2382249 | 440 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
6ccbe607 KM |
441 | rcar_i2c_flags_set(priv, ID_NACK); |
442 | goto out; | |
443 | } | |
444 | ||
dd318b0d SS |
445 | /* Stop */ |
446 | if (msr & MST) { | |
2bc3c5a8 | 447 | priv->msgs_left--; /* The last message also made it */ |
dd318b0d SS |
448 | rcar_i2c_flags_set(priv, ID_DONE); |
449 | goto out; | |
450 | } | |
451 | ||
6ccbe607 KM |
452 | if (rcar_i2c_is_recv(priv)) |
453 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); | |
454 | else | |
455 | rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); | |
456 | ||
457 | out: | |
458 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | |
f2382249 | 459 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 460 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
461 | wake_up(&priv->wait); |
462 | } | |
463 | ||
2151ba75 | 464 | return IRQ_HANDLED; |
6ccbe607 KM |
465 | } |
466 | ||
467 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
468 | struct i2c_msg *msgs, | |
469 | int num) | |
470 | { | |
471 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
472 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
b6763d0d | 473 | int i, ret; |
738206de | 474 | long time_left; |
6ccbe607 KM |
475 | |
476 | pm_runtime_get_sync(dev); | |
477 | ||
3f7de22e WS |
478 | ret = rcar_i2c_bus_barrier(priv); |
479 | if (ret < 0) | |
480 | goto out; | |
481 | ||
6ccbe607 | 482 | for (i = 0; i < num; i++) { |
d7653964 WS |
483 | /* This HW can't send STOP after address phase */ |
484 | if (msgs[i].len == 0) { | |
485 | ret = -EOPNOTSUPP; | |
2bc3c5a8 | 486 | goto out; |
6ccbe607 | 487 | } |
2bc3c5a8 | 488 | } |
6ccbe607 | 489 | |
2bc3c5a8 WS |
490 | /* init data */ |
491 | priv->msg = msgs; | |
492 | priv->msgs_left = num; | |
493 | ||
494 | rcar_i2c_prepare_msg(priv); | |
495 | ||
496 | time_left = wait_event_timeout(priv->wait, | |
497 | rcar_i2c_flags_has(priv, ID_DONE), | |
498 | num * adap->timeout); | |
499 | if (!time_left) { | |
500 | rcar_i2c_init(priv); | |
501 | ret = -ETIMEDOUT; | |
502 | } else if (rcar_i2c_flags_has(priv, ID_NACK)) { | |
503 | ret = -ENXIO; | |
504 | } else if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { | |
505 | ret = -EAGAIN; | |
506 | } else { | |
507 | ret = num - priv->msgs_left; /* The number of transfer */ | |
6ccbe607 | 508 | } |
3f7de22e | 509 | out: |
6ccbe607 KM |
510 | pm_runtime_put(dev); |
511 | ||
6ff4b105 | 512 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
513 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
514 | ||
515 | return ret; | |
516 | } | |
517 | ||
de20d185 WS |
518 | static int rcar_reg_slave(struct i2c_client *slave) |
519 | { | |
520 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
521 | ||
522 | if (priv->slave) | |
523 | return -EBUSY; | |
524 | ||
525 | if (slave->flags & I2C_CLIENT_TEN) | |
526 | return -EAFNOSUPPORT; | |
527 | ||
528 | pm_runtime_forbid(rcar_i2c_priv_to_dev(priv)); | |
529 | ||
530 | priv->slave = slave; | |
531 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
532 | rcar_i2c_write(priv, ICSSR, 0); | |
533 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
534 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | static int rcar_unreg_slave(struct i2c_client *slave) | |
540 | { | |
541 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
542 | ||
543 | WARN_ON(!priv->slave); | |
544 | ||
545 | rcar_i2c_write(priv, ICSIER, 0); | |
546 | rcar_i2c_write(priv, ICSCR, 0); | |
547 | ||
548 | priv->slave = NULL; | |
549 | ||
550 | pm_runtime_allow(rcar_i2c_priv_to_dev(priv)); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
6ccbe607 KM |
555 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
556 | { | |
d7653964 | 557 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
1fb2ad95 WS |
558 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
559 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
560 | } |
561 | ||
562 | static const struct i2c_algorithm rcar_i2c_algo = { | |
563 | .master_xfer = rcar_i2c_master_xfer, | |
564 | .functionality = rcar_i2c_func, | |
de20d185 WS |
565 | .reg_slave = rcar_reg_slave, |
566 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
567 | }; |
568 | ||
7679c0e1 | 569 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
570 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
571 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
572 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
573 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 574 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
575 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
576 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
577 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 578 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
7679c0e1 GL |
579 | {}, |
580 | }; | |
581 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
582 | ||
0b255e92 | 583 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 584 | { |
6d4028c6 | 585 | struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); |
6ccbe607 KM |
586 | struct rcar_i2c_priv *priv; |
587 | struct i2c_adapter *adap; | |
588 | struct resource *res; | |
589 | struct device *dev = &pdev->dev; | |
590 | u32 bus_speed; | |
93e953d3 | 591 | int irq, ret; |
6ccbe607 | 592 | |
6ccbe607 | 593 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 594 | if (!priv) |
6ccbe607 | 595 | return -ENOMEM; |
6ccbe607 | 596 | |
bc8120f1 BD |
597 | priv->clk = devm_clk_get(dev, NULL); |
598 | if (IS_ERR(priv->clk)) { | |
599 | dev_err(dev, "cannot get clock\n"); | |
600 | return PTR_ERR(priv->clk); | |
601 | } | |
602 | ||
6ccbe607 | 603 | bus_speed = 100000; /* default 100 kHz */ |
7679c0e1 GL |
604 | ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); |
605 | if (ret < 0 && pdata && pdata->bus_speed) | |
6ccbe607 | 606 | bus_speed = pdata->bus_speed; |
b720423a | 607 | |
7679c0e1 GL |
608 | if (pdev->dev.of_node) |
609 | priv->devtype = (long)of_match_device(rcar_i2c_dt_ids, | |
610 | dev)->data; | |
611 | else | |
612 | priv->devtype = platform_get_device_id(pdev)->driver_data; | |
b720423a | 613 | |
6ccbe607 KM |
614 | ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); |
615 | if (ret < 0) | |
616 | return ret; | |
617 | ||
3cc2d009 | 618 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
619 | priv->io = devm_ioremap_resource(dev, res); |
620 | if (IS_ERR(priv->io)) | |
621 | return PTR_ERR(priv->io); | |
6ccbe607 | 622 | |
93c659d8 WS |
623 | rcar_i2c_init(priv); |
624 | ||
93e953d3 | 625 | irq = platform_get_irq(pdev, 0); |
6ccbe607 | 626 | init_waitqueue_head(&priv->wait); |
6ccbe607 | 627 | |
929e3aba WS |
628 | adap = &priv->adap; |
629 | adap->nr = pdev->id; | |
630 | adap->algo = &rcar_i2c_algo; | |
631 | adap->class = I2C_CLASS_DEPRECATED; | |
632 | adap->retries = 3; | |
633 | adap->dev.parent = dev; | |
634 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
635 | i2c_set_adapdata(adap, priv); |
636 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
637 | ||
93e953d3 | 638 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, |
6ccbe607 KM |
639 | dev_name(dev), priv); |
640 | if (ret < 0) { | |
93e953d3 | 641 | dev_err(dev, "cannot get irq %d\n", irq); |
6ccbe607 KM |
642 | return ret; |
643 | } | |
644 | ||
645 | ret = i2c_add_numbered_adapter(adap); | |
646 | if (ret < 0) { | |
647 | dev_err(dev, "reg adap failed: %d\n", ret); | |
648 | return ret; | |
649 | } | |
650 | ||
651 | pm_runtime_enable(dev); | |
652 | platform_set_drvdata(pdev, priv); | |
653 | ||
654 | dev_info(dev, "probed\n"); | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
0b255e92 | 659 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
660 | { |
661 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
662 | struct device *dev = &pdev->dev; | |
663 | ||
664 | i2c_del_adapter(&priv->adap); | |
665 | pm_runtime_disable(dev); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
e9a02a3d | 670 | static const struct platform_device_id rcar_i2c_id_table[] = { |
043a3f11 KM |
671 | { "i2c-rcar", I2C_RCAR_GEN1 }, |
672 | { "i2c-rcar_gen1", I2C_RCAR_GEN1 }, | |
673 | { "i2c-rcar_gen2", I2C_RCAR_GEN2 }, | |
b720423a NVD |
674 | {}, |
675 | }; | |
676 | MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); | |
677 | ||
45fd5e4a | 678 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
679 | .driver = { |
680 | .name = "i2c-rcar", | |
7679c0e1 | 681 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
682 | }, |
683 | .probe = rcar_i2c_probe, | |
0b255e92 | 684 | .remove = rcar_i2c_remove, |
b720423a | 685 | .id_table = rcar_i2c_id_table, |
6ccbe607 KM |
686 | }; |
687 | ||
45fd5e4a | 688 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 689 | |
3d99beab | 690 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
691 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
692 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |