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Commit | Line | Data |
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6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
3d99beab WS |
4 | * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> |
5 | * | |
6 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
7 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
8 | * | |
9 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
10 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
11 | * | |
12 | * This file used out-of-tree driver i2c-rcar.c | |
13 | * Copyright (C) 2011-2012 Renesas Electronics Corporation | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 17 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
18 | * |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
6ccbe607 KM |
23 | */ |
24 | #include <linux/clk.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/err.h> | |
6ccbe607 KM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/i2c/i2c-rcar.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
7679c0e1 | 33 | #include <linux/of_device.h> |
6ccbe607 KM |
34 | #include <linux/platform_device.h> |
35 | #include <linux/pm_runtime.h> | |
36 | #include <linux/slab.h> | |
91bfe298 | 37 | #include <linux/spinlock.h> |
6ccbe607 KM |
38 | |
39 | /* register offsets */ | |
40 | #define ICSCR 0x00 /* slave ctrl */ | |
41 | #define ICMCR 0x04 /* master ctrl */ | |
42 | #define ICSSR 0x08 /* slave status */ | |
43 | #define ICMSR 0x0C /* master status */ | |
44 | #define ICSIER 0x10 /* slave irq enable */ | |
45 | #define ICMIER 0x14 /* master irq enable */ | |
46 | #define ICCCR 0x18 /* clock dividers */ | |
47 | #define ICSAR 0x1C /* slave address */ | |
48 | #define ICMAR 0x20 /* master address */ | |
49 | #define ICRXTX 0x24 /* data port */ | |
50 | ||
51 | /* ICMCR */ | |
52 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
53 | #define FSCL (1 << 6) /* override SCL pin */ | |
54 | #define FSDA (1 << 5) /* override SDA pin */ | |
55 | #define OBPC (1 << 4) /* override pins */ | |
56 | #define MIE (1 << 3) /* master if enable */ | |
57 | #define TSBE (1 << 2) | |
58 | #define FSB (1 << 1) /* force stop bit */ | |
59 | #define ESG (1 << 0) /* en startbit gen */ | |
60 | ||
3e3aabac | 61 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
62 | #define MNR (1 << 6) /* nack received */ |
63 | #define MAL (1 << 5) /* arbitration lost */ | |
64 | #define MST (1 << 4) /* sent a stop */ | |
65 | #define MDE (1 << 3) | |
66 | #define MDT (1 << 2) | |
67 | #define MDR (1 << 1) | |
68 | #define MAT (1 << 0) /* slave addr xfer done */ | |
69 | ||
6ccbe607 | 70 | |
4f443a8a WS |
71 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
72 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
73 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) | |
6ccbe607 | 74 | |
3e3aabac WS |
75 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
76 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
77 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 78 | |
3c95de67 WS |
79 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE)) |
80 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR)) | |
81 | ||
6ccbe607 KM |
82 | #define ID_LAST_MSG (1 << 0) |
83 | #define ID_IOERROR (1 << 1) | |
84 | #define ID_DONE (1 << 2) | |
85 | #define ID_ARBLOST (1 << 3) | |
86 | #define ID_NACK (1 << 4) | |
87 | ||
b720423a | 88 | enum rcar_i2c_type { |
043a3f11 KM |
89 | I2C_RCAR_GEN1, |
90 | I2C_RCAR_GEN2, | |
b720423a NVD |
91 | }; |
92 | ||
6ccbe607 KM |
93 | struct rcar_i2c_priv { |
94 | void __iomem *io; | |
95 | struct i2c_adapter adap; | |
96 | struct i2c_msg *msg; | |
bc8120f1 | 97 | struct clk *clk; |
6ccbe607 | 98 | |
91bfe298 | 99 | spinlock_t lock; |
6ccbe607 KM |
100 | wait_queue_head_t wait; |
101 | ||
102 | int pos; | |
6ccbe607 KM |
103 | u32 icccr; |
104 | u32 flags; | |
51371cdc | 105 | enum rcar_i2c_type devtype; |
6ccbe607 KM |
106 | }; |
107 | ||
108 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
109 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
110 | ||
111 | #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) | |
112 | #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) | |
113 | ||
114 | #define LOOP_TIMEOUT 1024 | |
115 | ||
51371cdc | 116 | |
6ccbe607 KM |
117 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
118 | { | |
119 | writel(val, priv->io + reg); | |
120 | } | |
121 | ||
122 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
123 | { | |
124 | return readl(priv->io + reg); | |
125 | } | |
126 | ||
127 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
128 | { | |
129 | /* | |
130 | * reset slave mode. | |
131 | * slave mode is not used on this driver | |
132 | */ | |
133 | rcar_i2c_write(priv, ICSIER, 0); | |
134 | rcar_i2c_write(priv, ICSAR, 0); | |
135 | rcar_i2c_write(priv, ICSCR, 0); | |
136 | rcar_i2c_write(priv, ICSSR, 0); | |
137 | ||
138 | /* reset master mode */ | |
139 | rcar_i2c_write(priv, ICMIER, 0); | |
140 | rcar_i2c_write(priv, ICMCR, 0); | |
141 | rcar_i2c_write(priv, ICMSR, 0); | |
142 | rcar_i2c_write(priv, ICMAR, 0); | |
143 | } | |
144 | ||
6ccbe607 KM |
145 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
146 | { | |
147 | int i; | |
148 | ||
149 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
150 | /* make sure that bus is not busy */ | |
151 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
152 | return 0; | |
153 | udelay(1); | |
154 | } | |
155 | ||
156 | return -EBUSY; | |
157 | } | |
158 | ||
6ccbe607 KM |
159 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, |
160 | u32 bus_speed, | |
161 | struct device *dev) | |
162 | { | |
6ccbe607 KM |
163 | u32 scgd, cdf; |
164 | u32 round, ick; | |
165 | u32 scl; | |
b720423a | 166 | u32 cdf_width; |
8d049403 | 167 | unsigned long rate; |
6ccbe607 | 168 | |
b720423a | 169 | switch (priv->devtype) { |
043a3f11 | 170 | case I2C_RCAR_GEN1: |
b720423a NVD |
171 | cdf_width = 2; |
172 | break; | |
043a3f11 | 173 | case I2C_RCAR_GEN2: |
b720423a NVD |
174 | cdf_width = 3; |
175 | break; | |
176 | default: | |
177 | dev_err(dev, "device type error\n"); | |
178 | return -EIO; | |
179 | } | |
180 | ||
6ccbe607 KM |
181 | /* |
182 | * calculate SCL clock | |
183 | * see | |
184 | * ICCCR | |
185 | * | |
186 | * ick = clkp / (1 + CDF) | |
187 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
188 | * | |
189 | * ick : I2C internal clock < 20 MHz | |
190 | * ticf : I2C SCL falling time = 35 ns here | |
191 | * tr : I2C SCL rising time = 200 ns here | |
192 | * intd : LSI internal delay = 50 ns here | |
193 | * clkp : peripheral_clk | |
194 | * F[] : integer up-valuation | |
195 | */ | |
bc8120f1 | 196 | rate = clk_get_rate(priv->clk); |
8d049403 GL |
197 | cdf = rate / 20000000; |
198 | if (cdf >= 1 << cdf_width) { | |
199 | dev_err(dev, "Input clock %lu too high\n", rate); | |
200 | return -EIO; | |
6ccbe607 | 201 | } |
8d049403 | 202 | ick = rate / (cdf + 1); |
6ccbe607 | 203 | |
6ccbe607 KM |
204 | /* |
205 | * it is impossible to calculate large scale | |
206 | * number on u32. separate it | |
207 | * | |
208 | * F[(ticf + tr + intd) * ick] | |
209 | * = F[(35 + 200 + 50)ns * ick] | |
210 | * = F[285 * ick / 1000000000] | |
211 | * = F[(ick / 1000000) * 285 / 1000] | |
212 | */ | |
213 | round = (ick + 500000) / 1000000 * 285; | |
214 | round = (round + 500) / 1000; | |
215 | ||
216 | /* | |
217 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
218 | * | |
219 | * Calculation result (= SCL) should be less than | |
220 | * bus_speed for hardware safety | |
8d049403 GL |
221 | * |
222 | * We could use something along the lines of | |
223 | * div = ick / (bus_speed + 1) + 1; | |
224 | * scgd = (div - 20 - round + 7) / 8; | |
225 | * scl = ick / (20 + (scgd * 8) + round); | |
226 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
227 | */ |
228 | for (scgd = 0; scgd < 0x40; scgd++) { | |
229 | scl = ick / (20 + (scgd * 8) + round); | |
230 | if (scl <= bus_speed) | |
231 | goto scgd_find; | |
232 | } | |
233 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
234 | return -EIO; | |
235 | ||
236 | scgd_find: | |
237 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
bc8120f1 | 238 | scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 KM |
239 | |
240 | /* | |
241 | * keep icccr value | |
242 | */ | |
14d32f17 | 243 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
244 | |
245 | return 0; | |
246 | } | |
247 | ||
386babf8 | 248 | static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 249 | { |
386babf8 | 250 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 251 | |
386babf8 | 252 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
3c95de67 | 253 | rcar_i2c_write(priv, ICMSR, 0); |
4f443a8a | 254 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); |
386babf8 | 255 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
256 | |
257 | return 0; | |
258 | } | |
259 | ||
6ccbe607 KM |
260 | /* |
261 | * interrupt functions | |
262 | */ | |
263 | static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |
264 | { | |
265 | struct i2c_msg *msg = priv->msg; | |
266 | ||
267 | /* | |
268 | * FIXME | |
269 | * sometimes, unknown interrupt happened. | |
270 | * Do nothing | |
271 | */ | |
272 | if (!(msr & MDE)) | |
273 | return 0; | |
274 | ||
275 | /* | |
276 | * If address transfer phase finished, | |
277 | * goto data phase. | |
278 | */ | |
279 | if (msr & MAT) | |
4f443a8a | 280 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
6ccbe607 KM |
281 | |
282 | if (priv->pos < msg->len) { | |
283 | /* | |
284 | * Prepare next data to ICRXTX register. | |
285 | * This data will go to _SHIFT_ register. | |
286 | * | |
287 | * * | |
288 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
289 | */ | |
290 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
291 | priv->pos++; | |
292 | ||
293 | } else { | |
294 | /* | |
295 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
296 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
297 | * | |
298 | * * | |
299 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
300 | */ | |
301 | ||
302 | if (priv->flags & ID_LAST_MSG) | |
303 | /* | |
304 | * If current msg is the _LAST_ msg, | |
305 | * prepare stop condition here. | |
306 | * ID_DONE will be set on STOP irq. | |
307 | */ | |
4f443a8a | 308 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 KM |
309 | else |
310 | /* | |
311 | * If current msg is _NOT_ last msg, | |
312 | * it doesn't call stop phase. | |
313 | * thus, there is no STOP irq. | |
314 | * return ID_DONE here. | |
315 | */ | |
316 | return ID_DONE; | |
317 | } | |
318 | ||
3c95de67 | 319 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
324 | static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |
325 | { | |
326 | struct i2c_msg *msg = priv->msg; | |
327 | ||
328 | /* | |
329 | * FIXME | |
330 | * sometimes, unknown interrupt happened. | |
331 | * Do nothing | |
332 | */ | |
333 | if (!(msr & MDR)) | |
334 | return 0; | |
335 | ||
336 | if (msr & MAT) { | |
337 | /* | |
338 | * Address transfer phase finished, | |
339 | * but, there is no data at this point. | |
340 | * Do nothing. | |
341 | */ | |
342 | } else if (priv->pos < msg->len) { | |
343 | /* | |
344 | * get received data | |
345 | */ | |
346 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); | |
347 | priv->pos++; | |
348 | } | |
349 | ||
350 | /* | |
351 | * If next received data is the _LAST_, | |
352 | * go to STOP phase, | |
353 | * otherwise, go to DATA phase. | |
354 | */ | |
355 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 356 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 357 | else |
4f443a8a | 358 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
6ccbe607 | 359 | |
3c95de67 | 360 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); |
6ccbe607 KM |
361 | |
362 | return 0; | |
363 | } | |
364 | ||
365 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) | |
366 | { | |
367 | struct rcar_i2c_priv *priv = ptr; | |
6ccbe607 KM |
368 | u32 msr; |
369 | ||
91bfe298 SS |
370 | /*-------------- spin lock -----------------*/ |
371 | spin_lock(&priv->lock); | |
372 | ||
1c176d53 | 373 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 374 | |
dd318b0d SS |
375 | /* Only handle interrupts that are currently enabled */ |
376 | msr &= rcar_i2c_read(priv, ICMIER); | |
377 | ||
51371cdc | 378 | /* Arbitration lost */ |
6ccbe607 | 379 | if (msr & MAL) { |
6ccbe607 KM |
380 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); |
381 | goto out; | |
382 | } | |
383 | ||
51371cdc | 384 | /* Nack */ |
6ccbe607 | 385 | if (msr & MNR) { |
6ccbe607 | 386 | /* go to stop phase */ |
4f443a8a | 387 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
f2382249 | 388 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
6ccbe607 KM |
389 | rcar_i2c_flags_set(priv, ID_NACK); |
390 | goto out; | |
391 | } | |
392 | ||
dd318b0d SS |
393 | /* Stop */ |
394 | if (msr & MST) { | |
395 | rcar_i2c_flags_set(priv, ID_DONE); | |
396 | goto out; | |
397 | } | |
398 | ||
6ccbe607 KM |
399 | if (rcar_i2c_is_recv(priv)) |
400 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); | |
401 | else | |
402 | rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); | |
403 | ||
404 | out: | |
405 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | |
f2382249 | 406 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 407 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
408 | wake_up(&priv->wait); |
409 | } | |
410 | ||
91bfe298 SS |
411 | spin_unlock(&priv->lock); |
412 | /*-------------- spin unlock -----------------*/ | |
413 | ||
6ccbe607 KM |
414 | return IRQ_HANDLED; |
415 | } | |
416 | ||
417 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
418 | struct i2c_msg *msgs, | |
419 | int num) | |
420 | { | |
421 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
422 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
91bfe298 | 423 | unsigned long flags; |
6ccbe607 KM |
424 | int i, ret, timeout; |
425 | ||
426 | pm_runtime_get_sync(dev); | |
427 | ||
91bfe298 SS |
428 | /*-------------- spin lock -----------------*/ |
429 | spin_lock_irqsave(&priv->lock, flags); | |
430 | ||
6ccbe607 | 431 | rcar_i2c_init(priv); |
1c176d53 WS |
432 | /* start clock */ |
433 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 | 434 | |
91bfe298 SS |
435 | spin_unlock_irqrestore(&priv->lock, flags); |
436 | /*-------------- spin unlock -----------------*/ | |
437 | ||
3f7de22e WS |
438 | ret = rcar_i2c_bus_barrier(priv); |
439 | if (ret < 0) | |
440 | goto out; | |
441 | ||
6ccbe607 | 442 | for (i = 0; i < num; i++) { |
d7653964 WS |
443 | /* This HW can't send STOP after address phase */ |
444 | if (msgs[i].len == 0) { | |
445 | ret = -EOPNOTSUPP; | |
446 | break; | |
447 | } | |
448 | ||
91bfe298 SS |
449 | /*-------------- spin lock -----------------*/ |
450 | spin_lock_irqsave(&priv->lock, flags); | |
451 | ||
6ccbe607 KM |
452 | /* init each data */ |
453 | priv->msg = &msgs[i]; | |
454 | priv->pos = 0; | |
455 | priv->flags = 0; | |
456 | if (priv->msg == &msgs[num - 1]) | |
457 | rcar_i2c_flags_set(priv, ID_LAST_MSG); | |
458 | ||
386babf8 | 459 | ret = rcar_i2c_prepare_msg(priv); |
6ccbe607 | 460 | |
91bfe298 SS |
461 | spin_unlock_irqrestore(&priv->lock, flags); |
462 | /*-------------- spin unlock -----------------*/ | |
463 | ||
6ccbe607 KM |
464 | if (ret < 0) |
465 | break; | |
466 | ||
6ccbe607 KM |
467 | timeout = wait_event_timeout(priv->wait, |
468 | rcar_i2c_flags_has(priv, ID_DONE), | |
469 | 5 * HZ); | |
470 | if (!timeout) { | |
471 | ret = -ETIMEDOUT; | |
472 | break; | |
473 | } | |
474 | ||
6ccbe607 | 475 | if (rcar_i2c_flags_has(priv, ID_NACK)) { |
6ff4b105 | 476 | ret = -ENXIO; |
6ccbe607 KM |
477 | break; |
478 | } | |
479 | ||
480 | if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { | |
481 | ret = -EAGAIN; | |
482 | break; | |
483 | } | |
484 | ||
485 | if (rcar_i2c_flags_has(priv, ID_IOERROR)) { | |
486 | ret = -EIO; | |
487 | break; | |
488 | } | |
489 | ||
490 | ret = i + 1; /* The number of transfer */ | |
491 | } | |
3f7de22e | 492 | out: |
6ccbe607 KM |
493 | pm_runtime_put(dev); |
494 | ||
6ff4b105 | 495 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
496 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | static u32 rcar_i2c_func(struct i2c_adapter *adap) | |
502 | { | |
d7653964 WS |
503 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
504 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
505 | } |
506 | ||
507 | static const struct i2c_algorithm rcar_i2c_algo = { | |
508 | .master_xfer = rcar_i2c_master_xfer, | |
509 | .functionality = rcar_i2c_func, | |
510 | }; | |
511 | ||
7679c0e1 | 512 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
513 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
514 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
515 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
516 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 517 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
518 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
519 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
520 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
7679c0e1 GL |
521 | {}, |
522 | }; | |
523 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
524 | ||
0b255e92 | 525 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 526 | { |
6d4028c6 | 527 | struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); |
6ccbe607 KM |
528 | struct rcar_i2c_priv *priv; |
529 | struct i2c_adapter *adap; | |
530 | struct resource *res; | |
531 | struct device *dev = &pdev->dev; | |
532 | u32 bus_speed; | |
93e953d3 | 533 | int irq, ret; |
6ccbe607 | 534 | |
6ccbe607 | 535 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 536 | if (!priv) |
6ccbe607 | 537 | return -ENOMEM; |
6ccbe607 | 538 | |
bc8120f1 BD |
539 | priv->clk = devm_clk_get(dev, NULL); |
540 | if (IS_ERR(priv->clk)) { | |
541 | dev_err(dev, "cannot get clock\n"); | |
542 | return PTR_ERR(priv->clk); | |
543 | } | |
544 | ||
6ccbe607 | 545 | bus_speed = 100000; /* default 100 kHz */ |
7679c0e1 GL |
546 | ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); |
547 | if (ret < 0 && pdata && pdata->bus_speed) | |
6ccbe607 | 548 | bus_speed = pdata->bus_speed; |
b720423a | 549 | |
7679c0e1 GL |
550 | if (pdev->dev.of_node) |
551 | priv->devtype = (long)of_match_device(rcar_i2c_dt_ids, | |
552 | dev)->data; | |
553 | else | |
554 | priv->devtype = platform_get_device_id(pdev)->driver_data; | |
b720423a | 555 | |
6ccbe607 KM |
556 | ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); |
557 | if (ret < 0) | |
558 | return ret; | |
559 | ||
3cc2d009 | 560 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
561 | priv->io = devm_ioremap_resource(dev, res); |
562 | if (IS_ERR(priv->io)) | |
563 | return PTR_ERR(priv->io); | |
6ccbe607 | 564 | |
93e953d3 | 565 | irq = platform_get_irq(pdev, 0); |
6ccbe607 | 566 | init_waitqueue_head(&priv->wait); |
91bfe298 | 567 | spin_lock_init(&priv->lock); |
6ccbe607 | 568 | |
929e3aba WS |
569 | adap = &priv->adap; |
570 | adap->nr = pdev->id; | |
571 | adap->algo = &rcar_i2c_algo; | |
572 | adap->class = I2C_CLASS_DEPRECATED; | |
573 | adap->retries = 3; | |
574 | adap->dev.parent = dev; | |
575 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
576 | i2c_set_adapdata(adap, priv); |
577 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
578 | ||
93e953d3 | 579 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, |
6ccbe607 KM |
580 | dev_name(dev), priv); |
581 | if (ret < 0) { | |
93e953d3 | 582 | dev_err(dev, "cannot get irq %d\n", irq); |
6ccbe607 KM |
583 | return ret; |
584 | } | |
585 | ||
586 | ret = i2c_add_numbered_adapter(adap); | |
587 | if (ret < 0) { | |
588 | dev_err(dev, "reg adap failed: %d\n", ret); | |
589 | return ret; | |
590 | } | |
591 | ||
592 | pm_runtime_enable(dev); | |
593 | platform_set_drvdata(pdev, priv); | |
594 | ||
595 | dev_info(dev, "probed\n"); | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
0b255e92 | 600 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
601 | { |
602 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
603 | struct device *dev = &pdev->dev; | |
604 | ||
605 | i2c_del_adapter(&priv->adap); | |
606 | pm_runtime_disable(dev); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
b720423a | 611 | static struct platform_device_id rcar_i2c_id_table[] = { |
043a3f11 KM |
612 | { "i2c-rcar", I2C_RCAR_GEN1 }, |
613 | { "i2c-rcar_gen1", I2C_RCAR_GEN1 }, | |
614 | { "i2c-rcar_gen2", I2C_RCAR_GEN2 }, | |
b720423a NVD |
615 | {}, |
616 | }; | |
617 | MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); | |
618 | ||
45fd5e4a | 619 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
620 | .driver = { |
621 | .name = "i2c-rcar", | |
622 | .owner = THIS_MODULE, | |
7679c0e1 | 623 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
624 | }, |
625 | .probe = rcar_i2c_probe, | |
0b255e92 | 626 | .remove = rcar_i2c_remove, |
b720423a | 627 | .id_table = rcar_i2c_id_table, |
6ccbe607 KM |
628 | }; |
629 | ||
45fd5e4a | 630 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 631 | |
3d99beab | 632 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
633 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
634 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |