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1 | /* |
2 | * drivers/i2c/busses/i2c-rcar.c | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
6 | * | |
7 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
8 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
9 | * | |
10 | * This file used out-of-tree driver i2c-rcar.c | |
11 | * Copyright (C) 2011-2012 Renesas Electronics Corporation | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | #include <linux/clk.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/err.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/i2c.h> | |
33 | #include <linux/i2c/i2c-rcar.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/pm_runtime.h> | |
38 | #include <linux/slab.h> | |
39 | #include <linux/spinlock.h> | |
40 | ||
41 | /* register offsets */ | |
42 | #define ICSCR 0x00 /* slave ctrl */ | |
43 | #define ICMCR 0x04 /* master ctrl */ | |
44 | #define ICSSR 0x08 /* slave status */ | |
45 | #define ICMSR 0x0C /* master status */ | |
46 | #define ICSIER 0x10 /* slave irq enable */ | |
47 | #define ICMIER 0x14 /* master irq enable */ | |
48 | #define ICCCR 0x18 /* clock dividers */ | |
49 | #define ICSAR 0x1C /* slave address */ | |
50 | #define ICMAR 0x20 /* master address */ | |
51 | #define ICRXTX 0x24 /* data port */ | |
52 | ||
53 | /* ICMCR */ | |
54 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
55 | #define FSCL (1 << 6) /* override SCL pin */ | |
56 | #define FSDA (1 << 5) /* override SDA pin */ | |
57 | #define OBPC (1 << 4) /* override pins */ | |
58 | #define MIE (1 << 3) /* master if enable */ | |
59 | #define TSBE (1 << 2) | |
60 | #define FSB (1 << 1) /* force stop bit */ | |
61 | #define ESG (1 << 0) /* en startbit gen */ | |
62 | ||
63 | /* ICMSR */ | |
64 | #define MNR (1 << 6) /* nack received */ | |
65 | #define MAL (1 << 5) /* arbitration lost */ | |
66 | #define MST (1 << 4) /* sent a stop */ | |
67 | #define MDE (1 << 3) | |
68 | #define MDT (1 << 2) | |
69 | #define MDR (1 << 1) | |
70 | #define MAT (1 << 0) /* slave addr xfer done */ | |
71 | ||
72 | /* ICMIE */ | |
73 | #define MNRE (1 << 6) /* nack irq en */ | |
74 | #define MALE (1 << 5) /* arblos irq en */ | |
75 | #define MSTE (1 << 4) /* stop irq en */ | |
76 | #define MDEE (1 << 3) | |
77 | #define MDTE (1 << 2) | |
78 | #define MDRE (1 << 1) | |
79 | #define MATE (1 << 0) /* address sent irq en */ | |
80 | ||
81 | ||
82 | enum { | |
83 | RCAR_BUS_PHASE_ADDR, | |
84 | RCAR_BUS_PHASE_DATA, | |
85 | RCAR_BUS_PHASE_STOP, | |
86 | }; | |
87 | ||
88 | enum { | |
89 | RCAR_IRQ_CLOSE, | |
90 | RCAR_IRQ_OPEN_FOR_SEND, | |
91 | RCAR_IRQ_OPEN_FOR_RECV, | |
92 | RCAR_IRQ_OPEN_FOR_STOP, | |
93 | }; | |
94 | ||
95 | /* | |
96 | * flags | |
97 | */ | |
98 | #define ID_LAST_MSG (1 << 0) | |
99 | #define ID_IOERROR (1 << 1) | |
100 | #define ID_DONE (1 << 2) | |
101 | #define ID_ARBLOST (1 << 3) | |
102 | #define ID_NACK (1 << 4) | |
103 | ||
104 | struct rcar_i2c_priv { | |
105 | void __iomem *io; | |
106 | struct i2c_adapter adap; | |
107 | struct i2c_msg *msg; | |
108 | ||
109 | spinlock_t lock; | |
110 | wait_queue_head_t wait; | |
111 | ||
112 | int pos; | |
113 | int irq; | |
114 | u32 icccr; | |
115 | u32 flags; | |
116 | }; | |
117 | ||
118 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
119 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
120 | ||
121 | #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) | |
122 | #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) | |
123 | ||
124 | #define LOOP_TIMEOUT 1024 | |
125 | ||
126 | /* | |
127 | * basic functions | |
128 | */ | |
129 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) | |
130 | { | |
131 | writel(val, priv->io + reg); | |
132 | } | |
133 | ||
134 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
135 | { | |
136 | return readl(priv->io + reg); | |
137 | } | |
138 | ||
139 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
140 | { | |
141 | /* | |
142 | * reset slave mode. | |
143 | * slave mode is not used on this driver | |
144 | */ | |
145 | rcar_i2c_write(priv, ICSIER, 0); | |
146 | rcar_i2c_write(priv, ICSAR, 0); | |
147 | rcar_i2c_write(priv, ICSCR, 0); | |
148 | rcar_i2c_write(priv, ICSSR, 0); | |
149 | ||
150 | /* reset master mode */ | |
151 | rcar_i2c_write(priv, ICMIER, 0); | |
152 | rcar_i2c_write(priv, ICMCR, 0); | |
153 | rcar_i2c_write(priv, ICMSR, 0); | |
154 | rcar_i2c_write(priv, ICMAR, 0); | |
155 | } | |
156 | ||
157 | static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open) | |
158 | { | |
159 | u32 val = MNRE | MALE | MSTE | MATE; /* default */ | |
160 | ||
161 | switch (open) { | |
162 | case RCAR_IRQ_OPEN_FOR_SEND: | |
163 | val |= MDEE; /* default + send */ | |
164 | break; | |
165 | case RCAR_IRQ_OPEN_FOR_RECV: | |
166 | val |= MDRE; /* default + read */ | |
167 | break; | |
168 | case RCAR_IRQ_OPEN_FOR_STOP: | |
169 | val = MSTE; /* stop irq only */ | |
170 | break; | |
171 | case RCAR_IRQ_CLOSE: | |
172 | default: | |
173 | val = 0; /* all close */ | |
174 | break; | |
175 | } | |
176 | rcar_i2c_write(priv, ICMIER, val); | |
177 | } | |
178 | ||
179 | static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) | |
180 | { | |
181 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); | |
182 | } | |
183 | ||
184 | /* | |
185 | * bus control functions | |
186 | */ | |
187 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) | |
188 | { | |
189 | int i; | |
190 | ||
191 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
192 | /* make sure that bus is not busy */ | |
193 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
194 | return 0; | |
195 | udelay(1); | |
196 | } | |
197 | ||
198 | return -EBUSY; | |
199 | } | |
200 | ||
201 | static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase) | |
202 | { | |
203 | switch (phase) { | |
204 | case RCAR_BUS_PHASE_ADDR: | |
205 | rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG); | |
206 | break; | |
207 | case RCAR_BUS_PHASE_DATA: | |
208 | rcar_i2c_write(priv, ICMCR, MDBS | MIE); | |
209 | break; | |
210 | case RCAR_BUS_PHASE_STOP: | |
211 | rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB); | |
212 | break; | |
213 | } | |
214 | } | |
215 | ||
216 | /* | |
217 | * clock function | |
218 | */ | |
219 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, | |
220 | u32 bus_speed, | |
221 | struct device *dev) | |
222 | { | |
223 | struct clk *clkp = clk_get(NULL, "peripheral_clk"); | |
224 | u32 scgd, cdf; | |
225 | u32 round, ick; | |
226 | u32 scl; | |
227 | ||
228 | if (!clkp) { | |
229 | dev_err(dev, "there is no peripheral_clk\n"); | |
230 | return -EIO; | |
231 | } | |
232 | ||
233 | /* | |
234 | * calculate SCL clock | |
235 | * see | |
236 | * ICCCR | |
237 | * | |
238 | * ick = clkp / (1 + CDF) | |
239 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
240 | * | |
241 | * ick : I2C internal clock < 20 MHz | |
242 | * ticf : I2C SCL falling time = 35 ns here | |
243 | * tr : I2C SCL rising time = 200 ns here | |
244 | * intd : LSI internal delay = 50 ns here | |
245 | * clkp : peripheral_clk | |
246 | * F[] : integer up-valuation | |
247 | */ | |
248 | for (cdf = 0; cdf < 4; cdf++) { | |
249 | ick = clk_get_rate(clkp) / (1 + cdf); | |
250 | if (ick < 20000000) | |
251 | goto ick_find; | |
252 | } | |
253 | dev_err(dev, "there is no best CDF\n"); | |
254 | return -EIO; | |
255 | ||
256 | ick_find: | |
257 | /* | |
258 | * it is impossible to calculate large scale | |
259 | * number on u32. separate it | |
260 | * | |
261 | * F[(ticf + tr + intd) * ick] | |
262 | * = F[(35 + 200 + 50)ns * ick] | |
263 | * = F[285 * ick / 1000000000] | |
264 | * = F[(ick / 1000000) * 285 / 1000] | |
265 | */ | |
266 | round = (ick + 500000) / 1000000 * 285; | |
267 | round = (round + 500) / 1000; | |
268 | ||
269 | /* | |
270 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
271 | * | |
272 | * Calculation result (= SCL) should be less than | |
273 | * bus_speed for hardware safety | |
274 | */ | |
275 | for (scgd = 0; scgd < 0x40; scgd++) { | |
276 | scl = ick / (20 + (scgd * 8) + round); | |
277 | if (scl <= bus_speed) | |
278 | goto scgd_find; | |
279 | } | |
280 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
281 | return -EIO; | |
282 | ||
283 | scgd_find: | |
284 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
285 | scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd); | |
286 | ||
287 | /* | |
288 | * keep icccr value | |
289 | */ | |
290 | priv->icccr = (scgd << 2 | cdf); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv) | |
296 | { | |
297 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
298 | } | |
299 | ||
300 | /* | |
301 | * status functions | |
302 | */ | |
303 | static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv) | |
304 | { | |
305 | return rcar_i2c_read(priv, ICMSR); | |
306 | } | |
307 | ||
308 | #define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff) | |
309 | static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit) | |
310 | { | |
311 | rcar_i2c_write(priv, ICMSR, ~bit); | |
312 | } | |
313 | ||
314 | /* | |
315 | * recv/send functions | |
316 | */ | |
317 | static int rcar_i2c_recv(struct rcar_i2c_priv *priv) | |
318 | { | |
319 | rcar_i2c_set_addr(priv, 1); | |
320 | rcar_i2c_status_clear(priv); | |
321 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); | |
322 | rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int rcar_i2c_send(struct rcar_i2c_priv *priv) | |
328 | { | |
329 | int ret; | |
330 | ||
331 | /* | |
332 | * It should check bus status when send case | |
333 | */ | |
334 | ret = rcar_i2c_bus_barrier(priv); | |
335 | if (ret < 0) | |
336 | return ret; | |
337 | ||
338 | rcar_i2c_set_addr(priv, 0); | |
339 | rcar_i2c_status_clear(priv); | |
340 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); | |
341 | rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | #define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE)) | |
347 | #define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR)) | |
348 | ||
349 | /* | |
350 | * interrupt functions | |
351 | */ | |
352 | static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |
353 | { | |
354 | struct i2c_msg *msg = priv->msg; | |
355 | ||
356 | /* | |
357 | * FIXME | |
358 | * sometimes, unknown interrupt happened. | |
359 | * Do nothing | |
360 | */ | |
361 | if (!(msr & MDE)) | |
362 | return 0; | |
363 | ||
364 | /* | |
365 | * If address transfer phase finished, | |
366 | * goto data phase. | |
367 | */ | |
368 | if (msr & MAT) | |
369 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); | |
370 | ||
371 | if (priv->pos < msg->len) { | |
372 | /* | |
373 | * Prepare next data to ICRXTX register. | |
374 | * This data will go to _SHIFT_ register. | |
375 | * | |
376 | * * | |
377 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
378 | */ | |
379 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
380 | priv->pos++; | |
381 | ||
382 | } else { | |
383 | /* | |
384 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
385 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
386 | * | |
387 | * * | |
388 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
389 | */ | |
390 | ||
391 | if (priv->flags & ID_LAST_MSG) | |
392 | /* | |
393 | * If current msg is the _LAST_ msg, | |
394 | * prepare stop condition here. | |
395 | * ID_DONE will be set on STOP irq. | |
396 | */ | |
397 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); | |
398 | else | |
399 | /* | |
400 | * If current msg is _NOT_ last msg, | |
401 | * it doesn't call stop phase. | |
402 | * thus, there is no STOP irq. | |
403 | * return ID_DONE here. | |
404 | */ | |
405 | return ID_DONE; | |
406 | } | |
407 | ||
408 | rcar_i2c_send_restart(priv); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |
414 | { | |
415 | struct i2c_msg *msg = priv->msg; | |
416 | ||
417 | /* | |
418 | * FIXME | |
419 | * sometimes, unknown interrupt happened. | |
420 | * Do nothing | |
421 | */ | |
422 | if (!(msr & MDR)) | |
423 | return 0; | |
424 | ||
425 | if (msr & MAT) { | |
426 | /* | |
427 | * Address transfer phase finished, | |
428 | * but, there is no data at this point. | |
429 | * Do nothing. | |
430 | */ | |
431 | } else if (priv->pos < msg->len) { | |
432 | /* | |
433 | * get received data | |
434 | */ | |
435 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); | |
436 | priv->pos++; | |
437 | } | |
438 | ||
439 | /* | |
440 | * If next received data is the _LAST_, | |
441 | * go to STOP phase, | |
442 | * otherwise, go to DATA phase. | |
443 | */ | |
444 | if (priv->pos + 1 >= msg->len) | |
445 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); | |
446 | else | |
447 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); | |
448 | ||
449 | rcar_i2c_recv_restart(priv); | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) | |
455 | { | |
456 | struct rcar_i2c_priv *priv = ptr; | |
457 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
458 | u32 msr; | |
459 | ||
460 | /*-------------- spin lock -----------------*/ | |
461 | spin_lock(&priv->lock); | |
462 | ||
463 | msr = rcar_i2c_status_get(priv); | |
464 | ||
465 | /* | |
466 | * Arbitration lost | |
467 | */ | |
468 | if (msr & MAL) { | |
469 | /* | |
470 | * CAUTION | |
471 | * | |
472 | * When arbitration lost, device become _slave_ mode. | |
473 | */ | |
474 | dev_dbg(dev, "Arbitration Lost\n"); | |
475 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); | |
476 | goto out; | |
477 | } | |
478 | ||
479 | /* | |
480 | * Stop | |
481 | */ | |
482 | if (msr & MST) { | |
483 | dev_dbg(dev, "Stop\n"); | |
484 | rcar_i2c_flags_set(priv, ID_DONE); | |
485 | goto out; | |
486 | } | |
487 | ||
488 | /* | |
489 | * Nack | |
490 | */ | |
491 | if (msr & MNR) { | |
492 | dev_dbg(dev, "Nack\n"); | |
493 | ||
494 | /* go to stop phase */ | |
495 | rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); | |
496 | rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); | |
497 | rcar_i2c_flags_set(priv, ID_NACK); | |
498 | goto out; | |
499 | } | |
500 | ||
501 | /* | |
502 | * recv/send | |
503 | */ | |
504 | if (rcar_i2c_is_recv(priv)) | |
505 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); | |
506 | else | |
507 | rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); | |
508 | ||
509 | out: | |
510 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | |
511 | rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); | |
512 | rcar_i2c_status_clear(priv); | |
513 | wake_up(&priv->wait); | |
514 | } | |
515 | ||
516 | spin_unlock(&priv->lock); | |
517 | /*-------------- spin unlock -----------------*/ | |
518 | ||
519 | return IRQ_HANDLED; | |
520 | } | |
521 | ||
522 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
523 | struct i2c_msg *msgs, | |
524 | int num) | |
525 | { | |
526 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
527 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
528 | unsigned long flags; | |
529 | int i, ret, timeout; | |
530 | ||
531 | pm_runtime_get_sync(dev); | |
532 | ||
533 | /*-------------- spin lock -----------------*/ | |
534 | spin_lock_irqsave(&priv->lock, flags); | |
535 | ||
536 | rcar_i2c_init(priv); | |
537 | rcar_i2c_clock_start(priv); | |
538 | ||
539 | spin_unlock_irqrestore(&priv->lock, flags); | |
540 | /*-------------- spin unlock -----------------*/ | |
541 | ||
542 | ret = -EINVAL; | |
543 | for (i = 0; i < num; i++) { | |
544 | /*-------------- spin lock -----------------*/ | |
545 | spin_lock_irqsave(&priv->lock, flags); | |
546 | ||
547 | /* init each data */ | |
548 | priv->msg = &msgs[i]; | |
549 | priv->pos = 0; | |
550 | priv->flags = 0; | |
551 | if (priv->msg == &msgs[num - 1]) | |
552 | rcar_i2c_flags_set(priv, ID_LAST_MSG); | |
553 | ||
554 | /* start send/recv */ | |
555 | if (rcar_i2c_is_recv(priv)) | |
556 | ret = rcar_i2c_recv(priv); | |
557 | else | |
558 | ret = rcar_i2c_send(priv); | |
559 | ||
560 | spin_unlock_irqrestore(&priv->lock, flags); | |
561 | /*-------------- spin unlock -----------------*/ | |
562 | ||
563 | if (ret < 0) | |
564 | break; | |
565 | ||
566 | /* | |
567 | * wait result | |
568 | */ | |
569 | timeout = wait_event_timeout(priv->wait, | |
570 | rcar_i2c_flags_has(priv, ID_DONE), | |
571 | 5 * HZ); | |
572 | if (!timeout) { | |
573 | ret = -ETIMEDOUT; | |
574 | break; | |
575 | } | |
576 | ||
577 | /* | |
578 | * error handling | |
579 | */ | |
580 | if (rcar_i2c_flags_has(priv, ID_NACK)) { | |
581 | ret = -EREMOTEIO; | |
582 | break; | |
583 | } | |
584 | ||
585 | if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { | |
586 | ret = -EAGAIN; | |
587 | break; | |
588 | } | |
589 | ||
590 | if (rcar_i2c_flags_has(priv, ID_IOERROR)) { | |
591 | ret = -EIO; | |
592 | break; | |
593 | } | |
594 | ||
595 | ret = i + 1; /* The number of transfer */ | |
596 | } | |
597 | ||
598 | pm_runtime_put(dev); | |
599 | ||
600 | if (ret < 0) | |
601 | dev_err(dev, "error %d : %x\n", ret, priv->flags); | |
602 | ||
603 | return ret; | |
604 | } | |
605 | ||
606 | static u32 rcar_i2c_func(struct i2c_adapter *adap) | |
607 | { | |
608 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
609 | } | |
610 | ||
611 | static const struct i2c_algorithm rcar_i2c_algo = { | |
612 | .master_xfer = rcar_i2c_master_xfer, | |
613 | .functionality = rcar_i2c_func, | |
614 | }; | |
615 | ||
0b255e92 | 616 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 KM |
617 | { |
618 | struct i2c_rcar_platform_data *pdata = pdev->dev.platform_data; | |
619 | struct rcar_i2c_priv *priv; | |
620 | struct i2c_adapter *adap; | |
621 | struct resource *res; | |
622 | struct device *dev = &pdev->dev; | |
623 | u32 bus_speed; | |
624 | int ret; | |
625 | ||
626 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
627 | if (!res) { | |
628 | dev_err(dev, "no mmio resources\n"); | |
629 | return -ENODEV; | |
630 | } | |
631 | ||
632 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); | |
633 | if (!priv) { | |
634 | dev_err(dev, "no mem for private data\n"); | |
635 | return -ENOMEM; | |
636 | } | |
637 | ||
638 | bus_speed = 100000; /* default 100 kHz */ | |
639 | if (pdata && pdata->bus_speed) | |
640 | bus_speed = pdata->bus_speed; | |
641 | ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); | |
642 | if (ret < 0) | |
643 | return ret; | |
644 | ||
b53f4baf | 645 | priv->io = devm_request_and_ioremap(dev, res); |
6ccbe607 KM |
646 | if (!priv->io) { |
647 | dev_err(dev, "cannot ioremap\n"); | |
648 | return -ENODEV; | |
649 | } | |
650 | ||
651 | priv->irq = platform_get_irq(pdev, 0); | |
652 | init_waitqueue_head(&priv->wait); | |
653 | spin_lock_init(&priv->lock); | |
654 | ||
655 | adap = &priv->adap; | |
656 | adap->nr = pdev->id; | |
657 | adap->algo = &rcar_i2c_algo; | |
658 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
659 | adap->retries = 3; | |
660 | adap->dev.parent = dev; | |
661 | i2c_set_adapdata(adap, priv); | |
662 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
663 | ||
664 | ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, | |
665 | dev_name(dev), priv); | |
666 | if (ret < 0) { | |
667 | dev_err(dev, "cannot get irq %d\n", priv->irq); | |
668 | return ret; | |
669 | } | |
670 | ||
671 | ret = i2c_add_numbered_adapter(adap); | |
672 | if (ret < 0) { | |
673 | dev_err(dev, "reg adap failed: %d\n", ret); | |
674 | return ret; | |
675 | } | |
676 | ||
677 | pm_runtime_enable(dev); | |
678 | platform_set_drvdata(pdev, priv); | |
679 | ||
680 | dev_info(dev, "probed\n"); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
0b255e92 | 685 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
686 | { |
687 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
688 | struct device *dev = &pdev->dev; | |
689 | ||
690 | i2c_del_adapter(&priv->adap); | |
691 | pm_runtime_disable(dev); | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
45fd5e4a | 696 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
697 | .driver = { |
698 | .name = "i2c-rcar", | |
699 | .owner = THIS_MODULE, | |
700 | }, | |
701 | .probe = rcar_i2c_probe, | |
0b255e92 | 702 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
703 | }; |
704 | ||
45fd5e4a | 705 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 KM |
706 | |
707 | MODULE_LICENSE("GPL"); | |
708 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); | |
709 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |