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Commit | Line | Data |
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6ccbe607 | 1 | /* |
5c8e3ab1 | 2 | * Driver for the Renesas R-Car I2C unit |
6ccbe607 | 3 | * |
3c2b1ff3 WS |
4 | * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> |
5 | * Copyright (C) 2011-2015 Renesas Electronics Corporation | |
3d99beab WS |
6 | * |
7 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
8 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
9 | * | |
10 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
11 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
12 | * | |
6ccbe607 KM |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 15 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
16 | * |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
6ccbe607 KM |
21 | */ |
22 | #include <linux/clk.h> | |
23 | #include <linux/delay.h> | |
73e8b052 NS |
24 | #include <linux/dmaengine.h> |
25 | #include <linux/dma-mapping.h> | |
6ccbe607 | 26 | #include <linux/err.h> |
6ccbe607 KM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/i2c.h> | |
6ccbe607 KM |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
7679c0e1 | 32 | #include <linux/of_device.h> |
6ccbe607 KM |
33 | #include <linux/platform_device.h> |
34 | #include <linux/pm_runtime.h> | |
fde773d5 | 35 | #include <linux/reset.h> |
6ccbe607 | 36 | #include <linux/slab.h> |
6ccbe607 KM |
37 | |
38 | /* register offsets */ | |
39 | #define ICSCR 0x00 /* slave ctrl */ | |
40 | #define ICMCR 0x04 /* master ctrl */ | |
41 | #define ICSSR 0x08 /* slave status */ | |
42 | #define ICMSR 0x0C /* master status */ | |
43 | #define ICSIER 0x10 /* slave irq enable */ | |
44 | #define ICMIER 0x14 /* master irq enable */ | |
45 | #define ICCCR 0x18 /* clock dividers */ | |
46 | #define ICSAR 0x1C /* slave address */ | |
47 | #define ICMAR 0x20 /* master address */ | |
48 | #define ICRXTX 0x24 /* data port */ | |
73e8b052 NS |
49 | #define ICDMAER 0x3c /* DMA enable */ |
50 | #define ICFBSCR 0x38 /* first bit setup cycle */ | |
6ccbe607 | 51 | |
de20d185 WS |
52 | /* ICSCR */ |
53 | #define SDBS (1 << 3) /* slave data buffer select */ | |
54 | #define SIE (1 << 2) /* slave interface enable */ | |
55 | #define GCAE (1 << 1) /* general call address enable */ | |
56 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
57 | ||
6ccbe607 KM |
58 | /* ICMCR */ |
59 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
60 | #define FSCL (1 << 6) /* override SCL pin */ | |
61 | #define FSDA (1 << 5) /* override SDA pin */ | |
62 | #define OBPC (1 << 4) /* override pins */ | |
63 | #define MIE (1 << 3) /* master if enable */ | |
64 | #define TSBE (1 << 2) | |
65 | #define FSB (1 << 1) /* force stop bit */ | |
66 | #define ESG (1 << 0) /* en startbit gen */ | |
67 | ||
de20d185 WS |
68 | /* ICSSR (also for ICSIER) */ |
69 | #define GCAR (1 << 6) /* general call received */ | |
70 | #define STM (1 << 5) /* slave transmit mode */ | |
71 | #define SSR (1 << 4) /* stop received */ | |
72 | #define SDE (1 << 3) /* slave data empty */ | |
73 | #define SDT (1 << 2) /* slave data transmitted */ | |
74 | #define SDR (1 << 1) /* slave data received */ | |
75 | #define SAR (1 << 0) /* slave addr received */ | |
76 | ||
3e3aabac | 77 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
78 | #define MNR (1 << 6) /* nack received */ |
79 | #define MAL (1 << 5) /* arbitration lost */ | |
80 | #define MST (1 << 4) /* sent a stop */ | |
81 | #define MDE (1 << 3) | |
82 | #define MDT (1 << 2) | |
83 | #define MDR (1 << 1) | |
84 | #define MAT (1 << 0) /* slave addr xfer done */ | |
85 | ||
73e8b052 NS |
86 | /* ICDMAER */ |
87 | #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ | |
88 | #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ | |
89 | #define RMDMAE (1 << 1) /* DMA Master Received Enable */ | |
90 | #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ | |
91 | ||
92 | /* ICFBSCR */ | |
93 | #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ | |
94 | #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ | |
95 | ||
6ccbe607 | 96 | |
4f443a8a WS |
97 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
98 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
52df445f | 99 | #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) |
4f443a8a | 100 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) |
6ccbe607 | 101 | |
3e3aabac WS |
102 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
103 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
104 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 105 | |
938916fb SS |
106 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
107 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 108 | |
6ccbe607 | 109 | #define ID_LAST_MSG (1 << 0) |
e49865d1 | 110 | #define ID_FIRST_MSG (1 << 1) |
6ccbe607 KM |
111 | #define ID_DONE (1 << 2) |
112 | #define ID_ARBLOST (1 << 3) | |
113 | #define ID_NACK (1 << 4) | |
7ee24eb5 | 114 | /* persistent flags */ |
fde773d5 | 115 | #define ID_P_NO_RXDMA (1 << 30) /* HW forbids RXDMA sometimes */ |
7ee24eb5 | 116 | #define ID_P_PM_BLOCKED (1 << 31) |
fde773d5 | 117 | #define ID_P_MASK (ID_P_PM_BLOCKED | ID_P_NO_RXDMA) |
6ccbe607 | 118 | |
b720423a | 119 | enum rcar_i2c_type { |
043a3f11 KM |
120 | I2C_RCAR_GEN1, |
121 | I2C_RCAR_GEN2, | |
e7db0d34 | 122 | I2C_RCAR_GEN3, |
b720423a NVD |
123 | }; |
124 | ||
6ccbe607 KM |
125 | struct rcar_i2c_priv { |
126 | void __iomem *io; | |
127 | struct i2c_adapter adap; | |
b9d0684c WS |
128 | struct i2c_msg *msg; |
129 | int msgs_left; | |
bc8120f1 | 130 | struct clk *clk; |
6ccbe607 | 131 | |
6ccbe607 KM |
132 | wait_queue_head_t wait; |
133 | ||
134 | int pos; | |
6ccbe607 KM |
135 | u32 icccr; |
136 | u32 flags; | |
51371cdc | 137 | enum rcar_i2c_type devtype; |
de20d185 | 138 | struct i2c_client *slave; |
73e8b052 NS |
139 | |
140 | struct resource *res; | |
141 | struct dma_chan *dma_tx; | |
142 | struct dma_chan *dma_rx; | |
143 | struct scatterlist sg; | |
144 | enum dma_data_direction dma_direction; | |
fde773d5 WS |
145 | |
146 | struct reset_control *rstc; | |
6ccbe607 KM |
147 | }; |
148 | ||
149 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
150 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
151 | ||
6ccbe607 KM |
152 | #define LOOP_TIMEOUT 1024 |
153 | ||
51371cdc | 154 | |
6ccbe607 KM |
155 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
156 | { | |
157 | writel(val, priv->io + reg); | |
158 | } | |
159 | ||
160 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
161 | { | |
162 | return readl(priv->io + reg); | |
163 | } | |
164 | ||
165 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
166 | { | |
6ccbe607 KM |
167 | /* reset master mode */ |
168 | rcar_i2c_write(priv, ICMIER, 0); | |
2c78cdc1 | 169 | rcar_i2c_write(priv, ICMCR, MDBS); |
6ccbe607 | 170 | rcar_i2c_write(priv, ICMSR, 0); |
2c78cdc1 WS |
171 | /* start clock */ |
172 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 KM |
173 | } |
174 | ||
6ccbe607 KM |
175 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
176 | { | |
177 | int i; | |
178 | ||
179 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
180 | /* make sure that bus is not busy */ | |
181 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
182 | return 0; | |
183 | udelay(1); | |
184 | } | |
185 | ||
186 | return -EBUSY; | |
187 | } | |
188 | ||
c7881871 | 189 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) |
6ccbe607 | 190 | { |
ca68eade | 191 | u32 scgd, cdf, round, ick, sum, scl, cdf_width; |
8d049403 | 192 | unsigned long rate; |
f9c9d31b | 193 | struct device *dev = rcar_i2c_priv_to_dev(priv); |
6ccbe607 | 194 | |
c7881871 WS |
195 | /* Fall back to previously used values if not supplied */ |
196 | t->bus_freq_hz = t->bus_freq_hz ?: 100000; | |
ca68eade WS |
197 | t->scl_fall_ns = t->scl_fall_ns ?: 35; |
198 | t->scl_rise_ns = t->scl_rise_ns ?: 200; | |
199 | t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; | |
6ccbe607 | 200 | |
b720423a | 201 | switch (priv->devtype) { |
043a3f11 | 202 | case I2C_RCAR_GEN1: |
b720423a NVD |
203 | cdf_width = 2; |
204 | break; | |
043a3f11 | 205 | case I2C_RCAR_GEN2: |
e7db0d34 | 206 | case I2C_RCAR_GEN3: |
b720423a NVD |
207 | cdf_width = 3; |
208 | break; | |
209 | default: | |
210 | dev_err(dev, "device type error\n"); | |
211 | return -EIO; | |
212 | } | |
213 | ||
6ccbe607 KM |
214 | /* |
215 | * calculate SCL clock | |
216 | * see | |
217 | * ICCCR | |
218 | * | |
219 | * ick = clkp / (1 + CDF) | |
220 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
221 | * | |
222 | * ick : I2C internal clock < 20 MHz | |
ca68eade WS |
223 | * ticf : I2C SCL falling time |
224 | * tr : I2C SCL rising time | |
225 | * intd : LSI internal delay | |
6ccbe607 KM |
226 | * clkp : peripheral_clk |
227 | * F[] : integer up-valuation | |
228 | */ | |
bc8120f1 | 229 | rate = clk_get_rate(priv->clk); |
8d049403 | 230 | cdf = rate / 20000000; |
22762ccb | 231 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
232 | dev_err(dev, "Input clock %lu too high\n", rate); |
233 | return -EIO; | |
6ccbe607 | 234 | } |
8d049403 | 235 | ick = rate / (cdf + 1); |
6ccbe607 | 236 | |
6ccbe607 KM |
237 | /* |
238 | * it is impossible to calculate large scale | |
239 | * number on u32. separate it | |
240 | * | |
ca68eade WS |
241 | * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) |
242 | * = F[sum * ick / 1000000000] | |
243 | * = F[(ick / 1000000) * sum / 1000] | |
6ccbe607 | 244 | */ |
ca68eade WS |
245 | sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; |
246 | round = (ick + 500000) / 1000000 * sum; | |
6ccbe607 KM |
247 | round = (round + 500) / 1000; |
248 | ||
249 | /* | |
250 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
251 | * | |
252 | * Calculation result (= SCL) should be less than | |
253 | * bus_speed for hardware safety | |
8d049403 GL |
254 | * |
255 | * We could use something along the lines of | |
256 | * div = ick / (bus_speed + 1) + 1; | |
257 | * scgd = (div - 20 - round + 7) / 8; | |
258 | * scl = ick / (20 + (scgd * 8) + round); | |
259 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
260 | */ |
261 | for (scgd = 0; scgd < 0x40; scgd++) { | |
262 | scl = ick / (20 + (scgd * 8) + round); | |
c7881871 | 263 | if (scl <= t->bus_freq_hz) |
6ccbe607 KM |
264 | goto scgd_find; |
265 | } | |
266 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
267 | return -EIO; | |
268 | ||
269 | scgd_find: | |
270 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
c7881871 | 271 | scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 | 272 | |
3c2b1ff3 | 273 | /* keep icccr value */ |
14d32f17 | 274 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
275 | |
276 | return 0; | |
277 | } | |
278 | ||
7c7117ff | 279 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 280 | { |
386babf8 | 281 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 282 | |
b9d0684c | 283 | priv->pos = 0; |
b9d0684c | 284 | if (priv->msgs_left == 1) |
42c0783b | 285 | priv->flags |= ID_LAST_MSG; |
b9d0684c | 286 | |
386babf8 | 287 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
e49865d1 WS |
288 | /* |
289 | * We don't have a testcase but the HW engineers say that the write order | |
290 | * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since | |
291 | * it didn't cause a drawback for me, let's rather be safe than sorry. | |
292 | */ | |
42c0783b | 293 | if (priv->flags & ID_FIRST_MSG) { |
e49865d1 WS |
294 | rcar_i2c_write(priv, ICMSR, 0); |
295 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
296 | } else { | |
297 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
298 | rcar_i2c_write(priv, ICMSR, 0); | |
299 | } | |
386babf8 | 300 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
301 | } |
302 | ||
cc21d0b4 WS |
303 | static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) |
304 | { | |
305 | priv->msg++; | |
306 | priv->msgs_left--; | |
7ee24eb5 | 307 | priv->flags &= ID_P_MASK; |
cc21d0b4 WS |
308 | rcar_i2c_prepare_msg(priv); |
309 | } | |
310 | ||
6ccbe607 KM |
311 | /* |
312 | * interrupt functions | |
313 | */ | |
73e8b052 NS |
314 | static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) |
315 | { | |
316 | struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE | |
317 | ? priv->dma_rx : priv->dma_tx; | |
318 | ||
319 | /* Disable DMA Master Received/Transmitted */ | |
320 | rcar_i2c_write(priv, ICDMAER, 0); | |
321 | ||
322 | /* Reset default delay */ | |
323 | rcar_i2c_write(priv, ICFBSCR, TCYC06); | |
324 | ||
325 | dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), | |
91633503 | 326 | sg_dma_len(&priv->sg), priv->dma_direction); |
73e8b052 | 327 | |
fde773d5 WS |
328 | /* Gen3 can only do one RXDMA per transfer and we just completed it */ |
329 | if (priv->devtype == I2C_RCAR_GEN3 && | |
330 | priv->dma_direction == DMA_FROM_DEVICE) | |
331 | priv->flags |= ID_P_NO_RXDMA; | |
332 | ||
73e8b052 NS |
333 | priv->dma_direction = DMA_NONE; |
334 | } | |
335 | ||
336 | static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) | |
337 | { | |
338 | if (priv->dma_direction == DMA_NONE) | |
339 | return; | |
340 | else if (priv->dma_direction == DMA_FROM_DEVICE) | |
341 | dmaengine_terminate_all(priv->dma_rx); | |
342 | else if (priv->dma_direction == DMA_TO_DEVICE) | |
343 | dmaengine_terminate_all(priv->dma_tx); | |
344 | ||
345 | rcar_i2c_dma_unmap(priv); | |
346 | } | |
347 | ||
348 | static void rcar_i2c_dma_callback(void *data) | |
349 | { | |
350 | struct rcar_i2c_priv *priv = data; | |
351 | ||
352 | priv->pos += sg_dma_len(&priv->sg); | |
353 | ||
354 | rcar_i2c_dma_unmap(priv); | |
355 | } | |
356 | ||
357 | static void rcar_i2c_dma(struct rcar_i2c_priv *priv) | |
358 | { | |
359 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
360 | struct i2c_msg *msg = priv->msg; | |
361 | bool read = msg->flags & I2C_M_RD; | |
362 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
363 | struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; | |
364 | struct dma_async_tx_descriptor *txdesc; | |
365 | dma_addr_t dma_addr; | |
366 | dma_cookie_t cookie; | |
367 | unsigned char *buf; | |
368 | int len; | |
369 | ||
fde773d5 WS |
370 | /* Do various checks to see if DMA is feasible at all */ |
371 | if (IS_ERR(chan) || msg->len < 8 || | |
372 | (read && priv->flags & ID_P_NO_RXDMA)) | |
73e8b052 NS |
373 | return; |
374 | ||
375 | if (read) { | |
376 | /* | |
377 | * The last two bytes needs to be fetched using PIO in | |
378 | * order for the STOP phase to work. | |
379 | */ | |
380 | buf = priv->msg->buf; | |
381 | len = priv->msg->len - 2; | |
382 | } else { | |
383 | /* | |
384 | * First byte in message was sent using PIO. | |
385 | */ | |
386 | buf = priv->msg->buf + 1; | |
387 | len = priv->msg->len - 1; | |
388 | } | |
389 | ||
390 | dma_addr = dma_map_single(chan->device->dev, buf, len, dir); | |
c13c2918 | 391 | if (dma_mapping_error(chan->device->dev, dma_addr)) { |
73e8b052 NS |
392 | dev_dbg(dev, "dma map failed, using PIO\n"); |
393 | return; | |
394 | } | |
395 | ||
396 | sg_dma_len(&priv->sg) = len; | |
397 | sg_dma_address(&priv->sg) = dma_addr; | |
398 | ||
399 | priv->dma_direction = dir; | |
400 | ||
401 | txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, | |
402 | read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, | |
403 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
404 | if (!txdesc) { | |
405 | dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); | |
406 | rcar_i2c_cleanup_dma(priv); | |
407 | return; | |
408 | } | |
409 | ||
410 | txdesc->callback = rcar_i2c_dma_callback; | |
411 | txdesc->callback_param = priv; | |
412 | ||
413 | cookie = dmaengine_submit(txdesc); | |
414 | if (dma_submit_error(cookie)) { | |
415 | dev_dbg(dev, "submitting dma failed, using PIO\n"); | |
416 | rcar_i2c_cleanup_dma(priv); | |
417 | return; | |
418 | } | |
419 | ||
420 | /* Set delay for DMA operations */ | |
421 | rcar_i2c_write(priv, ICFBSCR, TCYC17); | |
422 | ||
423 | /* Enable DMA Master Received/Transmitted */ | |
424 | if (read) | |
425 | rcar_i2c_write(priv, ICDMAER, RMDMAE); | |
426 | else | |
427 | rcar_i2c_write(priv, ICDMAER, TMDMAE); | |
428 | ||
429 | dma_async_issue_pending(chan); | |
430 | } | |
431 | ||
cc21d0b4 | 432 | static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
433 | { |
434 | struct i2c_msg *msg = priv->msg; | |
435 | ||
3c2b1ff3 | 436 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 437 | if (!(msr & MDE)) |
cc21d0b4 | 438 | return; |
6ccbe607 KM |
439 | |
440 | if (priv->pos < msg->len) { | |
441 | /* | |
442 | * Prepare next data to ICRXTX register. | |
443 | * This data will go to _SHIFT_ register. | |
444 | * | |
445 | * * | |
446 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
447 | */ | |
448 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
449 | priv->pos++; | |
450 | ||
73e8b052 NS |
451 | /* |
452 | * Try to use DMA to transmit the rest of the data if | |
453 | * address transfer pashe just finished. | |
454 | */ | |
455 | if (msr & MAT) | |
456 | rcar_i2c_dma(priv); | |
6ccbe607 KM |
457 | } else { |
458 | /* | |
459 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
460 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
461 | * | |
462 | * * | |
463 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
464 | */ | |
465 | ||
cc21d0b4 | 466 | if (priv->flags & ID_LAST_MSG) { |
6ccbe607 KM |
467 | /* |
468 | * If current msg is the _LAST_ msg, | |
469 | * prepare stop condition here. | |
470 | * ID_DONE will be set on STOP irq. | |
471 | */ | |
4f443a8a | 472 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
cc21d0b4 WS |
473 | } else { |
474 | rcar_i2c_next_msg(priv); | |
475 | return; | |
476 | } | |
6ccbe607 KM |
477 | } |
478 | ||
3c95de67 | 479 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
480 | } |
481 | ||
cc21d0b4 | 482 | static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
483 | { |
484 | struct i2c_msg *msg = priv->msg; | |
485 | ||
3c2b1ff3 | 486 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 487 | if (!(msr & MDR)) |
cc21d0b4 | 488 | return; |
6ccbe607 KM |
489 | |
490 | if (msr & MAT) { | |
73e8b052 NS |
491 | /* |
492 | * Address transfer phase finished, but no data at this point. | |
493 | * Try to use DMA to receive data. | |
494 | */ | |
495 | rcar_i2c_dma(priv); | |
6ccbe607 | 496 | } else if (priv->pos < msg->len) { |
3c2b1ff3 | 497 | /* get received data */ |
6ccbe607 KM |
498 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); |
499 | priv->pos++; | |
500 | } | |
501 | ||
502 | /* | |
3c2b1ff3 WS |
503 | * If next received data is the _LAST_, go to STOP phase. Might be |
504 | * overwritten by REP START when setting up a new msg. Not elegant | |
505 | * but the only stable sequence for REP START I have found so far. | |
6ccbe607 KM |
506 | */ |
507 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 508 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 509 | |
cc21d0b4 WS |
510 | if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) |
511 | rcar_i2c_next_msg(priv); | |
512 | else | |
513 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); | |
6ccbe607 KM |
514 | } |
515 | ||
de20d185 WS |
516 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
517 | { | |
518 | u32 ssr_raw, ssr_filtered; | |
519 | u8 value; | |
520 | ||
521 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
522 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
523 | ||
524 | if (!ssr_filtered) | |
525 | return false; | |
526 | ||
527 | /* address detected */ | |
528 | if (ssr_filtered & SAR) { | |
529 | /* read or write request */ | |
530 | if (ssr_raw & STM) { | |
5b77d162 | 531 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
532 | rcar_i2c_write(priv, ICRXTX, value); |
533 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
534 | } else { | |
5b77d162 | 535 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
536 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
537 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
538 | } | |
539 | ||
540 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
541 | } | |
542 | ||
543 | /* master sent stop */ | |
544 | if (ssr_filtered & SSR) { | |
545 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
546 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
547 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
548 | } | |
549 | ||
550 | /* master wants to write to us */ | |
551 | if (ssr_filtered & SDR) { | |
552 | int ret; | |
553 | ||
554 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 555 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
556 | /* Send NACK in case of error */ |
557 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
558 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
559 | } | |
560 | ||
561 | /* master wants to read from us */ | |
562 | if (ssr_filtered & SDE) { | |
5b77d162 | 563 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
564 | rcar_i2c_write(priv, ICRXTX, value); |
565 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
566 | } | |
567 | ||
568 | return true; | |
569 | } | |
570 | ||
6ccbe607 KM |
571 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
572 | { | |
573 | struct rcar_i2c_priv *priv = ptr; | |
52df445f | 574 | u32 msr, val; |
91bfe298 | 575 | |
52df445f WS |
576 | /* Clear START or STOP as soon as we can */ |
577 | val = rcar_i2c_read(priv, ICMCR); | |
578 | rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); | |
de20d185 | 579 | |
1c176d53 | 580 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 581 | |
dd318b0d SS |
582 | /* Only handle interrupts that are currently enabled */ |
583 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 | 584 | if (!msr) { |
c3be0af1 WS |
585 | if (rcar_i2c_slave_irq(priv)) |
586 | return IRQ_HANDLED; | |
587 | ||
588 | return IRQ_NONE; | |
aa5beaf6 | 589 | } |
dd318b0d | 590 | |
51371cdc | 591 | /* Arbitration lost */ |
6ccbe607 | 592 | if (msr & MAL) { |
42c0783b | 593 | priv->flags |= ID_DONE | ID_ARBLOST; |
6ccbe607 KM |
594 | goto out; |
595 | } | |
596 | ||
51371cdc | 597 | /* Nack */ |
6ccbe607 | 598 | if (msr & MNR) { |
d89667b1 | 599 | /* HW automatically sends STOP after received NACK */ |
f2382249 | 600 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
42c0783b | 601 | priv->flags |= ID_NACK; |
6ccbe607 KM |
602 | goto out; |
603 | } | |
604 | ||
dd318b0d SS |
605 | /* Stop */ |
606 | if (msr & MST) { | |
cc21d0b4 | 607 | priv->msgs_left--; /* The last message also made it */ |
42c0783b | 608 | priv->flags |= ID_DONE; |
dd318b0d SS |
609 | goto out; |
610 | } | |
611 | ||
6ccbe607 | 612 | if (rcar_i2c_is_recv(priv)) |
cc21d0b4 | 613 | rcar_i2c_irq_recv(priv, msr); |
6ccbe607 | 614 | else |
cc21d0b4 | 615 | rcar_i2c_irq_send(priv, msr); |
6ccbe607 KM |
616 | |
617 | out: | |
42c0783b | 618 | if (priv->flags & ID_DONE) { |
f2382249 | 619 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 620 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
621 | wake_up(&priv->wait); |
622 | } | |
623 | ||
c3be0af1 | 624 | return IRQ_HANDLED; |
6ccbe607 KM |
625 | } |
626 | ||
73e8b052 NS |
627 | static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, |
628 | enum dma_transfer_direction dir, | |
629 | dma_addr_t port_addr) | |
630 | { | |
631 | struct dma_chan *chan; | |
632 | struct dma_slave_config cfg; | |
633 | char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; | |
634 | int ret; | |
635 | ||
6aabf9d0 | 636 | chan = dma_request_chan(dev, chan_name); |
73e8b052 | 637 | if (IS_ERR(chan)) { |
8ae034c2 ER |
638 | dev_dbg(dev, "request_channel failed for %s (%ld)\n", |
639 | chan_name, PTR_ERR(chan)); | |
73e8b052 NS |
640 | return chan; |
641 | } | |
642 | ||
643 | memset(&cfg, 0, sizeof(cfg)); | |
644 | cfg.direction = dir; | |
645 | if (dir == DMA_MEM_TO_DEV) { | |
646 | cfg.dst_addr = port_addr; | |
647 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
648 | } else { | |
649 | cfg.src_addr = port_addr; | |
650 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
651 | } | |
652 | ||
653 | ret = dmaengine_slave_config(chan, &cfg); | |
654 | if (ret) { | |
655 | dev_dbg(dev, "slave_config failed for %s (%d)\n", | |
656 | chan_name, ret); | |
657 | dma_release_channel(chan); | |
658 | return ERR_PTR(ret); | |
659 | } | |
660 | ||
661 | dev_dbg(dev, "got DMA channel for %s\n", chan_name); | |
662 | return chan; | |
663 | } | |
664 | ||
665 | static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, | |
666 | struct i2c_msg *msg) | |
667 | { | |
668 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
669 | bool read; | |
670 | struct dma_chan *chan; | |
671 | enum dma_transfer_direction dir; | |
672 | ||
673 | read = msg->flags & I2C_M_RD; | |
674 | ||
675 | chan = read ? priv->dma_rx : priv->dma_tx; | |
676 | if (PTR_ERR(chan) != -EPROBE_DEFER) | |
677 | return; | |
678 | ||
679 | dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; | |
680 | chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); | |
681 | ||
682 | if (read) | |
683 | priv->dma_rx = chan; | |
684 | else | |
685 | priv->dma_tx = chan; | |
686 | } | |
687 | ||
688 | static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) | |
689 | { | |
690 | if (!IS_ERR(priv->dma_tx)) { | |
691 | dma_release_channel(priv->dma_tx); | |
692 | priv->dma_tx = ERR_PTR(-EPROBE_DEFER); | |
693 | } | |
694 | ||
695 | if (!IS_ERR(priv->dma_rx)) { | |
696 | dma_release_channel(priv->dma_rx); | |
697 | priv->dma_rx = ERR_PTR(-EPROBE_DEFER); | |
698 | } | |
699 | } | |
700 | ||
fde773d5 WS |
701 | /* I2C is a special case, we need to poll the status of a reset */ |
702 | static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) | |
703 | { | |
704 | int i, ret; | |
705 | ||
706 | ret = reset_control_reset(priv->rstc); | |
707 | if (ret) | |
708 | return ret; | |
709 | ||
710 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
711 | ret = reset_control_status(priv->rstc); | |
712 | if (ret == 0) | |
713 | return 0; | |
714 | udelay(1); | |
715 | } | |
716 | ||
717 | return -ETIMEDOUT; | |
718 | } | |
719 | ||
6ccbe607 KM |
720 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, |
721 | struct i2c_msg *msgs, | |
722 | int num) | |
723 | { | |
724 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
725 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
b6763d0d | 726 | int i, ret; |
ff2316b8 | 727 | long time_left; |
6ccbe607 KM |
728 | |
729 | pm_runtime_get_sync(dev); | |
730 | ||
fde773d5 WS |
731 | /* Gen3 needs a reset before allowing RXDMA once */ |
732 | if (priv->devtype == I2C_RCAR_GEN3) { | |
733 | priv->flags |= ID_P_NO_RXDMA; | |
734 | if (!IS_ERR(priv->rstc)) { | |
735 | ret = rcar_i2c_do_reset(priv); | |
736 | if (ret == 0) | |
737 | priv->flags &= ~ID_P_NO_RXDMA; | |
738 | } | |
739 | } | |
740 | ||
ae481cc1 WS |
741 | rcar_i2c_init(priv); |
742 | ||
3f7de22e WS |
743 | ret = rcar_i2c_bus_barrier(priv); |
744 | if (ret < 0) | |
745 | goto out; | |
746 | ||
6ccbe607 | 747 | for (i = 0; i < num; i++) { |
d7653964 WS |
748 | /* This HW can't send STOP after address phase */ |
749 | if (msgs[i].len == 0) { | |
750 | ret = -EOPNOTSUPP; | |
cc21d0b4 | 751 | goto out; |
6ccbe607 | 752 | } |
73e8b052 | 753 | rcar_i2c_request_dma(priv, msgs + i); |
cc21d0b4 | 754 | } |
6ccbe607 | 755 | |
e49865d1 | 756 | /* init first message */ |
cc21d0b4 WS |
757 | priv->msg = msgs; |
758 | priv->msgs_left = num; | |
7ee24eb5 | 759 | priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; |
cc21d0b4 WS |
760 | rcar_i2c_prepare_msg(priv); |
761 | ||
42c0783b | 762 | time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, |
cc21d0b4 WS |
763 | num * adap->timeout); |
764 | if (!time_left) { | |
73e8b052 | 765 | rcar_i2c_cleanup_dma(priv); |
cc21d0b4 WS |
766 | rcar_i2c_init(priv); |
767 | ret = -ETIMEDOUT; | |
42c0783b | 768 | } else if (priv->flags & ID_NACK) { |
cc21d0b4 | 769 | ret = -ENXIO; |
42c0783b | 770 | } else if (priv->flags & ID_ARBLOST) { |
cc21d0b4 WS |
771 | ret = -EAGAIN; |
772 | } else { | |
773 | ret = num - priv->msgs_left; /* The number of transfer */ | |
6ccbe607 | 774 | } |
3f7de22e | 775 | out: |
6ccbe607 KM |
776 | pm_runtime_put(dev); |
777 | ||
6ff4b105 | 778 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
779 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
780 | ||
781 | return ret; | |
782 | } | |
783 | ||
de20d185 WS |
784 | static int rcar_reg_slave(struct i2c_client *slave) |
785 | { | |
786 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
787 | ||
788 | if (priv->slave) | |
789 | return -EBUSY; | |
790 | ||
791 | if (slave->flags & I2C_CLIENT_TEN) | |
792 | return -EAFNOSUPPORT; | |
793 | ||
63a761ee | 794 | /* Keep device active for slave address detection logic */ |
b4cd08aa | 795 | pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
796 | |
797 | priv->slave = slave; | |
798 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
799 | rcar_i2c_write(priv, ICSSR, 0); | |
800 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
801 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | static int rcar_unreg_slave(struct i2c_client *slave) | |
807 | { | |
808 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
809 | ||
810 | WARN_ON(!priv->slave); | |
811 | ||
812 | rcar_i2c_write(priv, ICSIER, 0); | |
813 | rcar_i2c_write(priv, ICSCR, 0); | |
814 | ||
815 | priv->slave = NULL; | |
816 | ||
b4cd08aa | 817 | pm_runtime_put(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
818 | |
819 | return 0; | |
820 | } | |
821 | ||
6ccbe607 KM |
822 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
823 | { | |
b395ba21 WS |
824 | /* |
825 | * This HW can't do: | |
826 | * I2C_SMBUS_QUICK (setting FSB during START didn't work) | |
827 | * I2C_M_NOSTART (automatically sends address after START) | |
828 | * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) | |
829 | */ | |
1fb2ad95 WS |
830 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
831 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
832 | } |
833 | ||
834 | static const struct i2c_algorithm rcar_i2c_algo = { | |
835 | .master_xfer = rcar_i2c_master_xfer, | |
836 | .functionality = rcar_i2c_func, | |
de20d185 WS |
837 | .reg_slave = rcar_reg_slave, |
838 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
839 | }; |
840 | ||
7679c0e1 | 841 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
842 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, |
843 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
844 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 845 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
846 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
847 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
848 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 849 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
c13f743a | 850 | { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, |
ad4a8dc3 SH |
851 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ |
852 | { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, | |
853 | { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, | |
854 | { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, | |
7679c0e1 GL |
855 | {}, |
856 | }; | |
857 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
858 | ||
0b255e92 | 859 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 860 | { |
6ccbe607 KM |
861 | struct rcar_i2c_priv *priv; |
862 | struct i2c_adapter *adap; | |
6ccbe607 | 863 | struct device *dev = &pdev->dev; |
c7881871 | 864 | struct i2c_timings i2c_t; |
93e953d3 | 865 | int irq, ret; |
6ccbe607 | 866 | |
6ccbe607 | 867 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 868 | if (!priv) |
6ccbe607 | 869 | return -ENOMEM; |
6ccbe607 | 870 | |
bc8120f1 BD |
871 | priv->clk = devm_clk_get(dev, NULL); |
872 | if (IS_ERR(priv->clk)) { | |
873 | dev_err(dev, "cannot get clock\n"); | |
874 | return PTR_ERR(priv->clk); | |
875 | } | |
876 | ||
73e8b052 NS |
877 | priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
878 | ||
879 | priv->io = devm_ioremap_resource(dev, priv->res); | |
84dbf809 TR |
880 | if (IS_ERR(priv->io)) |
881 | return PTR_ERR(priv->io); | |
6ccbe607 | 882 | |
69e558fa | 883 | priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); |
6ccbe607 | 884 | init_waitqueue_head(&priv->wait); |
6ccbe607 | 885 | |
929e3aba WS |
886 | adap = &priv->adap; |
887 | adap->nr = pdev->id; | |
888 | adap->algo = &rcar_i2c_algo; | |
889 | adap->class = I2C_CLASS_DEPRECATED; | |
890 | adap->retries = 3; | |
891 | adap->dev.parent = dev; | |
892 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
893 | i2c_set_adapdata(adap, priv); |
894 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
895 | ||
c7881871 | 896 | i2c_parse_fw_timings(dev, &i2c_t, false); |
f9c9d31b | 897 | |
73e8b052 NS |
898 | /* Init DMA */ |
899 | sg_init_table(&priv->sg, 1); | |
900 | priv->dma_direction = DMA_NONE; | |
901 | priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); | |
902 | ||
63a761ee | 903 | /* Activate device for clock calculation */ |
f9c9d31b WS |
904 | pm_runtime_enable(dev); |
905 | pm_runtime_get_sync(dev); | |
c7881871 | 906 | ret = rcar_i2c_clock_calculate(priv, &i2c_t); |
f9c9d31b WS |
907 | if (ret < 0) |
908 | goto out_pm_put; | |
909 | ||
fde773d5 WS |
910 | if (priv->devtype == I2C_RCAR_GEN3) { |
911 | priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); | |
912 | if (!IS_ERR(priv->rstc)) { | |
913 | ret = reset_control_status(priv->rstc); | |
914 | if (ret < 0) | |
915 | priv->rstc = ERR_PTR(-ENOTSUPP); | |
916 | } | |
917 | } | |
918 | ||
63a761ee | 919 | /* Stay always active when multi-master to keep arbitration working */ |
7ee24eb5 WS |
920 | if (of_property_read_bool(dev->of_node, "multi-master")) |
921 | priv->flags |= ID_P_PM_BLOCKED; | |
922 | else | |
923 | pm_runtime_put(dev); | |
924 | ||
f9c9d31b WS |
925 | |
926 | irq = platform_get_irq(pdev, 0); | |
927 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); | |
6ccbe607 | 928 | if (ret < 0) { |
93e953d3 | 929 | dev_err(dev, "cannot get irq %d\n", irq); |
e43e0df1 | 930 | goto out_pm_disable; |
6ccbe607 KM |
931 | } |
932 | ||
4f7effdd WS |
933 | platform_set_drvdata(pdev, priv); |
934 | ||
6ccbe607 | 935 | ret = i2c_add_numbered_adapter(adap); |
ea734404 | 936 | if (ret < 0) |
e43e0df1 | 937 | goto out_pm_disable; |
6ccbe607 | 938 | |
6ccbe607 KM |
939 | dev_info(dev, "probed\n"); |
940 | ||
941 | return 0; | |
e43e0df1 WS |
942 | |
943 | out_pm_put: | |
944 | pm_runtime_put(dev); | |
945 | out_pm_disable: | |
946 | pm_runtime_disable(dev); | |
947 | return ret; | |
6ccbe607 KM |
948 | } |
949 | ||
0b255e92 | 950 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
951 | { |
952 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
953 | struct device *dev = &pdev->dev; | |
954 | ||
955 | i2c_del_adapter(&priv->adap); | |
73e8b052 | 956 | rcar_i2c_release_dma(priv); |
7ee24eb5 WS |
957 | if (priv->flags & ID_P_PM_BLOCKED) |
958 | pm_runtime_put(dev); | |
6ccbe607 KM |
959 | pm_runtime_disable(dev); |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
45fd5e4a | 964 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
965 | .driver = { |
966 | .name = "i2c-rcar", | |
7679c0e1 | 967 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
968 | }, |
969 | .probe = rcar_i2c_probe, | |
0b255e92 | 970 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
971 | }; |
972 | ||
45fd5e4a | 973 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 974 | |
3d99beab | 975 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
976 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
977 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |