[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-riic.c

/*
 * Renesas RIIC driver
 *
 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
 * Copyright (C) 2013 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

/*
 * This i2c core has a lot of interrupts, namely 8. We use their chaining as
 * some kind of state machine.
 *
 * 1) The main xfer routine kicks off a transmission by putting the start bit
 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
 * since we need to send the slave address + RW bit in every case.
 *
 * 2) TIE sends slave address + RW bit and selects how to continue.
 *
 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
 * are done, we switch over to the transmission done interrupt (TEIE) and mark
 * the message as completed (includes sending STOP) there.
 *
 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
 * needed to start clocking, then we keep receiving until we are done. Note
 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
 * message to create the final NACK as sketched in the datasheet. This caused
 * some subtle races (when byte n was processed and byte n+1 was already
 * waiting), though, and I started with the safe approach.
 *
 * 4) If we got a NACK somewhere, we flag the error and stop the transmission
 * via NAKIE.
 *
 * Also check the comments in the interrupt routines for some gory details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#define RIIC_ICCR1	0x00
#define RIIC_ICCR2	0x04
#define RIIC_ICMR1	0x08
#define RIIC_ICMR3	0x10
#define RIIC_ICSER	0x18
#define RIIC_ICIER	0x1c
#define RIIC_ICSR2	0x24
#define RIIC_ICBRL	0x34
#define RIIC_ICBRH	0x38
#define RIIC_ICDRT	0x3c
#define RIIC_ICDRR	0x40

#define ICCR1_ICE	0x80
#define ICCR1_IICRST	0x40
#define ICCR1_SOWP	0x10

#define ICCR2_BBSY	0x80
#define ICCR2_SP	0x08
#define ICCR2_RS	0x04
#define ICCR2_ST	0x02

#define ICMR1_CKS_MASK	0x70
#define ICMR1_BCWP	0x08
#define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)

#define ICMR3_RDRFS	0x20
#define ICMR3_ACKWP	0x10
#define ICMR3_ACKBT	0x08

#define ICIER_TIE	0x80
#define ICIER_TEIE	0x40
#define ICIER_RIE	0x20
#define ICIER_NAKIE	0x10
#define ICIER_SPIE	0x08

#define ICSR2_NACKF	0x10

#define ICBR_RESERVED	0xe0 /* Should be 1 on writes */

#define RIIC_INIT_MSG	-1

struct riic_dev {
	void __iomem *base;
	u8 *buf;
	struct i2c_msg *msg;
	int bytes_left;
	int err;
	int is_last;
	struct completion msg_done;
	struct i2c_adapter adapter;
	struct clk *clk;
};

struct riic_irq_desc {
	int res_num;
	irq_handler_t isr;
	char *name;
};

static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
{
	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
}

static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
{
	struct riic_dev *riic = i2c_get_adapdata(adap);
	unsigned long time_left;
	int i, ret;
	u8 start_bit;

	ret = clk_prepare_enable(riic->clk);
	if (ret)
		return ret;

	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
		riic->err = -EBUSY;
		goto out;
	}

	reinit_completion(&riic->msg_done);
	riic->err = 0;

	writeb(0, riic->base + RIIC_ICSR2);

	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
		riic->bytes_left = RIIC_INIT_MSG;
		riic->buf = msgs[i].buf;
		riic->msg = &msgs[i];
		riic->is_last = (i == num - 1);

		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);

		writeb(start_bit, riic->base + RIIC_ICCR2);

		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
		if (time_left == 0)
			riic->err = -ETIMEDOUT;

		if (riic->err)
			break;

		start_bit = ICCR2_RS;
	}

 out:
	clk_disable_unprepare(riic->clk);

	return riic->err ?: num;
}

static irqreturn_t riic_tdre_isr(int irq, void *data)
{
	struct riic_dev *riic = data;
	u8 val;

	if (!riic->bytes_left)
		return IRQ_NONE;

	if (riic->bytes_left == RIIC_INIT_MSG) {
		val = !!(riic->msg->flags & I2C_M_RD);
		if (val)
			/* On read, switch over to receive interrupt */
			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
		else
			/* On write, initialize length */
			riic->bytes_left = riic->msg->len;

		val |= (riic->msg->addr << 1);
	} else {
		val = *riic->buf;
		riic->buf++;
		riic->bytes_left--;
	}

	/*
	 * Switch to transmission ended interrupt when done. Do check here
	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
	 * 0 length then)
	 */
	if (riic->bytes_left == 0)
		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);

	/*
	 * This acks the TIE interrupt. We get another TIE immediately if our
	 * value could be moved to the shadow shift register right away. So
	 * this must be after updates to ICIER (where we want to disable TIE)!
	 */
	writeb(val, riic->base + RIIC_ICDRT);

	return IRQ_HANDLED;
}

static irqreturn_t riic_tend_isr(int irq, void *data)
{
	struct riic_dev *riic = data;

	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
		/* We got a NACKIE */
		readb(riic->base + RIIC_ICDRR);	/* dummy read */
		riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
		riic->err = -ENXIO;
	} else if (riic->bytes_left) {
		return IRQ_NONE;
	}

	if (riic->is_last || riic->err) {
		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
	} else {
		/* Transfer is complete, but do not send STOP */
		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
		complete(&riic->msg_done);
	}

	return IRQ_HANDLED;
}

static irqreturn_t riic_rdrf_isr(int irq, void *data)
{
	struct riic_dev *riic = data;

	if (!riic->bytes_left)
		return IRQ_NONE;

	if (riic->bytes_left == RIIC_INIT_MSG) {
		riic->bytes_left = riic->msg->len;
		readb(riic->base + RIIC_ICDRR);	/* dummy read */
		return IRQ_HANDLED;
	}

	if (riic->bytes_left == 1) {
		/* STOP must come before we set ACKBT! */
		if (riic->is_last) {
			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
		}

		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);

	} else {
		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
	}

	/* Reading acks the RIE interrupt */
	*riic->buf = readb(riic->base + RIIC_ICDRR);
	riic->buf++;
	riic->bytes_left--;

	return IRQ_HANDLED;
}

static irqreturn_t riic_stop_isr(int irq, void *data)
{
	struct riic_dev *riic = data;

	/* read back registers to confirm writes have fully propagated */
	writeb(0, riic->base + RIIC_ICSR2);
	readb(riic->base + RIIC_ICSR2);
	writeb(0, riic->base + RIIC_ICIER);
	readb(riic->base + RIIC_ICIER);

	complete(&riic->msg_done);

	return IRQ_HANDLED;
}

static u32 riic_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm riic_algo = {
	.master_xfer	= riic_xfer,
	.functionality	= riic_func,
};

static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
{
	int ret;
	unsigned long rate;
	int total_ticks, cks, brl, brh;

	ret = clk_prepare_enable(riic->clk);
	if (ret)
		return ret;

	if (t->bus_freq_hz > 400000) {
		dev_err(&riic->adapter.dev,
			"unsupported bus speed (%dHz). 400000 max\n",
			t->bus_freq_hz);
		clk_disable_unprepare(riic->clk);
		return -EINVAL;
	}

	rate = clk_get_rate(riic->clk);

	/*
	 * Assume the default register settings:
	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
	 *  FER.NFE = 1 (noise circuit enabled)
	 *  MR3.NF = 0 (1 cycle of noise filtered out)
	 *
	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
	 */

	/*
	 * Determine reference clock rate. We must be able to get the desired
	 * frequency with only 62 clock ticks max (31 high, 31 low).
	 * Aim for a duty of 60% LOW, 40% HIGH.
	 */
	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);

	for (cks = 0; cks < 7; cks++) {
		/*
		 * 60% low time must be less than BRL + 2 + 1
		 * BRL max register value is 0x1F.
		 */
		brl = ((total_ticks * 6) / 10);
		if (brl <= (0x1F + 3))
			break;

		total_ticks /= 2;
		rate /= 2;
	}

	if (brl > (0x1F + 3)) {
		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
			(unsigned long)t->bus_freq_hz);
		clk_disable_unprepare(riic->clk);
		return -EINVAL;
	}

	brh = total_ticks - brl;

	/* Remove automatic clock ticks for sync circuit and NF */
	if (cks == 0) {
		brl -= 4;
		brh -= 4;
	} else {
		brl -= 3;
		brh -= 3;
	}

	/*
	 * Remove clock ticks for rise and fall times. Convert ns to clock
	 * ticks.
	 */
	brl -= t->scl_fall_ns / (1000000000 / rate);
	brh -= t->scl_rise_ns / (1000000000 / rate);

	/* Adjust for min register values for when SCLE=1 and NFE=1 */
	if (brl < 1)
		brl = 1;
	if (brh < 1)
		brh = 1;

	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
		 t->scl_fall_ns / (1000000000 / rate),
		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);

	/* Changing the order of accessing IICRST and ICE may break things! */
	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);

	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);

	writeb(0, riic->base + RIIC_ICSER);
	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);

	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);

	clk_disable_unprepare(riic->clk);

	return 0;
}

static struct riic_irq_desc riic_irqs[] = {
	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
};

static int riic_i2c_probe(struct platform_device *pdev)
{
	struct riic_dev *riic;
	struct i2c_adapter *adap;
	struct resource *res;
	struct i2c_timings i2c_t;
	int i, ret;

	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
	if (!riic)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	riic->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(riic->base))
		return PTR_ERR(riic->base);

	riic->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(riic->clk)) {
		dev_err(&pdev->dev, "missing controller clock");
		return PTR_ERR(riic->clk);
	}

	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
		if (!res)
			return -ENODEV;

		ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
					0, riic_irqs[i].name, riic);
		if (ret) {
			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
			return ret;
		}
	}

	adap = &riic->adapter;
	i2c_set_adapdata(adap, riic);
	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
	adap->owner = THIS_MODULE;
	adap->algo = &riic_algo;
	adap->dev.parent = &pdev->dev;
	adap->dev.of_node = pdev->dev.of_node;

	init_completion(&riic->msg_done);

	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);

	ret = riic_init_hw(riic, &i2c_t);
	if (ret)
		return ret;


	ret = i2c_add_adapter(adap);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, riic);

	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
		 i2c_t.bus_freq_hz);
	return 0;
}

static int riic_i2c_remove(struct platform_device *pdev)
{
	struct riic_dev *riic = platform_get_drvdata(pdev);

	writeb(0, riic->base + RIIC_ICIER);
	i2c_del_adapter(&riic->adapter);

	return 0;
}

static const struct of_device_id riic_i2c_dt_ids[] = {
	{ .compatible = "renesas,riic-rz" },
	{ /* Sentinel */ },
};

static struct platform_driver riic_i2c_driver = {
	.probe		= riic_i2c_probe,
	.remove		= riic_i2c_remove,
	.driver		= {
		.name	= "i2c-riic",
		.of_match_table = riic_i2c_dt_ids,
	},
};

module_platform_driver(riic_i2c_driver);

MODULE_DESCRIPTION("Renesas RIIC adapter");
MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
Commit	Line	Data
310c18a4 WS	1	/*
	2	* Renesas RIIC driver
	3	*
	4	* Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
	5	* Copyright (C) 2013 Renesas Solutions Corp.
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*/
	11
	12	/*
	13	* This i2c core has a lot of interrupts, namely 8. We use their chaining as
	14	* some kind of state machine.
	15	*
	16	* 1) The main xfer routine kicks off a transmission by putting the start bit
	17	* (or repeated start) on the bus and enabling the transmit interrupt (TIE)
	18	* since we need to send the slave address + RW bit in every case.
	19	*
	20	* 2) TIE sends slave address + RW bit and selects how to continue.
	21	*
	22	* 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
	23	* are done, we switch over to the transmission done interrupt (TEIE) and mark
	24	* the message as completed (includes sending STOP) there.
	25	*
	26	* 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
	27	* needed to start clocking, then we keep receiving until we are done. Note
	28	* that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
	29	* writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
	30	* message to create the final NACK as sketched in the datasheet. This caused
	31	* some subtle races (when byte n was processed and byte n+1 was already
	32	* waiting), though, and I started with the safe approach.
	33	*
	34	* 4) If we got a NACK somewhere, we flag the error and stop the transmission
	35	* via NAKIE.
	36	*
	37	* Also check the comments in the interrupt routines for some gory details.
	38	*/
	39
	40	#include <linux/clk.h>
	41	#include <linux/completion.h>
	42	#include <linux/err.h>
	43	#include <linux/i2c.h>
	44	#include <linux/interrupt.h>
	45	#include <linux/io.h>
	46	#include <linux/module.h>
	47	#include <linux/of.h>
	48	#include <linux/platform_device.h>
	49
	50	#define RIIC_ICCR1 0x00
	51	#define RIIC_ICCR2 0x04
	52	#define RIIC_ICMR1 0x08
	53	#define RIIC_ICMR3 0x10
	54	#define RIIC_ICSER 0x18
	55	#define RIIC_ICIER 0x1c
	56	#define RIIC_ICSR2 0x24
	57	#define RIIC_ICBRL 0x34
	58	#define RIIC_ICBRH 0x38
	59	#define RIIC_ICDRT 0x3c
	60	#define RIIC_ICDRR 0x40
	61
	62	#define ICCR1_ICE 0x80
	63	#define ICCR1_IICRST 0x40
	64	#define ICCR1_SOWP 0x10
65
66	#define ICCR2_BBSY 0x80
67	#define ICCR2_SP 0x08
68	#define ICCR2_RS 0x04
69	#define ICCR2_ST 0x02
70
71	#define ICMR1_CKS_MASK 0x70
72	#define ICMR1_BCWP 0x08
73	#define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) \| ICMR1_BCWP)
74
75	#define ICMR3_RDRFS 0x20
76	#define ICMR3_ACKWP 0x10
77	#define ICMR3_ACKBT 0x08
78
79	#define ICIER_TIE 0x80
80	#define ICIER_TEIE 0x40
81	#define ICIER_RIE 0x20
82	#define ICIER_NAKIE 0x10
71ccea09	83	#define ICIER_SPIE 0x08
310c18a4 WS	84
	85	#define ICSR2_NACKF 0x10
	86
310c18a4	87	#define ICBR_RESERVED 0xe0 /* Should be 1 on writes */
310c18a4 WS	88
	89	#define RIIC_INIT_MSG -1
	90
	91	struct riic_dev {
	92	void __iomem *base;
	93	u8 *buf;
	94	struct i2c_msg *msg;
	95	int bytes_left;
	96	int err;
	97	int is_last;
	98	struct completion msg_done;
	99	struct i2c_adapter adapter;
	100	struct clk *clk;
	101	};
	102
	103	struct riic_irq_desc {
	104	int res_num;
	105	irq_handler_t isr;
	106	char *name;
	107	};
	108
	109	static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
	110	{
	111	writeb((readb(riic->base + reg) & ~clear) \| set, riic->base + reg);
	112	}
	113
	114	static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
	115	{
	116	struct riic_dev *riic = i2c_get_adapdata(adap);
	117	unsigned long time_left;
	118	int i, ret;
	119	u8 start_bit;
	120
	121	ret = clk_prepare_enable(riic->clk);
	122	if (ret)
	123	return ret;
	124
	125	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
	126	riic->err = -EBUSY;
	127	goto out;
	128	}
	129
	130	reinit_completion(&riic->msg_done);
	131	riic->err = 0;
	132
	133	writeb(0, riic->base + RIIC_ICSR2);
	134
	135	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
	136	riic->bytes_left = RIIC_INIT_MSG;
	137	riic->buf = msgs[i].buf;
	138	riic->msg = &msgs[i];
	139	riic->is_last = (i == num - 1);
	140
	141	writeb(ICIER_NAKIE \| ICIER_TIE, riic->base + RIIC_ICIER);
	142
	143	writeb(start_bit, riic->base + RIIC_ICCR2);
	144
	145	time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
	146	if (time_left == 0)
	147	riic->err = -ETIMEDOUT;
	148
	149	if (riic->err)
	150	break;
	151
152	start_bit = ICCR2_RS;
153	}
154
155	out:
156	clk_disable_unprepare(riic->clk);
157
158	return riic->err ?: num;
159	}
160
161	static irqreturn_t riic_tdre_isr(int irq, void *data)
162	{
163	struct riic_dev *riic = data;
164	u8 val;
165
166	if (!riic->bytes_left)
167	return IRQ_NONE;
168
169	if (riic->bytes_left == RIIC_INIT_MSG) {
170	val = !!(riic->msg->flags & I2C_M_RD);
171	if (val)
172	/* On read, switch over to receive interrupt */
173	riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
174	else
175	/* On write, initialize length */
176	riic->bytes_left = riic->msg->len;
177
178	val \|= (riic->msg->addr << 1);
179	} else {
180	val = *riic->buf;
181	riic->buf++;
182	riic->bytes_left--;
183	}
184
185	/*
186	* Switch to transmission ended interrupt when done. Do check here
187	* after bytes_left was initialized to support SMBUS_QUICK (new msg has
188	* 0 length then)
189	*/
190	if (riic->bytes_left == 0)
191	riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
192
193	/*
194	* This acks the TIE interrupt. We get another TIE immediately if our
195	* value could be moved to the shadow shift register right away. So
196	* this must be after updates to ICIER (where we want to disable TIE)!
197	*/
198	writeb(val, riic->base + RIIC_ICDRT);
199
200	return IRQ_HANDLED;
201	}
202
203	static irqreturn_t riic_tend_isr(int irq, void *data)
204	{
205	struct riic_dev *riic = data;
206
207	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
208	/* We got a NACKIE */
209	readb(riic->base + RIIC_ICDRR); /* dummy read */
f4d8e9e3	210	riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
310c18a4 WS	211	riic->err = -ENXIO;
	212	} else if (riic->bytes_left) {
	213	return IRQ_NONE;
	214	}
	215
71ccea09	216	if (riic->is_last \|\| riic->err) {
2501c1bb	217	riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
310c18a4	218	writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
2501c1bb CB	219	} else {
	220	/* Transfer is complete, but do not send STOP */
	221	riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
	222	complete(&riic->msg_done);
71ccea09	223	}
310c18a4 WS	224
	225	return IRQ_HANDLED;
	226	}
	227
	228	static irqreturn_t riic_rdrf_isr(int irq, void *data)
	229	{
	230	struct riic_dev *riic = data;
	231
	232	if (!riic->bytes_left)
	233	return IRQ_NONE;
	234
	235	if (riic->bytes_left == RIIC_INIT_MSG) {
	236	riic->bytes_left = riic->msg->len;
	237	readb(riic->base + RIIC_ICDRR); /* dummy read */
	238	return IRQ_HANDLED;
	239	}
	240
	241	if (riic->bytes_left == 1) {
	242	/* STOP must come before we set ACKBT! */
71ccea09 CB	243	if (riic->is_last) {
71ccea09 CB	244	riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
310c18a4	245	writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
71ccea09	246	}
310c18a4 WS	247
	248	riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
	249
310c18a4 WS	250	} else {
	251	riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
	252	}
	253
	254	/* Reading acks the RIE interrupt */
	255	*riic->buf = readb(riic->base + RIIC_ICDRR);
	256	riic->buf++;
	257	riic->bytes_left--;
	258
	259	return IRQ_HANDLED;
	260	}
	261
71ccea09 CB	262	static irqreturn_t riic_stop_isr(int irq, void *data)
	263	{
	264	struct riic_dev *riic = data;
	265
	266	/* read back registers to confirm writes have fully propagated */
	267	writeb(0, riic->base + RIIC_ICSR2);
	268	readb(riic->base + RIIC_ICSR2);
	269	writeb(0, riic->base + RIIC_ICIER);
	270	readb(riic->base + RIIC_ICIER);
	271
	272	complete(&riic->msg_done);
	273
	274	return IRQ_HANDLED;
	275	}
	276
310c18a4 WS	277	static u32 riic_func(struct i2c_adapter *adap)
	278	{
	279	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	280	}
	281
	282	static const struct i2c_algorithm riic_algo = {
	283	.master_xfer = riic_xfer,
	284	.functionality = riic_func,
	285	};
	286
d982d665	287	static int riic_init_hw(struct riic_dev riic, struct i2c_timings t)
310c18a4 WS	288	{
	289	int ret;
	290	unsigned long rate;
d982d665	291	int total_ticks, cks, brl, brh;
310c18a4 WS	292
	293	ret = clk_prepare_enable(riic->clk);
	294	if (ret)
	295	return ret;
	296
d982d665 CB	297	if (t->bus_freq_hz > 400000) {
	298	dev_err(&riic->adapter.dev,
	299	"unsupported bus speed (%dHz). 400000 max\n",
	300	t->bus_freq_hz);
	301	clk_disable_unprepare(riic->clk);
	302	return -EINVAL;
	303	}
	304
	305	rate = clk_get_rate(riic->clk);
	306
310c18a4	307	/*
d982d665 CB	308	* Assume the default register settings:
	309	* FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
	310	* FER.NFE = 1 (noise circuit enabled)
	311	* MR3.NF = 0 (1 cycle of noise filtered out)
	312	*
	313	* Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
	314	* Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
310c18a4	315	*/
d982d665 CB	316
	317	/*
	318	* Determine reference clock rate. We must be able to get the desired
	319	* frequency with only 62 clock ticks max (31 high, 31 low).
	320	* Aim for a duty of 60% LOW, 40% HIGH.
	321	*/
	322	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
	323
	324	for (cks = 0; cks < 7; cks++) {
	325	/*
	326	* 60% low time must be less than BRL + 2 + 1
	327	* BRL max register value is 0x1F.
	328	*/
	329	brl = ((total_ticks * 6) / 10);
	330	if (brl <= (0x1F + 3))
	331	break;
	332
	333	total_ticks /= 2;
	334	rate /= 2;
	335	}
	336
	337	if (brl > (0x1F + 3)) {
	338	dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
	339	(unsigned long)t->bus_freq_hz);
310c18a4 WS	340	clk_disable_unprepare(riic->clk);
	341	return -EINVAL;
	342	}
	343
d982d665 CB	344	brh = total_ticks - brl;
	345
	346	/* Remove automatic clock ticks for sync circuit and NF */
	347	if (cks == 0) {
	348	brl -= 4;
	349	brh -= 4;
	350	} else {
	351	brl -= 3;
	352	brh -= 3;
	353	}
	354
	355	/*
	356	* Remove clock ticks for rise and fall times. Convert ns to clock
	357	* ticks.
	358	*/
	359	brl -= t->scl_fall_ns / (1000000000 / rate);
	360	brh -= t->scl_rise_ns / (1000000000 / rate);
	361
	362	/* Adjust for min register values for when SCLE=1 and NFE=1 */
	363	if (brl < 1)
	364	brl = 1;
	365	if (brh < 1)
	366	brh = 1;
	367
	368	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
	369	rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
	370	t->scl_fall_ns / (1000000000 / rate),
	371	t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
	372
310c18a4 WS	373	/* Changing the order of accessing IICRST and ICE may break things! */
	374	writeb(ICCR1_IICRST \| ICCR1_SOWP, riic->base + RIIC_ICCR1);
	375	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
	376
d982d665 CB	377	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
	378	writeb(brh \| ICBR_RESERVED, riic->base + RIIC_ICBRH);
	379	writeb(brl \| ICBR_RESERVED, riic->base + RIIC_ICBRL);
310c18a4 WS	380
	381	writeb(0, riic->base + RIIC_ICSER);
	382	writeb(ICMR3_ACKWP \| ICMR3_RDRFS, riic->base + RIIC_ICMR3);
	383
	384	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
	385
	386	clk_disable_unprepare(riic->clk);
	387
	388	return 0;
	389	}
	390
	391	static struct riic_irq_desc riic_irqs[] = {
	392	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
	393	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
	394	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
71ccea09	395	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
310c18a4 WS	396	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
	397	};
	398
	399	static int riic_i2c_probe(struct platform_device *pdev)
	400	{
310c18a4 WS	401	struct riic_dev *riic;
	402	struct i2c_adapter *adap;
	403	struct resource *res;
d982d665	404	struct i2c_timings i2c_t;
310c18a4 WS	405	int i, ret;
	406
	407	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
	408	if (!riic)
	409	return -ENOMEM;
	410
	411	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	412	riic->base = devm_ioremap_resource(&pdev->dev, res);
	413	if (IS_ERR(riic->base))
	414	return PTR_ERR(riic->base);
	415
	416	riic->clk = devm_clk_get(&pdev->dev, NULL);
	417	if (IS_ERR(riic->clk)) {
	418	dev_err(&pdev->dev, "missing controller clock");
	419	return PTR_ERR(riic->clk);
	420	}
	421
	422	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
	423	res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
	424	if (!res)
	425	return -ENODEV;
	426
	427	ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
	428	0, riic_irqs[i].name, riic);
	429	if (ret) {
	430	dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
	431	return ret;
	432	}
	433	}
	434
	435	adap = &riic->adapter;
	436	i2c_set_adapdata(adap, riic);
	437	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
	438	adap->owner = THIS_MODULE;
	439	adap->algo = &riic_algo;
	440	adap->dev.parent = &pdev->dev;
	441	adap->dev.of_node = pdev->dev.of_node;
	442
	443	init_completion(&riic->msg_done);
	444
d982d665 CB	445	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
	446
	447	ret = riic_init_hw(riic, &i2c_t);
310c18a4 WS	448	if (ret)
	449	return ret;
	450
	451
	452	ret = i2c_add_adapter(adap);
ea734404	453	if (ret)
310c18a4	454	return ret;
310c18a4 WS	455
	456	platform_set_drvdata(pdev, riic);
	457
d982d665 CB	458	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
d982d665 CB	459	i2c_t.bus_freq_hz);
310c18a4 WS	460	return 0;
	461	}
	462
	463	static int riic_i2c_remove(struct platform_device *pdev)
	464	{
	465	struct riic_dev *riic = platform_get_drvdata(pdev);
	466
	467	writeb(0, riic->base + RIIC_ICIER);
	468	i2c_del_adapter(&riic->adapter);
	469
	470	return 0;
	471	}
	472
eae45e5d	473	static const struct of_device_id riic_i2c_dt_ids[] = {
310c18a4 WS	474	{ .compatible = "renesas,riic-rz" },
	475	{ /* Sentinel */ },
	476	};
	477
	478	static struct platform_driver riic_i2c_driver = {
	479	.probe = riic_i2c_probe,
	480	.remove = riic_i2c_remove,
	481	.driver = {
	482	.name = "i2c-riic",
310c18a4 WS	483	.of_match_table = riic_i2c_dt_ids,
	484	},
	485	};
	486
	487	module_platform_driver(riic_i2c_driver);
	488
	489	MODULE_DESCRIPTION("Renesas RIIC adapter");
	490	MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
	491	MODULE_LICENSE("GPL v2");
	492	MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);