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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
3 | * Copyright (C) 2004,2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
27 | #include <linux/i2c-id.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/interrupt.h> | |
1da177e4 LT |
31 | #include <linux/delay.h> |
32 | #include <linux/errno.h> | |
33 | #include <linux/err.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
1da177e4 LT |
36 | |
37 | #include <asm/hardware.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
1da177e4 | 41 | #include <asm/arch/regs-gpio.h> |
b5d0b4ba BD |
42 | #include <asm/plat-s3c/regs-iic.h> |
43 | #include <asm/plat-s3c/iic.h> | |
1da177e4 LT |
44 | |
45 | /* i2c controller state */ | |
46 | ||
47 | enum s3c24xx_i2c_state { | |
48 | STATE_IDLE, | |
49 | STATE_START, | |
50 | STATE_READ, | |
51 | STATE_WRITE, | |
52 | STATE_STOP | |
53 | }; | |
54 | ||
55 | struct s3c24xx_i2c { | |
56 | spinlock_t lock; | |
57 | wait_queue_head_t wait; | |
58 | ||
59 | struct i2c_msg *msg; | |
60 | unsigned int msg_num; | |
61 | unsigned int msg_idx; | |
62 | unsigned int msg_ptr; | |
63 | ||
e00a8cdf BD |
64 | unsigned int tx_setup; |
65 | ||
1da177e4 LT |
66 | enum s3c24xx_i2c_state state; |
67 | ||
68 | void __iomem *regs; | |
69 | struct clk *clk; | |
70 | struct device *dev; | |
71 | struct resource *irq; | |
72 | struct resource *ioarea; | |
73 | struct i2c_adapter adap; | |
74 | }; | |
75 | ||
76 | /* default platform data to use if not supplied in the platform_device | |
77 | */ | |
78 | ||
79 | static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = { | |
80 | .flags = 0, | |
81 | .slave_addr = 0x10, | |
82 | .bus_freq = 100*1000, | |
83 | .max_freq = 400*1000, | |
84 | .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, | |
85 | }; | |
86 | ||
87 | /* s3c24xx_i2c_is2440() | |
88 | * | |
89 | * return true is this is an s3c2440 | |
90 | */ | |
91 | ||
92 | static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) | |
93 | { | |
94 | struct platform_device *pdev = to_platform_device(i2c->dev); | |
95 | ||
96 | return !strcmp(pdev->name, "s3c2440-i2c"); | |
97 | } | |
98 | ||
99 | ||
100 | /* s3c24xx_i2c_get_platformdata | |
101 | * | |
102 | * get the platform data associated with the given device, or return | |
103 | * the default if there is none | |
104 | */ | |
105 | ||
106 | static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev) | |
107 | { | |
108 | if (dev->platform_data != NULL) | |
109 | return (struct s3c2410_platform_i2c *)dev->platform_data; | |
110 | ||
111 | return &s3c24xx_i2c_default_platform; | |
112 | } | |
113 | ||
114 | /* s3c24xx_i2c_master_complete | |
115 | * | |
116 | * complete the message and wake up the caller, using the given return code, | |
117 | * or zero to mean ok. | |
118 | */ | |
119 | ||
120 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
121 | { | |
122 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
123 | ||
124 | i2c->msg_ptr = 0; | |
125 | i2c->msg = NULL; | |
126 | i2c->msg_idx ++; | |
127 | i2c->msg_num = 0; | |
128 | if (ret) | |
129 | i2c->msg_idx = ret; | |
130 | ||
131 | wake_up(&i2c->wait); | |
132 | } | |
133 | ||
134 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
135 | { | |
136 | unsigned long tmp; | |
137 | ||
138 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
139 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
140 | ||
141 | } | |
142 | ||
143 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
144 | { | |
145 | unsigned long tmp; | |
146 | ||
147 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
148 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
149 | ||
150 | } | |
151 | ||
152 | /* irq enable/disable functions */ | |
153 | ||
154 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
155 | { | |
156 | unsigned long tmp; | |
157 | ||
158 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
159 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
160 | } | |
161 | ||
162 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
163 | { | |
164 | unsigned long tmp; | |
165 | ||
166 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
167 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
168 | } | |
169 | ||
170 | ||
171 | /* s3c24xx_i2c_message_start | |
172 | * | |
173 | * put the start of a message onto the bus | |
174 | */ | |
175 | ||
176 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, | |
177 | struct i2c_msg *msg) | |
178 | { | |
179 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
180 | unsigned long stat; | |
181 | unsigned long iiccon; | |
182 | ||
183 | stat = 0; | |
184 | stat |= S3C2410_IICSTAT_TXRXEN; | |
185 | ||
186 | if (msg->flags & I2C_M_RD) { | |
187 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
188 | addr |= 1; | |
189 | } else | |
190 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
191 | ||
192 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
193 | addr ^= 1; | |
194 | ||
195 | // todo - check for wether ack wanted or not | |
196 | s3c24xx_i2c_enable_ack(i2c); | |
197 | ||
198 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
199 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
200 | ||
201 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); | |
202 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
203 | ||
e00a8cdf BD |
204 | /* delay here to ensure the data byte has gotten onto the bus |
205 | * before the transaction is started */ | |
206 | ||
207 | ndelay(i2c->tx_setup); | |
208 | ||
1da177e4 LT |
209 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
210 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
211 | ||
212 | stat |= S3C2410_IICSTAT_START; | |
213 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
214 | } | |
215 | ||
216 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
217 | { | |
218 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
219 | ||
220 | dev_dbg(i2c->dev, "STOP\n"); | |
221 | ||
222 | /* stop the transfer */ | |
223 | iicstat &= ~ S3C2410_IICSTAT_START; | |
224 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); | |
225 | ||
226 | i2c->state = STATE_STOP; | |
227 | ||
228 | s3c24xx_i2c_master_complete(i2c, ret); | |
229 | s3c24xx_i2c_disable_irq(i2c); | |
230 | } | |
231 | ||
232 | /* helper functions to determine the current state in the set of | |
233 | * messages we are sending */ | |
234 | ||
235 | /* is_lastmsg() | |
236 | * | |
237 | * returns TRUE if the current message is the last in the set | |
238 | */ | |
239 | ||
240 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
241 | { | |
242 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
243 | } | |
244 | ||
245 | /* is_msglast | |
246 | * | |
247 | * returns TRUE if we this is the last byte in the current message | |
248 | */ | |
249 | ||
250 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
251 | { | |
252 | return i2c->msg_ptr == i2c->msg->len-1; | |
253 | } | |
254 | ||
255 | /* is_msgend | |
256 | * | |
257 | * returns TRUE if we reached the end of the current message | |
258 | */ | |
259 | ||
260 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
261 | { | |
262 | return i2c->msg_ptr >= i2c->msg->len; | |
263 | } | |
264 | ||
265 | /* i2s_s3c_irq_nextbyte | |
266 | * | |
267 | * process an interrupt and work out what to do | |
268 | */ | |
269 | ||
270 | static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |
271 | { | |
272 | unsigned long tmp; | |
273 | unsigned char byte; | |
274 | int ret = 0; | |
275 | ||
276 | switch (i2c->state) { | |
277 | ||
278 | case STATE_IDLE: | |
08882d20 | 279 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 LT |
280 | goto out; |
281 | break; | |
282 | ||
283 | case STATE_STOP: | |
08882d20 | 284 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
1da177e4 LT |
285 | s3c24xx_i2c_disable_irq(i2c); |
286 | goto out_ack; | |
287 | ||
288 | case STATE_START: | |
289 | /* last thing we did was send a start condition on the | |
290 | * bus, or started a new i2c message | |
291 | */ | |
292 | ||
63f5c289 | 293 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
294 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
295 | /* ack was not received... */ | |
296 | ||
297 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 298 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
299 | goto out_ack; |
300 | } | |
301 | ||
302 | if (i2c->msg->flags & I2C_M_RD) | |
303 | i2c->state = STATE_READ; | |
304 | else | |
305 | i2c->state = STATE_WRITE; | |
306 | ||
307 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 308 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
309 | |
310 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
311 | s3c24xx_i2c_stop(i2c, 0); | |
312 | goto out_ack; | |
313 | } | |
314 | ||
315 | if (i2c->state == STATE_READ) | |
316 | goto prepare_read; | |
317 | ||
318 | /* fall through to the write state, as we will need to | |
319 | * send a byte as well */ | |
320 | ||
321 | case STATE_WRITE: | |
322 | /* we are writing data to the device... check for the | |
323 | * end of the message, and if so, work out what to do | |
324 | */ | |
325 | ||
2709781b BD |
326 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
327 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
328 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
329 | ||
330 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
331 | goto out_ack; | |
332 | } | |
333 | } | |
334 | ||
1da177e4 | 335 | retry_write: |
2709781b | 336 | |
1da177e4 LT |
337 | if (!is_msgend(i2c)) { |
338 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
339 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
340 | |
341 | /* delay after writing the byte to allow the | |
342 | * data setup time on the bus, as writing the | |
343 | * data to the register causes the first bit | |
344 | * to appear on SDA, and SCL will change as | |
345 | * soon as the interrupt is acknowledged */ | |
346 | ||
347 | ndelay(i2c->tx_setup); | |
348 | ||
1da177e4 LT |
349 | } else if (!is_lastmsg(i2c)) { |
350 | /* we need to go to the next i2c message */ | |
351 | ||
352 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
353 | ||
354 | i2c->msg_ptr = 0; | |
355 | i2c->msg_idx ++; | |
356 | i2c->msg++; | |
357 | ||
358 | /* check to see if we need to do another message */ | |
359 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
360 | ||
361 | if (i2c->msg->flags & I2C_M_RD) { | |
362 | /* cannot do this, the controller | |
363 | * forces us to send a new START | |
364 | * when we change direction */ | |
365 | ||
366 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
367 | } | |
368 | ||
369 | goto retry_write; | |
370 | } else { | |
371 | ||
372 | /* send the new start */ | |
373 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
374 | i2c->state = STATE_START; | |
375 | } | |
376 | ||
377 | } else { | |
378 | /* send stop */ | |
379 | ||
380 | s3c24xx_i2c_stop(i2c, 0); | |
381 | } | |
382 | break; | |
383 | ||
384 | case STATE_READ: | |
385 | /* we have a byte of data in the data register, do | |
386 | * something with it, and then work out wether we are | |
387 | * going to do any more read/write | |
388 | */ | |
389 | ||
1da177e4 LT |
390 | byte = readb(i2c->regs + S3C2410_IICDS); |
391 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
392 | ||
393 | prepare_read: | |
394 | if (is_msglast(i2c)) { | |
395 | /* last byte of buffer */ | |
396 | ||
397 | if (is_lastmsg(i2c)) | |
398 | s3c24xx_i2c_disable_ack(i2c); | |
399 | ||
400 | } else if (is_msgend(i2c)) { | |
401 | /* ok, we've read the entire buffer, see if there | |
402 | * is anything else we need to do */ | |
403 | ||
404 | if (is_lastmsg(i2c)) { | |
405 | /* last message, send stop and complete */ | |
406 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
407 | ||
408 | s3c24xx_i2c_stop(i2c, 0); | |
409 | } else { | |
410 | /* go to the next transfer */ | |
411 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
412 | ||
413 | i2c->msg_ptr = 0; | |
414 | i2c->msg_idx++; | |
415 | i2c->msg++; | |
416 | } | |
417 | } | |
418 | ||
419 | break; | |
420 | } | |
421 | ||
422 | /* acknowlegde the IRQ and get back on with the work */ | |
423 | ||
424 | out_ack: | |
425 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
426 | tmp &= ~S3C2410_IICCON_IRQPEND; | |
427 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
428 | out: | |
429 | return ret; | |
430 | } | |
431 | ||
432 | /* s3c24xx_i2c_irq | |
433 | * | |
434 | * top level IRQ servicing routine | |
435 | */ | |
436 | ||
7d12e780 | 437 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
438 | { |
439 | struct s3c24xx_i2c *i2c = dev_id; | |
440 | unsigned long status; | |
441 | unsigned long tmp; | |
442 | ||
443 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
444 | ||
445 | if (status & S3C2410_IICSTAT_ARBITR) { | |
446 | // deal with arbitration loss | |
447 | dev_err(i2c->dev, "deal with arbitration loss\n"); | |
448 | } | |
449 | ||
450 | if (i2c->state == STATE_IDLE) { | |
451 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
452 | ||
453 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
454 | tmp &= ~S3C2410_IICCON_IRQPEND; | |
455 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
456 | goto out; | |
457 | } | |
458 | ||
459 | /* pretty much this leaves us with the fact that we've | |
460 | * transmitted or received whatever byte we last sent */ | |
461 | ||
462 | i2s_s3c_irq_nextbyte(i2c, status); | |
463 | ||
464 | out: | |
465 | return IRQ_HANDLED; | |
466 | } | |
467 | ||
468 | ||
469 | /* s3c24xx_i2c_set_master | |
470 | * | |
471 | * get the i2c bus for a master transaction | |
472 | */ | |
473 | ||
474 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
475 | { | |
476 | unsigned long iicstat; | |
477 | int timeout = 400; | |
478 | ||
479 | while (timeout-- > 0) { | |
480 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
481 | ||
482 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) | |
483 | return 0; | |
484 | ||
485 | msleep(1); | |
486 | } | |
487 | ||
488 | dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n", | |
489 | __raw_readl(S3C2410_GPEDAT)); | |
490 | ||
491 | return -ETIMEDOUT; | |
492 | } | |
493 | ||
494 | /* s3c24xx_i2c_doxfer | |
495 | * | |
496 | * this starts an i2c transfer | |
497 | */ | |
498 | ||
499 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num) | |
500 | { | |
501 | unsigned long timeout; | |
502 | int ret; | |
503 | ||
504 | ret = s3c24xx_i2c_set_master(i2c); | |
505 | if (ret != 0) { | |
506 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
507 | ret = -EAGAIN; | |
508 | goto out; | |
509 | } | |
510 | ||
511 | spin_lock_irq(&i2c->lock); | |
512 | ||
513 | i2c->msg = msgs; | |
514 | i2c->msg_num = num; | |
515 | i2c->msg_ptr = 0; | |
516 | i2c->msg_idx = 0; | |
517 | i2c->state = STATE_START; | |
518 | ||
519 | s3c24xx_i2c_enable_irq(i2c); | |
520 | s3c24xx_i2c_message_start(i2c, msgs); | |
521 | spin_unlock_irq(&i2c->lock); | |
522 | ||
523 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
524 | ||
525 | ret = i2c->msg_idx; | |
526 | ||
527 | /* having these next two as dev_err() makes life very | |
528 | * noisy when doing an i2cdetect */ | |
529 | ||
530 | if (timeout == 0) | |
531 | dev_dbg(i2c->dev, "timeout\n"); | |
532 | else if (ret != num) | |
533 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
534 | ||
535 | /* ensure the stop has been through the bus */ | |
536 | ||
537 | msleep(1); | |
538 | ||
539 | out: | |
540 | return ret; | |
541 | } | |
542 | ||
543 | /* s3c24xx_i2c_xfer | |
544 | * | |
545 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 546 | * transferring across the i2c bus. |
1da177e4 LT |
547 | */ |
548 | ||
549 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
550 | struct i2c_msg *msgs, int num) | |
551 | { | |
552 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
553 | int retry; | |
554 | int ret; | |
555 | ||
556 | for (retry = 0; retry < adap->retries; retry++) { | |
557 | ||
558 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
559 | ||
560 | if (ret != -EAGAIN) | |
561 | return ret; | |
562 | ||
563 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
564 | ||
565 | udelay(100); | |
566 | } | |
567 | ||
568 | return -EREMOTEIO; | |
569 | } | |
570 | ||
571 | /* declare our i2c functionality */ | |
572 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
573 | { | |
574 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
575 | } | |
576 | ||
577 | /* i2c bus registration info */ | |
578 | ||
8f9082c5 | 579 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
580 | .master_xfer = s3c24xx_i2c_xfer, |
581 | .functionality = s3c24xx_i2c_func, | |
582 | }; | |
583 | ||
584 | static struct s3c24xx_i2c s3c24xx_i2c = { | |
e00a8cdf BD |
585 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock), |
586 | .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait), | |
587 | .tx_setup = 50, | |
588 | .adap = { | |
1da177e4 LT |
589 | .name = "s3c2410-i2c", |
590 | .owner = THIS_MODULE, | |
591 | .algo = &s3c24xx_i2c_algorithm, | |
592 | .retries = 2, | |
3401b2ff | 593 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
1da177e4 LT |
594 | }, |
595 | }; | |
596 | ||
597 | /* s3c24xx_i2c_calcdivisor | |
598 | * | |
599 | * return the divisor settings for a given frequency | |
600 | */ | |
601 | ||
602 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
603 | unsigned int *div1, unsigned int *divs) | |
604 | { | |
605 | unsigned int calc_divs = clkin / wanted; | |
606 | unsigned int calc_div1; | |
607 | ||
608 | if (calc_divs > (16*16)) | |
609 | calc_div1 = 512; | |
610 | else | |
611 | calc_div1 = 16; | |
612 | ||
613 | calc_divs += calc_div1-1; | |
614 | calc_divs /= calc_div1; | |
615 | ||
616 | if (calc_divs == 0) | |
617 | calc_divs = 1; | |
618 | if (calc_divs > 17) | |
619 | calc_divs = 17; | |
620 | ||
621 | *divs = calc_divs; | |
622 | *div1 = calc_div1; | |
623 | ||
624 | return clkin / (calc_divs * calc_div1); | |
625 | } | |
626 | ||
627 | /* freq_acceptable | |
628 | * | |
629 | * test wether a frequency is within the acceptable range of error | |
630 | */ | |
631 | ||
632 | static inline int freq_acceptable(unsigned int freq, unsigned int wanted) | |
633 | { | |
634 | int diff = freq - wanted; | |
635 | ||
636 | return (diff >= -2 && diff <= 2); | |
637 | } | |
638 | ||
639 | /* s3c24xx_i2c_getdivisor | |
640 | * | |
641 | * work out a divisor for the user requested frequency setting, | |
642 | * either by the requested frequency, or scanning the acceptable | |
643 | * range of frequencies until something is found | |
644 | */ | |
645 | ||
646 | static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c, | |
647 | struct s3c2410_platform_i2c *pdata, | |
648 | unsigned long *iicon, | |
649 | unsigned int *got) | |
650 | { | |
651 | unsigned long clkin = clk_get_rate(i2c->clk); | |
652 | ||
653 | unsigned int divs, div1; | |
654 | int freq; | |
655 | int start, end; | |
656 | ||
657 | clkin /= 1000; /* clkin now in KHz */ | |
658 | ||
659 | dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n", | |
660 | pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq); | |
661 | ||
662 | if (pdata->bus_freq != 0) { | |
663 | freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000, | |
664 | &div1, &divs); | |
665 | if (freq_acceptable(freq, pdata->bus_freq/1000)) | |
666 | goto found; | |
667 | } | |
668 | ||
669 | /* ok, we may have to search for something suitable... */ | |
670 | ||
671 | start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq; | |
672 | end = pdata->min_freq; | |
673 | ||
674 | start /= 1000; | |
675 | end /= 1000; | |
676 | ||
677 | /* search loop... */ | |
678 | ||
679 | for (; start > end; start--) { | |
680 | freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs); | |
681 | if (freq_acceptable(freq, start)) | |
682 | goto found; | |
683 | } | |
684 | ||
685 | /* cannot find frequency spec */ | |
686 | ||
687 | return -EINVAL; | |
688 | ||
689 | found: | |
690 | *got = freq; | |
691 | *iicon |= (divs-1); | |
692 | *iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0; | |
693 | return 0; | |
694 | } | |
695 | ||
696 | /* s3c24xx_i2c_init | |
697 | * | |
698 | * initialise the controller, set the IO lines and frequency | |
699 | */ | |
700 | ||
701 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
702 | { | |
703 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
704 | struct s3c2410_platform_i2c *pdata; | |
705 | unsigned int freq; | |
706 | ||
707 | /* get the plafrom data */ | |
708 | ||
709 | pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent); | |
710 | ||
711 | /* inititalise the gpio */ | |
712 | ||
713 | s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); | |
714 | s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); | |
715 | ||
716 | /* write slave address */ | |
717 | ||
718 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); | |
719 | ||
720 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
721 | ||
722 | /* we need to work out the divisors for the clock... */ | |
723 | ||
724 | if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) { | |
725 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); | |
726 | return -EINVAL; | |
727 | } | |
728 | ||
729 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
730 | ||
731 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
732 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
733 | ||
734 | writel(iicon, i2c->regs + S3C2410_IICCON); | |
735 | ||
736 | /* check for s3c2440 i2c controller */ | |
737 | ||
738 | if (s3c24xx_i2c_is2440(i2c)) { | |
739 | dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay); | |
740 | ||
741 | writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC); | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
1da177e4 LT |
747 | /* s3c24xx_i2c_probe |
748 | * | |
749 | * called by the bus driver when a suitable device is found | |
750 | */ | |
751 | ||
3ae5eaec | 752 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 753 | { |
1da177e4 LT |
754 | struct s3c24xx_i2c *i2c = &s3c24xx_i2c; |
755 | struct resource *res; | |
756 | int ret; | |
757 | ||
758 | /* find the clock and enable it */ | |
759 | ||
3ae5eaec RK |
760 | i2c->dev = &pdev->dev; |
761 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 762 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 763 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 764 | ret = -ENOENT; |
5b68790c | 765 | goto err_noclk; |
1da177e4 LT |
766 | } |
767 | ||
3ae5eaec | 768 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 769 | |
1da177e4 LT |
770 | clk_enable(i2c->clk); |
771 | ||
772 | /* map the registers */ | |
773 | ||
774 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
775 | if (res == NULL) { | |
3ae5eaec | 776 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 777 | ret = -ENOENT; |
5b68790c | 778 | goto err_clk; |
1da177e4 LT |
779 | } |
780 | ||
781 | i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1, | |
782 | pdev->name); | |
783 | ||
784 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 785 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 786 | ret = -ENXIO; |
5b68790c | 787 | goto err_clk; |
1da177e4 LT |
788 | } |
789 | ||
790 | i2c->regs = ioremap(res->start, (res->end-res->start)+1); | |
791 | ||
792 | if (i2c->regs == NULL) { | |
3ae5eaec | 793 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 794 | ret = -ENXIO; |
5b68790c | 795 | goto err_ioarea; |
1da177e4 LT |
796 | } |
797 | ||
3ae5eaec | 798 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res); |
1da177e4 LT |
799 | |
800 | /* setup info block for the i2c core */ | |
801 | ||
802 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 803 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
804 | |
805 | /* initialise the i2c controller */ | |
806 | ||
807 | ret = s3c24xx_i2c_init(i2c); | |
808 | if (ret != 0) | |
5b68790c | 809 | goto err_iomap; |
1da177e4 LT |
810 | |
811 | /* find the IRQ for this unit (note, this relies on the init call to | |
812 | * ensure no current IRQs pending | |
813 | */ | |
814 | ||
815 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
816 | if (res == NULL) { | |
3ae5eaec | 817 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
1da177e4 | 818 | ret = -ENOENT; |
5b68790c | 819 | goto err_iomap; |
1da177e4 LT |
820 | } |
821 | ||
dace1453 | 822 | ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED, |
1da177e4 LT |
823 | pdev->name, i2c); |
824 | ||
825 | if (ret != 0) { | |
3ae5eaec | 826 | dev_err(&pdev->dev, "cannot claim IRQ\n"); |
5b68790c | 827 | goto err_iomap; |
1da177e4 LT |
828 | } |
829 | ||
830 | i2c->irq = res; | |
831 | ||
a1ba1583 AP |
832 | dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res, |
833 | (unsigned long)res->start); | |
1da177e4 LT |
834 | |
835 | ret = i2c_add_adapter(&i2c->adap); | |
836 | if (ret < 0) { | |
3ae5eaec | 837 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
5b68790c | 838 | goto err_irq; |
1da177e4 LT |
839 | } |
840 | ||
3ae5eaec | 841 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 842 | |
3ae5eaec | 843 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id); |
5b68790c | 844 | return 0; |
1da177e4 | 845 | |
5b68790c BD |
846 | err_irq: |
847 | free_irq(i2c->irq->start, i2c); | |
848 | ||
849 | err_iomap: | |
850 | iounmap(i2c->regs); | |
851 | ||
852 | err_ioarea: | |
853 | release_resource(i2c->ioarea); | |
854 | kfree(i2c->ioarea); | |
855 | ||
856 | err_clk: | |
857 | clk_disable(i2c->clk); | |
858 | clk_put(i2c->clk); | |
1da177e4 | 859 | |
5b68790c | 860 | err_noclk: |
1da177e4 LT |
861 | return ret; |
862 | } | |
863 | ||
864 | /* s3c24xx_i2c_remove | |
865 | * | |
866 | * called when device is removed from the bus | |
867 | */ | |
868 | ||
3ae5eaec | 869 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 870 | { |
3ae5eaec | 871 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c BD |
872 | |
873 | i2c_del_adapter(&i2c->adap); | |
874 | free_irq(i2c->irq->start, i2c); | |
875 | ||
876 | clk_disable(i2c->clk); | |
877 | clk_put(i2c->clk); | |
878 | ||
879 | iounmap(i2c->regs); | |
880 | ||
881 | release_resource(i2c->ioarea); | |
882 | kfree(i2c->ioarea); | |
1da177e4 LT |
883 | |
884 | return 0; | |
885 | } | |
886 | ||
887 | #ifdef CONFIG_PM | |
3ae5eaec | 888 | static int s3c24xx_i2c_resume(struct platform_device *dev) |
1da177e4 | 889 | { |
3ae5eaec | 890 | struct s3c24xx_i2c *i2c = platform_get_drvdata(dev); |
9480e307 RK |
891 | |
892 | if (i2c != NULL) | |
1da177e4 | 893 | s3c24xx_i2c_init(i2c); |
1da177e4 LT |
894 | |
895 | return 0; | |
896 | } | |
897 | ||
898 | #else | |
899 | #define s3c24xx_i2c_resume NULL | |
900 | #endif | |
901 | ||
902 | /* device driver for platform bus bits */ | |
903 | ||
3ae5eaec | 904 | static struct platform_driver s3c2410_i2c_driver = { |
1da177e4 LT |
905 | .probe = s3c24xx_i2c_probe, |
906 | .remove = s3c24xx_i2c_remove, | |
907 | .resume = s3c24xx_i2c_resume, | |
3ae5eaec RK |
908 | .driver = { |
909 | .owner = THIS_MODULE, | |
910 | .name = "s3c2410-i2c", | |
911 | }, | |
1da177e4 LT |
912 | }; |
913 | ||
3ae5eaec | 914 | static struct platform_driver s3c2440_i2c_driver = { |
1da177e4 LT |
915 | .probe = s3c24xx_i2c_probe, |
916 | .remove = s3c24xx_i2c_remove, | |
917 | .resume = s3c24xx_i2c_resume, | |
3ae5eaec RK |
918 | .driver = { |
919 | .owner = THIS_MODULE, | |
920 | .name = "s3c2440-i2c", | |
921 | }, | |
1da177e4 LT |
922 | }; |
923 | ||
924 | static int __init i2c_adap_s3c_init(void) | |
925 | { | |
926 | int ret; | |
927 | ||
3ae5eaec | 928 | ret = platform_driver_register(&s3c2410_i2c_driver); |
e32e28ed | 929 | if (ret == 0) { |
3ae5eaec | 930 | ret = platform_driver_register(&s3c2440_i2c_driver); |
e32e28ed | 931 | if (ret) |
3ae5eaec | 932 | platform_driver_unregister(&s3c2410_i2c_driver); |
e32e28ed | 933 | } |
1da177e4 LT |
934 | |
935 | return ret; | |
936 | } | |
937 | ||
938 | static void __exit i2c_adap_s3c_exit(void) | |
939 | { | |
3ae5eaec RK |
940 | platform_driver_unregister(&s3c2410_i2c_driver); |
941 | platform_driver_unregister(&s3c2440_i2c_driver); | |
1da177e4 LT |
942 | } |
943 | ||
944 | module_init(i2c_adap_s3c_init); | |
945 | module_exit(i2c_adap_s3c_exit); | |
946 | ||
947 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
948 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
949 | MODULE_LICENSE("GPL"); | |
add8eda7 | 950 | MODULE_ALIAS("platform:s3c2410-i2c"); |
d150a4bb | 951 | MODULE_ALIAS("platform:s3c2440-i2c"); |