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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
1da177e4 LT |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | ||
22 | #include <linux/i2c.h> | |
1da177e4 LT |
23 | #include <linux/init.h> |
24 | #include <linux/time.h> | |
25 | #include <linux/interrupt.h> | |
1da177e4 LT |
26 | #include <linux/delay.h> |
27 | #include <linux/errno.h> | |
28 | #include <linux/err.h> | |
d052d1be | 29 | #include <linux/platform_device.h> |
c62c3ca5 | 30 | #include <linux/pm_runtime.h> |
f8ce2547 | 31 | #include <linux/clk.h> |
61c7cff8 | 32 | #include <linux/cpufreq.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
21782180 | 34 | #include <linux/io.h> |
4edd65e6 | 35 | #include <linux/of.h> |
5a5f5080 | 36 | #include <linux/of_gpio.h> |
2693ac69 | 37 | #include <linux/pinctrl/consumer.h> |
a7750c3e PD |
38 | #include <linux/mfd/syscon.h> |
39 | #include <linux/regmap.h> | |
1da177e4 | 40 | |
1da177e4 | 41 | #include <asm/irq.h> |
1da177e4 | 42 | |
436d42c6 | 43 | #include <linux/platform_data/i2c-s3c2410.h> |
1da177e4 | 44 | |
e636602a HS |
45 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ |
46 | ||
7a6674da HS |
47 | #define S3C2410_IICCON 0x00 |
48 | #define S3C2410_IICSTAT 0x04 | |
49 | #define S3C2410_IICADD 0x08 | |
50 | #define S3C2410_IICDS 0x0C | |
51 | #define S3C2440_IICLC 0x10 | |
e636602a | 52 | |
7a6674da HS |
53 | #define S3C2410_IICCON_ACKEN (1 << 7) |
54 | #define S3C2410_IICCON_TXDIV_16 (0 << 6) | |
55 | #define S3C2410_IICCON_TXDIV_512 (1 << 6) | |
56 | #define S3C2410_IICCON_IRQEN (1 << 5) | |
57 | #define S3C2410_IICCON_IRQPEND (1 << 4) | |
58 | #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) | |
e636602a HS |
59 | #define S3C2410_IICCON_SCALEMASK (0xf) |
60 | ||
7a6674da HS |
61 | #define S3C2410_IICSTAT_MASTER_RX (2 << 6) |
62 | #define S3C2410_IICSTAT_MASTER_TX (3 << 6) | |
63 | #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) | |
64 | #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) | |
65 | #define S3C2410_IICSTAT_MODEMASK (3 << 6) | |
e636602a | 66 | |
7a6674da HS |
67 | #define S3C2410_IICSTAT_START (1 << 5) |
68 | #define S3C2410_IICSTAT_BUSBUSY (1 << 5) | |
69 | #define S3C2410_IICSTAT_TXRXEN (1 << 4) | |
70 | #define S3C2410_IICSTAT_ARBITR (1 << 3) | |
71 | #define S3C2410_IICSTAT_ASSLAVE (1 << 2) | |
72 | #define S3C2410_IICSTAT_ADDR0 (1 << 1) | |
73 | #define S3C2410_IICSTAT_LASTBIT (1 << 0) | |
e636602a HS |
74 | |
75 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) | |
76 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) | |
77 | #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) | |
78 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) | |
79 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) | |
80 | ||
7a6674da | 81 | #define S3C2410_IICLC_FILTER_ON (1 << 2) |
e636602a | 82 | |
27452498 KL |
83 | /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ |
84 | #define QUIRK_S3C2440 (1 << 0) | |
ec39ef83 KL |
85 | #define QUIRK_HDMIPHY (1 << 1) |
86 | #define QUIRK_NO_GPIO (1 << 2) | |
117053f7 | 87 | #define QUIRK_POLL (1 << 3) |
1da177e4 | 88 | |
fe724bf9 DK |
89 | /* Max time to wait for bus to become idle after a xfer (in us) */ |
90 | #define S3C2410_IDLE_TIMEOUT 5000 | |
91 | ||
a7750c3e PD |
92 | /* Exynos5 Sysreg offset */ |
93 | #define EXYNOS5_SYS_I2C_CFG 0x0234 | |
94 | ||
27452498 | 95 | /* i2c controller state */ |
1da177e4 LT |
96 | enum s3c24xx_i2c_state { |
97 | STATE_IDLE, | |
98 | STATE_START, | |
99 | STATE_READ, | |
100 | STATE_WRITE, | |
101 | STATE_STOP | |
102 | }; | |
103 | ||
104 | struct s3c24xx_i2c { | |
1da177e4 | 105 | wait_queue_head_t wait; |
5f1b1155 | 106 | kernel_ulong_t quirks; |
be44f01e | 107 | unsigned int suspended:1; |
1da177e4 LT |
108 | |
109 | struct i2c_msg *msg; | |
110 | unsigned int msg_num; | |
111 | unsigned int msg_idx; | |
112 | unsigned int msg_ptr; | |
113 | ||
e00a8cdf | 114 | unsigned int tx_setup; |
e0d1ec97 | 115 | unsigned int irq; |
e00a8cdf | 116 | |
1da177e4 | 117 | enum s3c24xx_i2c_state state; |
61c7cff8 | 118 | unsigned long clkrate; |
1da177e4 LT |
119 | |
120 | void __iomem *regs; | |
121 | struct clk *clk; | |
122 | struct device *dev; | |
1da177e4 | 123 | struct i2c_adapter adap; |
61c7cff8 | 124 | |
4fd81eb2 | 125 | struct s3c2410_platform_i2c *pdata; |
5a5f5080 | 126 | int gpios[2]; |
2693ac69 | 127 | struct pinctrl *pctrl; |
61f4d6b4 | 128 | #if defined(CONFIG_ARM_S3C24XX_CPUFREQ) |
61c7cff8 BD |
129 | struct notifier_block freq_transition; |
130 | #endif | |
a7750c3e PD |
131 | struct regmap *sysreg; |
132 | unsigned int sys_i2c_cfg; | |
1da177e4 LT |
133 | }; |
134 | ||
e9a02a3d | 135 | static const struct platform_device_id s3c24xx_driver_ids[] = { |
27452498 KL |
136 | { |
137 | .name = "s3c2410-i2c", | |
138 | .driver_data = 0, | |
139 | }, { | |
140 | .name = "s3c2440-i2c", | |
141 | .driver_data = QUIRK_S3C2440, | |
ec39ef83 KL |
142 | }, { |
143 | .name = "s3c2440-hdmiphy-i2c", | |
144 | .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, | |
27452498 KL |
145 | }, { }, |
146 | }; | |
147 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); | |
148 | ||
117053f7 VA |
149 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); |
150 | ||
27452498 KL |
151 | #ifdef CONFIG_OF |
152 | static const struct of_device_id s3c24xx_i2c_match[] = { | |
153 | { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, | |
154 | { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, | |
ec39ef83 KL |
155 | { .compatible = "samsung,s3c2440-hdmiphy-i2c", |
156 | .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, | |
faf93ff6 GM |
157 | { .compatible = "samsung,exynos5440-i2c", |
158 | .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, | |
117053f7 VA |
159 | { .compatible = "samsung,exynos5-sata-phy-i2c", |
160 | .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) }, | |
27452498 KL |
161 | {}, |
162 | }; | |
163 | MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); | |
164 | #endif | |
1da177e4 | 165 | |
27452498 | 166 | /* s3c24xx_get_device_quirks |
1da177e4 | 167 | * |
27452498 | 168 | * Get controller type either from device tree or platform device variant. |
1da177e4 LT |
169 | */ |
170 | ||
5f1b1155 | 171 | static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) |
1da177e4 | 172 | { |
27452498 KL |
173 | if (pdev->dev.of_node) { |
174 | const struct of_device_id *match; | |
b900ba4c | 175 | match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); |
5f1b1155 | 176 | return (kernel_ulong_t)match->data; |
27452498 | 177 | } |
5a5f5080 | 178 | |
27452498 | 179 | return platform_get_device_id(pdev)->driver_data; |
1da177e4 LT |
180 | } |
181 | ||
1da177e4 LT |
182 | /* s3c24xx_i2c_master_complete |
183 | * | |
184 | * complete the message and wake up the caller, using the given return code, | |
185 | * or zero to mean ok. | |
186 | */ | |
187 | ||
188 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
189 | { | |
190 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
191 | ||
192 | i2c->msg_ptr = 0; | |
193 | i2c->msg = NULL; | |
3d0911bf | 194 | i2c->msg_idx++; |
1da177e4 LT |
195 | i2c->msg_num = 0; |
196 | if (ret) | |
197 | i2c->msg_idx = ret; | |
198 | ||
117053f7 VA |
199 | if (!(i2c->quirks & QUIRK_POLL)) |
200 | wake_up(&i2c->wait); | |
1da177e4 LT |
201 | } |
202 | ||
203 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
204 | { | |
205 | unsigned long tmp; | |
3d0911bf | 206 | |
1da177e4 LT |
207 | tmp = readl(i2c->regs + S3C2410_IICCON); |
208 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
209 | } |
210 | ||
211 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
212 | { | |
213 | unsigned long tmp; | |
3d0911bf | 214 | |
1da177e4 LT |
215 | tmp = readl(i2c->regs + S3C2410_IICCON); |
216 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
217 | } |
218 | ||
219 | /* irq enable/disable functions */ | |
220 | ||
221 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
222 | { | |
223 | unsigned long tmp; | |
3d0911bf | 224 | |
1da177e4 LT |
225 | tmp = readl(i2c->regs + S3C2410_IICCON); |
226 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
227 | } | |
228 | ||
229 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
230 | { | |
231 | unsigned long tmp; | |
3d0911bf | 232 | |
1da177e4 LT |
233 | tmp = readl(i2c->regs + S3C2410_IICCON); |
234 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
235 | } | |
236 | ||
117053f7 VA |
237 | static bool is_ack(struct s3c24xx_i2c *i2c) |
238 | { | |
239 | int tries; | |
240 | ||
241 | for (tries = 50; tries; --tries) { | |
242 | if (readl(i2c->regs + S3C2410_IICCON) | |
243 | & S3C2410_IICCON_IRQPEND) { | |
244 | if (!(readl(i2c->regs + S3C2410_IICSTAT) | |
245 | & S3C2410_IICSTAT_LASTBIT)) | |
246 | return true; | |
247 | } | |
248 | usleep_range(1000, 2000); | |
249 | } | |
9b13494c | 250 | dev_err(i2c->dev, "ack was not received\n"); |
117053f7 VA |
251 | return false; |
252 | } | |
1da177e4 LT |
253 | |
254 | /* s3c24xx_i2c_message_start | |
255 | * | |
3d0911bf | 256 | * put the start of a message onto the bus |
1da177e4 LT |
257 | */ |
258 | ||
3d0911bf | 259 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
260 | struct i2c_msg *msg) |
261 | { | |
262 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
263 | unsigned long stat; | |
264 | unsigned long iiccon; | |
265 | ||
266 | stat = 0; | |
267 | stat |= S3C2410_IICSTAT_TXRXEN; | |
268 | ||
269 | if (msg->flags & I2C_M_RD) { | |
270 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
271 | addr |= 1; | |
272 | } else | |
273 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
274 | ||
275 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
276 | addr ^= 1; | |
277 | ||
48fc7f7e | 278 | /* todo - check for whether ack wanted or not */ |
1da177e4 LT |
279 | s3c24xx_i2c_enable_ack(i2c); |
280 | ||
281 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
282 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 283 | |
1da177e4 LT |
284 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
285 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 286 | |
e00a8cdf BD |
287 | /* delay here to ensure the data byte has gotten onto the bus |
288 | * before the transaction is started */ | |
289 | ||
290 | ndelay(i2c->tx_setup); | |
291 | ||
1da177e4 LT |
292 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
293 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
294 | |
295 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 | 296 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
117053f7 VA |
297 | |
298 | if (i2c->quirks & QUIRK_POLL) { | |
299 | while ((i2c->msg_num != 0) && is_ack(i2c)) { | |
300 | i2c_s3c_irq_nextbyte(i2c, stat); | |
301 | stat = readl(i2c->regs + S3C2410_IICSTAT); | |
302 | ||
303 | if (stat & S3C2410_IICSTAT_ARBITR) | |
304 | dev_err(i2c->dev, "deal with arbitration loss\n"); | |
305 | } | |
306 | } | |
1da177e4 LT |
307 | } |
308 | ||
309 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
310 | { | |
311 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
312 | ||
313 | dev_dbg(i2c->dev, "STOP\n"); | |
314 | ||
0da2e776 DK |
315 | /* |
316 | * The datasheet says that the STOP sequence should be: | |
317 | * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') | |
318 | * 2) I2CCON.4 = 0 - Clear IRQPEND | |
319 | * 3) Wait until the stop condition takes effect. | |
320 | * 4*) I2CSTAT.4 = 0 - Clear TXRXEN | |
321 | * | |
322 | * Where, step "4*" is only for buses with the "HDMIPHY" quirk. | |
323 | * | |
324 | * However, after much experimentation, it appears that: | |
325 | * a) normal buses automatically clear BUSY and transition from | |
326 | * Master->Slave when they complete generating a STOP condition. | |
327 | * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 | |
328 | * after starting the STOP generation here. | |
329 | * b) HDMIPHY bus does neither, so there is no way to do step 3. | |
330 | * There is no indication when this bus has finished generating | |
331 | * STOP. | |
332 | * | |
333 | * In fact, we have found that as soon as the IRQPEND bit is cleared in | |
334 | * step 2, the HDMIPHY bus generates the STOP condition, and then | |
335 | * immediately starts transferring another data byte, even though the | |
336 | * bus is supposedly stopped. This is presumably because the bus is | |
337 | * still in "Master" mode, and its BUSY bit is still set. | |
338 | * | |
339 | * To avoid these extra post-STOP transactions on HDMI phy devices, we | |
340 | * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, | |
341 | * instead of first generating a proper STOP condition. This should | |
342 | * float SDA & SCK terminating the transfer. Subsequent transfers | |
343 | * start with a proper START condition, and proceed normally. | |
344 | * | |
345 | * The HDMIPHY bus is an internal bus that always has exactly two | |
346 | * devices, the host as Master and the HDMIPHY device as the slave. | |
347 | * Skipping the STOP condition has been tested on this bus and works. | |
348 | */ | |
349 | if (i2c->quirks & QUIRK_HDMIPHY) { | |
350 | /* Stop driving the I2C pins */ | |
351 | iicstat &= ~S3C2410_IICSTAT_TXRXEN; | |
352 | } else { | |
353 | /* stop the transfer */ | |
354 | iicstat &= ~S3C2410_IICSTAT_START; | |
355 | } | |
1da177e4 | 356 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 357 | |
1da177e4 | 358 | i2c->state = STATE_STOP; |
3d0911bf | 359 | |
1da177e4 LT |
360 | s3c24xx_i2c_master_complete(i2c, ret); |
361 | s3c24xx_i2c_disable_irq(i2c); | |
362 | } | |
363 | ||
364 | /* helper functions to determine the current state in the set of | |
365 | * messages we are sending */ | |
366 | ||
367 | /* is_lastmsg() | |
368 | * | |
3d0911bf | 369 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
370 | */ |
371 | ||
372 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
373 | { | |
374 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
375 | } | |
376 | ||
377 | /* is_msglast | |
378 | * | |
379 | * returns TRUE if we this is the last byte in the current message | |
380 | */ | |
381 | ||
382 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
383 | { | |
85747311 JY |
384 | /* msg->len is always 1 for the first byte of smbus block read. |
385 | * Actual length will be read from slave. More bytes will be | |
386 | * read according to the length then. */ | |
387 | if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) | |
388 | return 0; | |
389 | ||
1da177e4 LT |
390 | return i2c->msg_ptr == i2c->msg->len-1; |
391 | } | |
392 | ||
393 | /* is_msgend | |
394 | * | |
395 | * returns TRUE if we reached the end of the current message | |
396 | */ | |
397 | ||
398 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
399 | { | |
400 | return i2c->msg_ptr >= i2c->msg->len; | |
401 | } | |
402 | ||
19820510 | 403 | /* i2c_s3c_irq_nextbyte |
1da177e4 LT |
404 | * |
405 | * process an interrupt and work out what to do | |
406 | */ | |
407 | ||
19820510 | 408 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) |
1da177e4 LT |
409 | { |
410 | unsigned long tmp; | |
411 | unsigned char byte; | |
412 | int ret = 0; | |
413 | ||
414 | switch (i2c->state) { | |
415 | ||
416 | case STATE_IDLE: | |
08882d20 | 417 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 | 418 | goto out; |
1da177e4 LT |
419 | |
420 | case STATE_STOP: | |
08882d20 | 421 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 422 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
423 | goto out_ack; |
424 | ||
425 | case STATE_START: | |
426 | /* last thing we did was send a start condition on the | |
427 | * bus, or started a new i2c message | |
428 | */ | |
3d0911bf | 429 | |
63f5c289 | 430 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
431 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
432 | /* ack was not received... */ | |
433 | ||
434 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 435 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
436 | goto out_ack; |
437 | } | |
438 | ||
439 | if (i2c->msg->flags & I2C_M_RD) | |
440 | i2c->state = STATE_READ; | |
441 | else | |
442 | i2c->state = STATE_WRITE; | |
443 | ||
444 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 445 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
446 | |
447 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
448 | s3c24xx_i2c_stop(i2c, 0); | |
449 | goto out_ack; | |
450 | } | |
451 | ||
452 | if (i2c->state == STATE_READ) | |
453 | goto prepare_read; | |
454 | ||
3d0911bf | 455 | /* fall through to the write state, as we will need to |
1da177e4 LT |
456 | * send a byte as well */ |
457 | ||
458 | case STATE_WRITE: | |
459 | /* we are writing data to the device... check for the | |
460 | * end of the message, and if so, work out what to do | |
461 | */ | |
462 | ||
2709781b BD |
463 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
464 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
465 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
466 | ||
467 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
468 | goto out_ack; | |
469 | } | |
470 | } | |
471 | ||
3d0911bf | 472 | retry_write: |
2709781b | 473 | |
1da177e4 LT |
474 | if (!is_msgend(i2c)) { |
475 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
476 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
477 | |
478 | /* delay after writing the byte to allow the | |
479 | * data setup time on the bus, as writing the | |
480 | * data to the register causes the first bit | |
481 | * to appear on SDA, and SCL will change as | |
482 | * soon as the interrupt is acknowledged */ | |
483 | ||
484 | ndelay(i2c->tx_setup); | |
485 | ||
1da177e4 LT |
486 | } else if (!is_lastmsg(i2c)) { |
487 | /* we need to go to the next i2c message */ | |
488 | ||
489 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
490 | ||
491 | i2c->msg_ptr = 0; | |
3d0911bf | 492 | i2c->msg_idx++; |
1da177e4 | 493 | i2c->msg++; |
3d0911bf | 494 | |
1da177e4 LT |
495 | /* check to see if we need to do another message */ |
496 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
497 | ||
498 | if (i2c->msg->flags & I2C_M_RD) { | |
499 | /* cannot do this, the controller | |
500 | * forces us to send a new START | |
501 | * when we change direction */ | |
502 | ||
503 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
504 | } | |
505 | ||
506 | goto retry_write; | |
507 | } else { | |
1da177e4 LT |
508 | /* send the new start */ |
509 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
510 | i2c->state = STATE_START; | |
511 | } | |
512 | ||
513 | } else { | |
514 | /* send stop */ | |
515 | ||
516 | s3c24xx_i2c_stop(i2c, 0); | |
517 | } | |
518 | break; | |
519 | ||
520 | case STATE_READ: | |
3d0911bf | 521 | /* we have a byte of data in the data register, do |
48fc7f7e | 522 | * something with it, and then work out whether we are |
1da177e4 LT |
523 | * going to do any more read/write |
524 | */ | |
525 | ||
1da177e4 LT |
526 | byte = readb(i2c->regs + S3C2410_IICDS); |
527 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
528 | ||
85747311 JY |
529 | /* Add actual length to read for smbus block read */ |
530 | if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) | |
531 | i2c->msg->len += byte; | |
3d0911bf | 532 | prepare_read: |
1da177e4 LT |
533 | if (is_msglast(i2c)) { |
534 | /* last byte of buffer */ | |
535 | ||
536 | if (is_lastmsg(i2c)) | |
537 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 538 | |
1da177e4 LT |
539 | } else if (is_msgend(i2c)) { |
540 | /* ok, we've read the entire buffer, see if there | |
541 | * is anything else we need to do */ | |
542 | ||
543 | if (is_lastmsg(i2c)) { | |
544 | /* last message, send stop and complete */ | |
545 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
546 | ||
547 | s3c24xx_i2c_stop(i2c, 0); | |
548 | } else { | |
549 | /* go to the next transfer */ | |
550 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
551 | ||
552 | i2c->msg_ptr = 0; | |
553 | i2c->msg_idx++; | |
554 | i2c->msg++; | |
555 | } | |
556 | } | |
557 | ||
558 | break; | |
559 | } | |
560 | ||
561 | /* acknowlegde the IRQ and get back on with the work */ | |
562 | ||
563 | out_ack: | |
3d0911bf | 564 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
565 | tmp &= ~S3C2410_IICCON_IRQPEND; |
566 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
567 | out: | |
568 | return ret; | |
569 | } | |
570 | ||
571 | /* s3c24xx_i2c_irq | |
572 | * | |
573 | * top level IRQ servicing routine | |
574 | */ | |
575 | ||
7d12e780 | 576 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
577 | { |
578 | struct s3c24xx_i2c *i2c = dev_id; | |
579 | unsigned long status; | |
580 | unsigned long tmp; | |
581 | ||
582 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
583 | ||
584 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 585 | /* deal with arbitration loss */ |
1da177e4 LT |
586 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
587 | } | |
588 | ||
589 | if (i2c->state == STATE_IDLE) { | |
590 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
591 | ||
3d0911bf | 592 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
593 | tmp &= ~S3C2410_IICCON_IRQPEND; |
594 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
595 | goto out; | |
596 | } | |
3d0911bf | 597 | |
1da177e4 LT |
598 | /* pretty much this leaves us with the fact that we've |
599 | * transmitted or received whatever byte we last sent */ | |
600 | ||
19820510 | 601 | i2c_s3c_irq_nextbyte(i2c, status); |
1da177e4 LT |
602 | |
603 | out: | |
604 | return IRQ_HANDLED; | |
605 | } | |
606 | ||
069a9502 SG |
607 | /* |
608 | * Disable the bus so that we won't get any interrupts from now on, or try | |
609 | * to drive any lines. This is the default state when we don't have | |
610 | * anything to send/receive. | |
611 | * | |
612 | * If there is an event on the bus, or we have a pre-existing event at | |
613 | * kernel boot time, we may not notice the event and the I2C controller | |
614 | * will lock the bus with the I2C clock line low indefinitely. | |
615 | */ | |
616 | static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c) | |
617 | { | |
618 | unsigned long tmp; | |
619 | ||
620 | /* Stop driving the I2C pins */ | |
621 | tmp = readl(i2c->regs + S3C2410_IICSTAT); | |
622 | tmp &= ~S3C2410_IICSTAT_TXRXEN; | |
623 | writel(tmp, i2c->regs + S3C2410_IICSTAT); | |
624 | ||
625 | /* We don't expect any interrupts now, and don't want send acks */ | |
626 | tmp = readl(i2c->regs + S3C2410_IICCON); | |
627 | tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND | | |
628 | S3C2410_IICCON_ACKEN); | |
629 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
630 | } | |
631 | ||
1da177e4 LT |
632 | |
633 | /* s3c24xx_i2c_set_master | |
634 | * | |
635 | * get the i2c bus for a master transaction | |
636 | */ | |
637 | ||
638 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
639 | { | |
640 | unsigned long iicstat; | |
641 | int timeout = 400; | |
642 | ||
643 | while (timeout-- > 0) { | |
644 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 645 | |
1da177e4 LT |
646 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
647 | return 0; | |
648 | ||
649 | msleep(1); | |
650 | } | |
651 | ||
1da177e4 LT |
652 | return -ETIMEDOUT; |
653 | } | |
ec39ef83 | 654 | |
fe724bf9 DK |
655 | /* s3c24xx_i2c_wait_idle |
656 | * | |
657 | * wait for the i2c bus to become idle. | |
658 | */ | |
659 | ||
660 | static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) | |
661 | { | |
662 | unsigned long iicstat; | |
663 | ktime_t start, now; | |
664 | unsigned long delay; | |
31f313d9 | 665 | int spins; |
fe724bf9 DK |
666 | |
667 | /* ensure the stop has been through the bus */ | |
668 | ||
669 | dev_dbg(i2c->dev, "waiting for bus idle\n"); | |
670 | ||
671 | start = now = ktime_get(); | |
672 | ||
673 | /* | |
674 | * Most of the time, the bus is already idle within a few usec of the | |
675 | * end of a transaction. However, really slow i2c devices can stretch | |
676 | * the clock, delaying STOP generation. | |
677 | * | |
31f313d9 MB |
678 | * On slower SoCs this typically happens within a very small number of |
679 | * instructions so busy wait briefly to avoid scheduling overhead. | |
fe724bf9 | 680 | */ |
31f313d9 | 681 | spins = 3; |
fe724bf9 | 682 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); |
31f313d9 MB |
683 | while ((iicstat & S3C2410_IICSTAT_START) && --spins) { |
684 | cpu_relax(); | |
685 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
ec39ef83 KL |
686 | } |
687 | ||
31f313d9 MB |
688 | /* |
689 | * If we do get an appreciable delay as a compromise between idle | |
690 | * detection latency for the normal, fast case, and system load in the | |
691 | * slow device case, use an exponential back off in the polling loop, | |
692 | * up to 1/10th of the total timeout, then continue to poll at a | |
693 | * constant rate up to the timeout. | |
694 | */ | |
fe724bf9 DK |
695 | delay = 1; |
696 | while ((iicstat & S3C2410_IICSTAT_START) && | |
697 | ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { | |
698 | usleep_range(delay, 2 * delay); | |
699 | if (delay < S3C2410_IDLE_TIMEOUT / 10) | |
700 | delay <<= 1; | |
701 | now = ktime_get(); | |
702 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
703 | } | |
704 | ||
705 | if (iicstat & S3C2410_IICSTAT_START) | |
706 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
707 | } |
708 | ||
709 | /* s3c24xx_i2c_doxfer | |
710 | * | |
711 | * this starts an i2c transfer | |
712 | */ | |
713 | ||
3d0911bf BD |
714 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
715 | struct i2c_msg *msgs, int num) | |
1da177e4 | 716 | { |
fe724bf9 | 717 | unsigned long timeout; |
1da177e4 LT |
718 | int ret; |
719 | ||
be44f01e | 720 | if (i2c->suspended) |
61c7cff8 BD |
721 | return -EIO; |
722 | ||
1da177e4 LT |
723 | ret = s3c24xx_i2c_set_master(i2c); |
724 | if (ret != 0) { | |
725 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
726 | ret = -EAGAIN; | |
727 | goto out; | |
728 | } | |
729 | ||
1da177e4 LT |
730 | i2c->msg = msgs; |
731 | i2c->msg_num = num; | |
732 | i2c->msg_ptr = 0; | |
733 | i2c->msg_idx = 0; | |
734 | i2c->state = STATE_START; | |
735 | ||
736 | s3c24xx_i2c_enable_irq(i2c); | |
737 | s3c24xx_i2c_message_start(i2c, msgs); | |
3d0911bf | 738 | |
117053f7 VA |
739 | if (i2c->quirks & QUIRK_POLL) { |
740 | ret = i2c->msg_idx; | |
741 | ||
742 | if (ret != num) | |
743 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
744 | ||
745 | goto out; | |
746 | } | |
747 | ||
1da177e4 LT |
748 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
749 | ||
750 | ret = i2c->msg_idx; | |
751 | ||
3d0911bf | 752 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
753 | * noisy when doing an i2cdetect */ |
754 | ||
755 | if (timeout == 0) | |
756 | dev_dbg(i2c->dev, "timeout\n"); | |
757 | else if (ret != num) | |
758 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
759 | ||
0da2e776 DK |
760 | /* For QUIRK_HDMIPHY, bus is already disabled */ |
761 | if (i2c->quirks & QUIRK_HDMIPHY) | |
762 | goto out; | |
1bc2962e | 763 | |
fe724bf9 | 764 | s3c24xx_i2c_wait_idle(i2c); |
1da177e4 | 765 | |
069a9502 SG |
766 | s3c24xx_i2c_disable_bus(i2c); |
767 | ||
1da177e4 | 768 | out: |
069a9502 SG |
769 | i2c->state = STATE_IDLE; |
770 | ||
1da177e4 LT |
771 | return ret; |
772 | } | |
773 | ||
774 | /* s3c24xx_i2c_xfer | |
775 | * | |
776 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 777 | * transferring across the i2c bus. |
1da177e4 LT |
778 | */ |
779 | ||
780 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
781 | struct i2c_msg *msgs, int num) | |
782 | { | |
783 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
784 | int retry; | |
785 | int ret; | |
786 | ||
c62c3ca5 | 787 | pm_runtime_get_sync(&adap->dev); |
34e81ad5 PO |
788 | ret = clk_enable(i2c->clk); |
789 | if (ret) | |
790 | return ret; | |
d2360b8e | 791 | |
1da177e4 LT |
792 | for (retry = 0; retry < adap->retries; retry++) { |
793 | ||
794 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
795 | ||
d2360b8e | 796 | if (ret != -EAGAIN) { |
34e81ad5 | 797 | clk_disable(i2c->clk); |
a86ae9ff | 798 | pm_runtime_put(&adap->dev); |
1da177e4 | 799 | return ret; |
d2360b8e | 800 | } |
1da177e4 LT |
801 | |
802 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
803 | ||
804 | udelay(100); | |
805 | } | |
806 | ||
34e81ad5 | 807 | clk_disable(i2c->clk); |
a86ae9ff | 808 | pm_runtime_put(&adap->dev); |
1da177e4 LT |
809 | return -EREMOTEIO; |
810 | } | |
811 | ||
812 | /* declare our i2c functionality */ | |
813 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
814 | { | |
14674e70 MB |
815 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | |
816 | I2C_FUNC_PROTOCOL_MANGLING; | |
1da177e4 LT |
817 | } |
818 | ||
819 | /* i2c bus registration info */ | |
820 | ||
8f9082c5 | 821 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
822 | .master_xfer = s3c24xx_i2c_xfer, |
823 | .functionality = s3c24xx_i2c_func, | |
824 | }; | |
825 | ||
1da177e4 LT |
826 | /* s3c24xx_i2c_calcdivisor |
827 | * | |
828 | * return the divisor settings for a given frequency | |
829 | */ | |
830 | ||
831 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
832 | unsigned int *div1, unsigned int *divs) | |
833 | { | |
834 | unsigned int calc_divs = clkin / wanted; | |
835 | unsigned int calc_div1; | |
836 | ||
837 | if (calc_divs > (16*16)) | |
838 | calc_div1 = 512; | |
839 | else | |
840 | calc_div1 = 16; | |
841 | ||
842 | calc_divs += calc_div1-1; | |
843 | calc_divs /= calc_div1; | |
844 | ||
845 | if (calc_divs == 0) | |
846 | calc_divs = 1; | |
847 | if (calc_divs > 17) | |
848 | calc_divs = 17; | |
849 | ||
850 | *divs = calc_divs; | |
851 | *div1 = calc_div1; | |
852 | ||
853 | return clkin / (calc_divs * calc_div1); | |
854 | } | |
855 | ||
61c7cff8 | 856 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
857 | * |
858 | * work out a divisor for the user requested frequency setting, | |
859 | * either by the requested frequency, or scanning the acceptable | |
860 | * range of frequencies until something is found | |
861 | */ | |
862 | ||
61c7cff8 | 863 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 864 | { |
4fd81eb2 | 865 | struct s3c2410_platform_i2c *pdata = i2c->pdata; |
1da177e4 | 866 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 867 | unsigned int divs, div1; |
c564e6ae | 868 | unsigned long target_frequency; |
61c7cff8 | 869 | u32 iiccon; |
1da177e4 | 870 | int freq; |
1da177e4 | 871 | |
61c7cff8 | 872 | i2c->clkrate = clkin; |
1da177e4 | 873 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 874 | |
c564e6ae | 875 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 876 | |
c564e6ae | 877 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 878 | |
c564e6ae | 879 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 880 | |
c564e6ae | 881 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 882 | |
c564e6ae DS |
883 | if (freq > target_frequency) { |
884 | dev_err(i2c->dev, | |
885 | "Unable to achieve desired frequency %luKHz." \ | |
886 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
887 | return -EINVAL; | |
1da177e4 LT |
888 | } |
889 | ||
1da177e4 | 890 | *got = freq; |
61c7cff8 BD |
891 | |
892 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
893 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
894 | iiccon |= (divs-1); | |
895 | ||
896 | if (div1 == 512) | |
897 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
898 | ||
117053f7 VA |
899 | if (i2c->quirks & QUIRK_POLL) |
900 | iiccon |= S3C2410_IICCON_SCALE(2); | |
901 | ||
61c7cff8 BD |
902 | writel(iiccon, i2c->regs + S3C2410_IICCON); |
903 | ||
27452498 | 904 | if (i2c->quirks & QUIRK_S3C2440) { |
a192f715 BD |
905 | unsigned long sda_delay; |
906 | ||
907 | if (pdata->sda_delay) { | |
7031307a MH |
908 | sda_delay = clkin * pdata->sda_delay; |
909 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
910 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
911 | if (sda_delay > 3) | |
912 | sda_delay = 3; | |
913 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
914 | } else | |
915 | sda_delay = 0; | |
916 | ||
917 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
918 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
919 | } | |
920 | ||
61c7cff8 BD |
921 | return 0; |
922 | } | |
923 | ||
61f4d6b4 | 924 | #if defined(CONFIG_ARM_S3C24XX_CPUFREQ) |
61c7cff8 BD |
925 | |
926 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
927 | ||
928 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
929 | unsigned long val, void *data) | |
930 | { | |
931 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
61c7cff8 BD |
932 | unsigned int got; |
933 | int delta_f; | |
934 | int ret; | |
935 | ||
936 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
937 | ||
938 | /* if we're post-change and the input clock has slowed down | |
939 | * or at pre-change and the clock is about to speed up, then | |
940 | * adjust our clock rate. <0 is slow, >0 speedup. | |
941 | */ | |
942 | ||
943 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
944 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
9bcd04bf | 945 | i2c_lock_adapter(&i2c->adap); |
61c7cff8 | 946 | ret = s3c24xx_i2c_clockrate(i2c, &got); |
9bcd04bf | 947 | i2c_unlock_adapter(&i2c->adap); |
61c7cff8 BD |
948 | |
949 | if (ret < 0) | |
950 | dev_err(i2c->dev, "cannot find frequency\n"); | |
951 | else | |
952 | dev_info(i2c->dev, "setting freq %d\n", got); | |
953 | } | |
954 | ||
1da177e4 LT |
955 | return 0; |
956 | } | |
957 | ||
61c7cff8 BD |
958 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
959 | { | |
960 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
961 | ||
962 | return cpufreq_register_notifier(&i2c->freq_transition, | |
963 | CPUFREQ_TRANSITION_NOTIFIER); | |
964 | } | |
965 | ||
966 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
967 | { | |
968 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
969 | CPUFREQ_TRANSITION_NOTIFIER); | |
970 | } | |
971 | ||
972 | #else | |
973 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
974 | { | |
1da177e4 LT |
975 | return 0; |
976 | } | |
977 | ||
61c7cff8 BD |
978 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
979 | { | |
980 | } | |
981 | #endif | |
982 | ||
5a5f5080 TA |
983 | #ifdef CONFIG_OF |
984 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
985 | { | |
986 | int idx, gpio, ret; | |
987 | ||
ec39ef83 KL |
988 | if (i2c->quirks & QUIRK_NO_GPIO) |
989 | return 0; | |
990 | ||
5a5f5080 TA |
991 | for (idx = 0; idx < 2; idx++) { |
992 | gpio = of_get_gpio(i2c->dev->of_node, idx); | |
993 | if (!gpio_is_valid(gpio)) { | |
994 | dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); | |
995 | goto free_gpio; | |
996 | } | |
963f2076 | 997 | i2c->gpios[idx] = gpio; |
5a5f5080 TA |
998 | |
999 | ret = gpio_request(gpio, "i2c-bus"); | |
1000 | if (ret) { | |
1001 | dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); | |
1002 | goto free_gpio; | |
1003 | } | |
1004 | } | |
1005 | return 0; | |
1006 | ||
1007 | free_gpio: | |
1008 | while (--idx >= 0) | |
1009 | gpio_free(i2c->gpios[idx]); | |
1010 | return -EINVAL; | |
1011 | } | |
1012 | ||
1013 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
1014 | { | |
1015 | unsigned int idx; | |
ec39ef83 KL |
1016 | |
1017 | if (i2c->quirks & QUIRK_NO_GPIO) | |
1018 | return; | |
1019 | ||
5a5f5080 TA |
1020 | for (idx = 0; idx < 2; idx++) |
1021 | gpio_free(i2c->gpios[idx]); | |
1022 | } | |
1023 | #else | |
1024 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
1025 | { | |
8ebe661d | 1026 | return 0; |
5a5f5080 TA |
1027 | } |
1028 | ||
1029 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
1030 | { | |
1031 | } | |
1032 | #endif | |
1033 | ||
1da177e4 LT |
1034 | /* s3c24xx_i2c_init |
1035 | * | |
3d0911bf | 1036 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
1037 | */ |
1038 | ||
1039 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
1040 | { | |
1da177e4 LT |
1041 | struct s3c2410_platform_i2c *pdata; |
1042 | unsigned int freq; | |
1043 | ||
1044 | /* get the plafrom data */ | |
1045 | ||
4fd81eb2 | 1046 | pdata = i2c->pdata; |
1da177e4 | 1047 | |
1da177e4 | 1048 | /* write slave address */ |
3d0911bf | 1049 | |
1da177e4 LT |
1050 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
1051 | ||
1052 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
1053 | ||
069a9502 SG |
1054 | writel(0, i2c->regs + S3C2410_IICCON); |
1055 | writel(0, i2c->regs + S3C2410_IICSTAT); | |
61c7cff8 | 1056 | |
1da177e4 LT |
1057 | /* we need to work out the divisors for the clock... */ |
1058 | ||
61c7cff8 | 1059 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
1da177e4 LT |
1060 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
1061 | return -EINVAL; | |
1062 | } | |
1063 | ||
1064 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
1065 | ||
1066 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
069a9502 SG |
1067 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", |
1068 | readl(i2c->regs + S3C2410_IICCON)); | |
1da177e4 | 1069 | |
1da177e4 LT |
1070 | return 0; |
1071 | } | |
1072 | ||
5a5f5080 TA |
1073 | #ifdef CONFIG_OF |
1074 | /* s3c24xx_i2c_parse_dt | |
1075 | * | |
1076 | * Parse the device tree node and retreive the platform data. | |
1077 | */ | |
1078 | ||
1079 | static void | |
1080 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
1081 | { | |
1082 | struct s3c2410_platform_i2c *pdata = i2c->pdata; | |
a7750c3e | 1083 | int id; |
5a5f5080 TA |
1084 | |
1085 | if (!np) | |
1086 | return; | |
1087 | ||
1088 | pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ | |
1089 | of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); | |
1090 | of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); | |
1091 | of_property_read_u32(np, "samsung,i2c-max-bus-freq", | |
1092 | (u32 *)&pdata->frequency); | |
a7750c3e PD |
1093 | /* |
1094 | * Exynos5's legacy i2c controller and new high speed i2c | |
1095 | * controller have muxed interrupt sources. By default the | |
1096 | * interrupts for 4-channel HS-I2C controller are enabled. | |
1097 | * If nodes for first four channels of legacy i2c controller | |
1098 | * are available then re-configure the interrupts via the | |
1099 | * system register. | |
1100 | */ | |
1101 | id = of_alias_get_id(np, "i2c"); | |
1102 | i2c->sysreg = syscon_regmap_lookup_by_phandle(np, | |
1103 | "samsung,sysreg-phandle"); | |
1104 | if (IS_ERR(i2c->sysreg)) | |
1105 | return; | |
1106 | ||
1107 | regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0); | |
5a5f5080 TA |
1108 | } |
1109 | #else | |
1110 | static void | |
1111 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
1112 | { | |
1113 | return; | |
1114 | } | |
1115 | #endif | |
1116 | ||
1da177e4 LT |
1117 | /* s3c24xx_i2c_probe |
1118 | * | |
1119 | * called by the bus driver when a suitable device is found | |
1120 | */ | |
1121 | ||
3ae5eaec | 1122 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 1123 | { |
692acbd3 | 1124 | struct s3c24xx_i2c *i2c; |
4fd81eb2 | 1125 | struct s3c2410_platform_i2c *pdata = NULL; |
1da177e4 LT |
1126 | struct resource *res; |
1127 | int ret; | |
1128 | ||
5a5f5080 | 1129 | if (!pdev->dev.of_node) { |
6d4028c6 | 1130 | pdata = dev_get_platdata(&pdev->dev); |
5a5f5080 TA |
1131 | if (!pdata) { |
1132 | dev_err(&pdev->dev, "no platform data\n"); | |
1133 | return -EINVAL; | |
1134 | } | |
6a039cab | 1135 | } |
399dee23 | 1136 | |
4ea1557f | 1137 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
46797a2a | 1138 | if (!i2c) |
692acbd3 | 1139 | return -ENOMEM; |
692acbd3 | 1140 | |
4fd81eb2 | 1141 | i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
46797a2a | 1142 | if (!i2c->pdata) |
669da30d | 1143 | return -ENOMEM; |
4fd81eb2 | 1144 | |
27452498 | 1145 | i2c->quirks = s3c24xx_get_device_quirks(pdev); |
8d487a43 | 1146 | i2c->sysreg = ERR_PTR(-ENOENT); |
4fd81eb2 TA |
1147 | if (pdata) |
1148 | memcpy(i2c->pdata, pdata, sizeof(*pdata)); | |
5a5f5080 TA |
1149 | else |
1150 | s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); | |
4fd81eb2 | 1151 | |
692acbd3 | 1152 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); |
6031d3df WS |
1153 | i2c->adap.owner = THIS_MODULE; |
1154 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
692acbd3 | 1155 | i2c->adap.retries = 2; |
6031d3df WS |
1156 | i2c->adap.class = I2C_CLASS_DEPRECATED; |
1157 | i2c->tx_setup = 50; | |
692acbd3 | 1158 | |
692acbd3 | 1159 | init_waitqueue_head(&i2c->wait); |
399dee23 | 1160 | |
1da177e4 LT |
1161 | /* find the clock and enable it */ |
1162 | ||
3ae5eaec | 1163 | i2c->dev = &pdev->dev; |
2b255b94 | 1164 | i2c->clk = devm_clk_get(&pdev->dev, "i2c"); |
1da177e4 | 1165 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 1166 | dev_err(&pdev->dev, "cannot get clock\n"); |
669da30d | 1167 | return -ENOENT; |
1da177e4 LT |
1168 | } |
1169 | ||
3ae5eaec | 1170 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 1171 | |
1da177e4 LT |
1172 | |
1173 | /* map the registers */ | |
1174 | ||
1175 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
84dbf809 | 1176 | i2c->regs = devm_ioremap_resource(&pdev->dev, res); |
1da177e4 | 1177 | |
52caa59e LT |
1178 | if (IS_ERR(i2c->regs)) |
1179 | return PTR_ERR(i2c->regs); | |
1da177e4 | 1180 | |
a72ad456 MB |
1181 | dev_dbg(&pdev->dev, "registers %p (%p)\n", |
1182 | i2c->regs, res); | |
1da177e4 LT |
1183 | |
1184 | /* setup info block for the i2c core */ | |
1185 | ||
1186 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1187 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 | 1188 | |
2693ac69 TF |
1189 | i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); |
1190 | ||
658122fe AK |
1191 | /* inititalise the i2c gpio lines */ |
1192 | ||
1193 | if (i2c->pdata->cfg_gpio) { | |
1194 | i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
1195 | } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { | |
d16933b3 | 1196 | return -EINVAL; |
658122fe AK |
1197 | } |
1198 | ||
1da177e4 LT |
1199 | /* initialise the i2c controller */ |
1200 | ||
d16933b3 | 1201 | clk_prepare_enable(i2c->clk); |
1da177e4 | 1202 | ret = s3c24xx_i2c_init(i2c); |
34e81ad5 | 1203 | clk_disable(i2c->clk); |
d16933b3 TB |
1204 | if (ret != 0) { |
1205 | dev_err(&pdev->dev, "I2C controller init failed\n"); | |
1206 | return ret; | |
1207 | } | |
1da177e4 | 1208 | /* find the IRQ for this unit (note, this relies on the init call to |
3d0911bf | 1209 | * ensure no current IRQs pending |
1da177e4 LT |
1210 | */ |
1211 | ||
117053f7 VA |
1212 | if (!(i2c->quirks & QUIRK_POLL)) { |
1213 | i2c->irq = ret = platform_get_irq(pdev, 0); | |
1214 | if (ret <= 0) { | |
1215 | dev_err(&pdev->dev, "cannot find IRQ\n"); | |
34e81ad5 | 1216 | clk_unprepare(i2c->clk); |
117053f7 VA |
1217 | return ret; |
1218 | } | |
1da177e4 | 1219 | |
2b255b94 | 1220 | ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, |
117053f7 | 1221 | dev_name(&pdev->dev), i2c); |
1da177e4 | 1222 | |
117053f7 VA |
1223 | if (ret != 0) { |
1224 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); | |
34e81ad5 | 1225 | clk_unprepare(i2c->clk); |
117053f7 VA |
1226 | return ret; |
1227 | } | |
1da177e4 LT |
1228 | } |
1229 | ||
61c7cff8 | 1230 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 1231 | if (ret < 0) { |
61c7cff8 | 1232 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
34e81ad5 | 1233 | clk_unprepare(i2c->clk); |
d16933b3 | 1234 | return ret; |
1da177e4 LT |
1235 | } |
1236 | ||
399dee23 BD |
1237 | /* Note, previous versions of the driver used i2c_add_adapter() |
1238 | * to add the bus at any number. We now pass the bus number via | |
1239 | * the platform data, so if unset it will now default to always | |
1240 | * being bus 0. | |
1241 | */ | |
1242 | ||
4fd81eb2 | 1243 | i2c->adap.nr = i2c->pdata->bus_num; |
5a5f5080 | 1244 | i2c->adap.dev.of_node = pdev->dev.of_node; |
399dee23 | 1245 | |
eadd709f WS |
1246 | platform_set_drvdata(pdev, i2c); |
1247 | ||
1248 | pm_runtime_enable(&pdev->dev); | |
1249 | ||
399dee23 | 1250 | ret = i2c_add_numbered_adapter(&i2c->adap); |
1da177e4 | 1251 | if (ret < 0) { |
3ae5eaec | 1252 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
eadd709f | 1253 | pm_runtime_disable(&pdev->dev); |
dc6fea44 | 1254 | s3c24xx_i2c_deregister_cpufreq(i2c); |
34e81ad5 | 1255 | clk_unprepare(i2c->clk); |
dc6fea44 | 1256 | return ret; |
1da177e4 LT |
1257 | } |
1258 | ||
c62c3ca5 MB |
1259 | pm_runtime_enable(&i2c->adap.dev); |
1260 | ||
22e965c2 | 1261 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
5b68790c | 1262 | return 0; |
1da177e4 LT |
1263 | } |
1264 | ||
1265 | /* s3c24xx_i2c_remove | |
1266 | * | |
1267 | * called when device is removed from the bus | |
1268 | */ | |
1269 | ||
3ae5eaec | 1270 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 1271 | { |
3ae5eaec | 1272 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 1273 | |
34e81ad5 PO |
1274 | clk_unprepare(i2c->clk); |
1275 | ||
c62c3ca5 MB |
1276 | pm_runtime_disable(&i2c->adap.dev); |
1277 | pm_runtime_disable(&pdev->dev); | |
1278 | ||
61c7cff8 BD |
1279 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1280 | ||
5b68790c | 1281 | i2c_del_adapter(&i2c->adap); |
5b68790c | 1282 | |
2693ac69 TF |
1283 | if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) |
1284 | s3c24xx_i2c_dt_gpio_free(i2c); | |
1da177e4 LT |
1285 | |
1286 | return 0; | |
1287 | } | |
1288 | ||
2935e0e0 | 1289 | #ifdef CONFIG_PM_SLEEP |
6a6c6189 | 1290 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 1291 | { |
6a6c6189 MD |
1292 | struct platform_device *pdev = to_platform_device(dev); |
1293 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
1294 | ||
be44f01e | 1295 | i2c->suspended = 1; |
6a6c6189 | 1296 | |
a7750c3e PD |
1297 | if (!IS_ERR(i2c->sysreg)) |
1298 | regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg); | |
1299 | ||
be44f01e BD |
1300 | return 0; |
1301 | } | |
1302 | ||
b19c1959 | 1303 | static int s3c24xx_i2c_resume_noirq(struct device *dev) |
1da177e4 | 1304 | { |
6a6c6189 MD |
1305 | struct platform_device *pdev = to_platform_device(dev); |
1306 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
34e81ad5 | 1307 | int ret; |
9480e307 | 1308 | |
a7750c3e PD |
1309 | if (!IS_ERR(i2c->sysreg)) |
1310 | regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg); | |
1311 | ||
34e81ad5 PO |
1312 | ret = clk_enable(i2c->clk); |
1313 | if (ret) | |
1314 | return ret; | |
be44f01e | 1315 | s3c24xx_i2c_init(i2c); |
34e81ad5 | 1316 | clk_disable(i2c->clk); |
ce78cc07 | 1317 | i2c->suspended = 0; |
1da177e4 LT |
1318 | |
1319 | return 0; | |
1320 | } | |
2935e0e0 | 1321 | #endif |
1da177e4 | 1322 | |
2935e0e0 | 1323 | #ifdef CONFIG_PM |
47145210 | 1324 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
2935e0e0 | 1325 | #ifdef CONFIG_PM_SLEEP |
6a6c6189 | 1326 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
b19c1959 VP |
1327 | .resume_noirq = s3c24xx_i2c_resume_noirq, |
1328 | .freeze_noirq = s3c24xx_i2c_suspend_noirq, | |
1329 | .thaw_noirq = s3c24xx_i2c_resume_noirq, | |
1330 | .poweroff_noirq = s3c24xx_i2c_suspend_noirq, | |
1331 | .restore_noirq = s3c24xx_i2c_resume_noirq, | |
2935e0e0 | 1332 | #endif |
6a6c6189 MD |
1333 | }; |
1334 | ||
1335 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 1336 | #else |
6a6c6189 | 1337 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
1338 | #endif |
1339 | ||
1340 | /* device driver for platform bus bits */ | |
1341 | ||
7d85ccd8 | 1342 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1343 | .probe = s3c24xx_i2c_probe, |
1344 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1345 | .id_table = s3c24xx_driver_ids, |
3ae5eaec | 1346 | .driver = { |
7d85ccd8 | 1347 | .name = "s3c-i2c", |
6a6c6189 | 1348 | .pm = S3C24XX_DEV_PM_OPS, |
9df7eadf | 1349 | .of_match_table = of_match_ptr(s3c24xx_i2c_match), |
3ae5eaec | 1350 | }, |
1da177e4 LT |
1351 | }; |
1352 | ||
1353 | static int __init i2c_adap_s3c_init(void) | |
1354 | { | |
7d85ccd8 | 1355 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1356 | } |
18dc83a6 | 1357 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1358 | |
1359 | static void __exit i2c_adap_s3c_exit(void) | |
1360 | { | |
7d85ccd8 | 1361 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1362 | } |
1da177e4 LT |
1363 | module_exit(i2c_adap_s3c_exit); |
1364 | ||
1365 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1366 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1367 | MODULE_LICENSE("GPL"); |