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da672773 MD |
1 | /* |
2 | * SuperH Mobile I2C Controller | |
3 | * | |
2d09581b WS |
4 | * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> |
5 | * | |
da672773 MD |
6 | * Copyright (C) 2008 Magnus Damm |
7 | * | |
8 | * Portions of the code based on out-of-tree driver i2c-sh7343.c | |
9 | * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
da672773 MD |
19 | */ |
20 | ||
5bbe6879 WS |
21 | #include <linux/clk.h> |
22 | #include <linux/delay.h> | |
2d09581b WS |
23 | #include <linux/dmaengine.h> |
24 | #include <linux/dma-mapping.h> | |
5bbe6879 WS |
25 | #include <linux/err.h> |
26 | #include <linux/i2c.h> | |
27 | #include <linux/i2c/i2c-sh_mobile.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
da672773 MD |
31 | #include <linux/kernel.h> |
32 | #include <linux/module.h> | |
5bbe6879 | 33 | #include <linux/of_device.h> |
da672773 | 34 | #include <linux/platform_device.h> |
f1a3b994 | 35 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
da672773 | 37 | |
4eb00c9f MD |
38 | /* Transmit operation: */ |
39 | /* */ | |
40 | /* 0 byte transmit */ | |
e7890297 | 41 | /* BUS: S A8 ACK P(*) */ |
4eb00c9f MD |
42 | /* IRQ: DTE WAIT */ |
43 | /* ICIC: */ | |
44 | /* ICCR: 0x94 0x90 */ | |
45 | /* ICDR: A8 */ | |
46 | /* */ | |
47 | /* 1 byte transmit */ | |
e7890297 | 48 | /* BUS: S A8 ACK D8(1) ACK P(*) */ |
4eb00c9f MD |
49 | /* IRQ: DTE WAIT WAIT */ |
50 | /* ICIC: -DTE */ | |
51 | /* ICCR: 0x94 0x90 */ | |
52 | /* ICDR: A8 D8(1) */ | |
53 | /* */ | |
54 | /* 2 byte transmit */ | |
e7890297 | 55 | /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ |
4eb00c9f MD |
56 | /* IRQ: DTE WAIT WAIT WAIT */ |
57 | /* ICIC: -DTE */ | |
58 | /* ICCR: 0x94 0x90 */ | |
59 | /* ICDR: A8 D8(1) D8(2) */ | |
60 | /* */ | |
61 | /* 3 bytes or more, +---------+ gets repeated */ | |
62 | /* */ | |
63 | /* */ | |
64 | /* Receive operation: */ | |
65 | /* */ | |
66 | /* 0 byte receive - not supported since slave may hold SDA low */ | |
67 | /* */ | |
68 | /* 1 byte receive [TX] | [RX] */ | |
e7890297 | 69 | /* BUS: S A8 ACK | D8(1) ACK P(*) */ |
4eb00c9f MD |
70 | /* IRQ: DTE WAIT | WAIT DTE */ |
71 | /* ICIC: -DTE | +DTE */ | |
72 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
73 | /* ICDR: A8 | D8(1) */ | |
74 | /* */ | |
75 | /* 2 byte receive [TX]| [RX] */ | |
e7890297 | 76 | /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ |
4eb00c9f MD |
77 | /* IRQ: DTE WAIT | WAIT WAIT DTE */ |
78 | /* ICIC: -DTE | +DTE */ | |
79 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
80 | /* ICDR: A8 | D8(1) D8(2) */ | |
81 | /* */ | |
e7890297 | 82 | /* 3 byte receive [TX] | [RX] (*) */ |
4eb00c9f MD |
83 | /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ |
84 | /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ | |
85 | /* ICIC: -DTE | +DTE */ | |
86 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
87 | /* ICDR: A8 | D8(1) D8(2) D8(3) */ | |
88 | /* */ | |
89 | /* 4 bytes or more, this part is repeated +---------+ */ | |
90 | /* */ | |
91 | /* */ | |
92 | /* Interrupt order and BUSY flag */ | |
93 | /* ___ _ */ | |
94 | /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ | |
95 | /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ | |
96 | /* */ | |
e7890297 | 97 | /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ |
4eb00c9f MD |
98 | /* ___ */ |
99 | /* WAIT IRQ ________________________________/ \___________ */ | |
100 | /* TACK IRQ ____________________________________/ \_______ */ | |
101 | /* DTE IRQ __________________________________________/ \_ */ | |
102 | /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ | |
103 | /* _______________________________________________ */ | |
104 | /* BUSY __/ \_ */ | |
105 | /* */ | |
e7890297 GL |
106 | /* (*) The STOP condition is only sent by the master at the end of the last */ |
107 | /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ | |
108 | /* only cleared after the STOP condition, so, between messages we have to */ | |
109 | /* poll for the DTE bit. */ | |
110 | /* */ | |
4eb00c9f | 111 | |
da672773 MD |
112 | enum sh_mobile_i2c_op { |
113 | OP_START = 0, | |
4eb00c9f MD |
114 | OP_TX_FIRST, |
115 | OP_TX, | |
da672773 | 116 | OP_TX_STOP, |
2d09581b | 117 | OP_TX_STOP_DATA, |
da672773 | 118 | OP_TX_TO_RX, |
4eb00c9f | 119 | OP_RX, |
da672773 | 120 | OP_RX_STOP, |
4eb00c9f | 121 | OP_RX_STOP_DATA, |
da672773 MD |
122 | }; |
123 | ||
124 | struct sh_mobile_i2c_data { | |
125 | struct device *dev; | |
126 | void __iomem *reg; | |
127 | struct i2c_adapter adap; | |
81f81153 | 128 | unsigned long bus_speed; |
ebd5ac16 | 129 | unsigned int clks_per_count; |
da672773 | 130 | struct clk *clk; |
962b6032 | 131 | u_int8_t icic; |
962b6032 | 132 | u_int8_t flags; |
23a61291 SK |
133 | u_int16_t iccl; |
134 | u_int16_t icch; | |
da672773 MD |
135 | |
136 | spinlock_t lock; | |
137 | wait_queue_head_t wait; | |
138 | struct i2c_msg *msg; | |
139 | int pos; | |
140 | int sr; | |
e7890297 | 141 | bool send_stop; |
2d09581b WS |
142 | |
143 | struct dma_chan *dma_tx; | |
144 | struct dma_chan *dma_rx; | |
145 | struct scatterlist sg; | |
146 | enum dma_data_direction dma_direction; | |
da672773 MD |
147 | }; |
148 | ||
67240dfc WS |
149 | struct sh_mobile_dt_config { |
150 | int clks_per_count; | |
151 | }; | |
152 | ||
962b6032 MD |
153 | #define IIC_FLAG_HAS_ICIC67 (1 << 0) |
154 | ||
23a61291 SK |
155 | #define STANDARD_MODE 100000 |
156 | #define FAST_MODE 400000 | |
da672773 MD |
157 | |
158 | /* Register offsets */ | |
12a55f2d MD |
159 | #define ICDR 0x00 |
160 | #define ICCR 0x04 | |
161 | #define ICSR 0x08 | |
162 | #define ICIC 0x0c | |
163 | #define ICCL 0x10 | |
164 | #define ICCH 0x14 | |
da672773 MD |
165 | |
166 | /* Register bits */ | |
167 | #define ICCR_ICE 0x80 | |
168 | #define ICCR_RACK 0x40 | |
169 | #define ICCR_TRS 0x10 | |
170 | #define ICCR_BBSY 0x04 | |
171 | #define ICCR_SCP 0x01 | |
172 | ||
173 | #define ICSR_SCLM 0x80 | |
174 | #define ICSR_SDAM 0x40 | |
175 | #define SW_DONE 0x20 | |
176 | #define ICSR_BUSY 0x10 | |
177 | #define ICSR_AL 0x08 | |
178 | #define ICSR_TACK 0x04 | |
179 | #define ICSR_WAIT 0x02 | |
180 | #define ICSR_DTE 0x01 | |
181 | ||
962b6032 MD |
182 | #define ICIC_ICCLB8 0x80 |
183 | #define ICIC_ICCHB8 0x40 | |
2d09581b WS |
184 | #define ICIC_TDMAE 0x20 |
185 | #define ICIC_RDMAE 0x10 | |
da672773 MD |
186 | #define ICIC_ALE 0x08 |
187 | #define ICIC_TACKE 0x04 | |
188 | #define ICIC_WAITE 0x02 | |
189 | #define ICIC_DTEE 0x01 | |
190 | ||
12a55f2d MD |
191 | static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) |
192 | { | |
962b6032 MD |
193 | if (offs == ICIC) |
194 | data |= pd->icic; | |
195 | ||
12a55f2d MD |
196 | iowrite8(data, pd->reg + offs); |
197 | } | |
198 | ||
199 | static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) | |
200 | { | |
201 | return ioread8(pd->reg + offs); | |
202 | } | |
203 | ||
204 | static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, | |
205 | unsigned char set, unsigned char clr) | |
206 | { | |
207 | iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); | |
208 | } | |
209 | ||
ed4121e1 | 210 | static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) |
23a61291 SK |
211 | { |
212 | /* | |
213 | * Conditional expression: | |
214 | * ICCL >= COUNT_CLK * (tLOW + tf) | |
215 | * | |
216 | * SH-Mobile IIC hardware starts counting the LOW period of | |
217 | * the SCL signal (tLOW) as soon as it pulls the SCL line. | |
218 | * In order to meet the tLOW timing spec, we need to take into | |
219 | * account the fall time of SCL signal (tf). Default tf value | |
220 | * should be 0.3 us, for safety. | |
221 | */ | |
ed4121e1 | 222 | return (((count_khz * (tLOW + tf)) + 5000) / 10000); |
23a61291 SK |
223 | } |
224 | ||
ed4121e1 | 225 | static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) |
23a61291 SK |
226 | { |
227 | /* | |
228 | * Conditional expression: | |
229 | * ICCH >= COUNT_CLK * (tHIGH + tf) | |
230 | * | |
231 | * SH-Mobile IIC hardware is aware of SCL transition period 'tr', | |
232 | * and can ignore it. SH-Mobile IIC controller starts counting | |
233 | * the HIGH period of the SCL signal (tHIGH) after the SCL input | |
234 | * voltage increases at VIH. | |
235 | * | |
236 | * Afterward it turned out calculating ICCH using only tHIGH spec | |
237 | * will result in violation of the tHD;STA timing spec. We need | |
238 | * to take into account the fall time of SDA signal (tf) at START | |
239 | * condition, in order to meet both tHIGH and tHD;STA specs. | |
240 | */ | |
ed4121e1 | 241 | return (((count_khz * (tHIGH + tf)) + 5000) / 10000); |
23a61291 SK |
242 | } |
243 | ||
6ed7053c | 244 | static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) |
da672773 | 245 | { |
23a61291 SK |
246 | unsigned long i2c_clk_khz; |
247 | u32 tHIGH, tLOW, tf; | |
7663ebef | 248 | uint16_t max_val; |
a5616bd0 | 249 | |
a5616bd0 | 250 | /* Get clock rate after clock is enabled */ |
f887605d | 251 | clk_prepare_enable(pd->clk); |
23a61291 | 252 | i2c_clk_khz = clk_get_rate(pd->clk) / 1000; |
6ed7053c | 253 | clk_disable_unprepare(pd->clk); |
ebd5ac16 | 254 | i2c_clk_khz /= pd->clks_per_count; |
23a61291 SK |
255 | |
256 | if (pd->bus_speed == STANDARD_MODE) { | |
257 | tLOW = 47; /* tLOW = 4.7 us */ | |
258 | tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ | |
259 | tf = 3; /* tf = 0.3 us */ | |
23a61291 SK |
260 | } else if (pd->bus_speed == FAST_MODE) { |
261 | tLOW = 13; /* tLOW = 1.3 us */ | |
262 | tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ | |
263 | tf = 3; /* tf = 0.3 us */ | |
23a61291 SK |
264 | } else { |
265 | dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", | |
266 | pd->bus_speed); | |
6ed7053c | 267 | return -EINVAL; |
962b6032 MD |
268 | } |
269 | ||
ed4121e1 | 270 | pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); |
7663ebef WS |
271 | pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); |
272 | ||
273 | max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; | |
274 | if (pd->iccl > max_val || pd->icch > max_val) { | |
275 | dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", | |
276 | pd->iccl, pd->icch); | |
277 | return -EINVAL; | |
278 | } | |
279 | ||
23a61291 | 280 | /* one more bit of ICCL in ICIC */ |
7663ebef | 281 | if (pd->iccl & 0x100) |
23a61291 | 282 | pd->icic |= ICIC_ICCLB8; |
a5616bd0 | 283 | else |
23a61291 | 284 | pd->icic &= ~ICIC_ICCLB8; |
a5616bd0 | 285 | |
962b6032 | 286 | /* one more bit of ICCH in ICIC */ |
7663ebef | 287 | if (pd->icch & 0x100) |
23a61291 SK |
288 | pd->icic |= ICIC_ICCHB8; |
289 | else | |
290 | pd->icic &= ~ICIC_ICCHB8; | |
962b6032 | 291 | |
7ca01864 | 292 | dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch); |
6ed7053c | 293 | return 0; |
7b0e6292 SK |
294 | } |
295 | ||
296 | static void activate_ch(struct sh_mobile_i2c_data *pd) | |
297 | { | |
298 | /* Wake up device and enable clock */ | |
299 | pm_runtime_get_sync(pd->dev); | |
f887605d | 300 | clk_prepare_enable(pd->clk); |
7b0e6292 | 301 | |
da672773 | 302 | /* Enable channel and configure rx ack */ |
12a55f2d | 303 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); |
da672773 MD |
304 | |
305 | /* Mask all interrupts */ | |
12a55f2d | 306 | iic_wr(pd, ICIC, 0); |
da672773 MD |
307 | |
308 | /* Set the clock */ | |
23a61291 SK |
309 | iic_wr(pd, ICCL, pd->iccl & 0xff); |
310 | iic_wr(pd, ICCH, pd->icch & 0xff); | |
da672773 MD |
311 | } |
312 | ||
313 | static void deactivate_ch(struct sh_mobile_i2c_data *pd) | |
314 | { | |
315 | /* Clear/disable interrupts */ | |
12a55f2d MD |
316 | iic_wr(pd, ICSR, 0); |
317 | iic_wr(pd, ICIC, 0); | |
da672773 MD |
318 | |
319 | /* Disable channel */ | |
12a55f2d | 320 | iic_set_clr(pd, ICCR, 0, ICCR_ICE); |
da672773 | 321 | |
f1a3b994 | 322 | /* Disable clock and mark device as idle */ |
f887605d | 323 | clk_disable_unprepare(pd->clk); |
f1a3b994 | 324 | pm_runtime_put_sync(pd->dev); |
da672773 MD |
325 | } |
326 | ||
327 | static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, | |
328 | enum sh_mobile_i2c_op op, unsigned char data) | |
329 | { | |
330 | unsigned char ret = 0; | |
331 | unsigned long flags; | |
332 | ||
333 | dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); | |
334 | ||
335 | spin_lock_irqsave(&pd->lock, flags); | |
336 | ||
337 | switch (op) { | |
4eb00c9f | 338 | case OP_START: /* issue start and trigger DTE interrupt */ |
a78f6a41 | 339 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); |
da672773 | 340 | break; |
4eb00c9f | 341 | case OP_TX_FIRST: /* disable DTE interrupt and write data */ |
12a55f2d MD |
342 | iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); |
343 | iic_wr(pd, ICDR, data); | |
da672773 | 344 | break; |
4eb00c9f | 345 | case OP_TX: /* write data */ |
12a55f2d | 346 | iic_wr(pd, ICDR, data); |
da672773 | 347 | break; |
2d09581b | 348 | case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */ |
12a55f2d | 349 | iic_wr(pd, ICDR, data); |
2d09581b WS |
350 | /* fallthrough */ |
351 | case OP_TX_STOP: /* issue a stop */ | |
a78f6a41 WS |
352 | iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS |
353 | : ICCR_ICE | ICCR_TRS | ICCR_BBSY); | |
4eb00c9f MD |
354 | break; |
355 | case OP_TX_TO_RX: /* select read mode */ | |
a78f6a41 | 356 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); |
da672773 | 357 | break; |
4eb00c9f | 358 | case OP_RX: /* just read data */ |
12a55f2d | 359 | ret = iic_rd(pd, ICDR); |
da672773 | 360 | break; |
4eb00c9f | 361 | case OP_RX_STOP: /* enable DTE interrupt, issue stop */ |
12a55f2d MD |
362 | iic_wr(pd, ICIC, |
363 | ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); | |
a78f6a41 | 364 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); |
4eb00c9f MD |
365 | break; |
366 | case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ | |
12a55f2d MD |
367 | iic_wr(pd, ICIC, |
368 | ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); | |
369 | ret = iic_rd(pd, ICDR); | |
a78f6a41 | 370 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); |
da672773 MD |
371 | break; |
372 | } | |
373 | ||
374 | spin_unlock_irqrestore(&pd->lock, flags); | |
375 | ||
376 | dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); | |
377 | return ret; | |
378 | } | |
379 | ||
05cf9368 | 380 | static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) |
4eb00c9f | 381 | { |
05cf9368 | 382 | return pd->pos == -1; |
4eb00c9f MD |
383 | } |
384 | ||
05cf9368 | 385 | static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) |
4eb00c9f | 386 | { |
05cf9368 | 387 | return pd->pos == pd->msg->len - 1; |
4eb00c9f MD |
388 | } |
389 | ||
390 | static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, | |
391 | unsigned char *buf) | |
392 | { | |
393 | switch (pd->pos) { | |
394 | case -1: | |
395 | *buf = (pd->msg->addr & 0x7f) << 1; | |
396 | *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; | |
397 | break; | |
398 | default: | |
399 | *buf = pd->msg->buf[pd->pos]; | |
400 | } | |
401 | } | |
402 | ||
403 | static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) | |
404 | { | |
405 | unsigned char data; | |
406 | ||
2d09581b WS |
407 | if (pd->pos == pd->msg->len) { |
408 | /* Send stop if we haven't yet (DMA case) */ | |
409 | if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY)) | |
410 | i2c_op(pd, OP_TX_STOP, 0); | |
4eb00c9f | 411 | return 1; |
2d09581b | 412 | } |
4eb00c9f MD |
413 | |
414 | sh_mobile_i2c_get_data(pd, &data); | |
415 | ||
416 | if (sh_mobile_i2c_is_last_byte(pd)) | |
2d09581b | 417 | i2c_op(pd, OP_TX_STOP_DATA, data); |
4eb00c9f MD |
418 | else if (sh_mobile_i2c_is_first_byte(pd)) |
419 | i2c_op(pd, OP_TX_FIRST, data); | |
420 | else | |
421 | i2c_op(pd, OP_TX, data); | |
422 | ||
423 | pd->pos++; | |
424 | return 0; | |
425 | } | |
426 | ||
427 | static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) | |
428 | { | |
429 | unsigned char data; | |
430 | int real_pos; | |
431 | ||
432 | do { | |
433 | if (pd->pos <= -1) { | |
434 | sh_mobile_i2c_get_data(pd, &data); | |
435 | ||
436 | if (sh_mobile_i2c_is_first_byte(pd)) | |
437 | i2c_op(pd, OP_TX_FIRST, data); | |
438 | else | |
439 | i2c_op(pd, OP_TX, data); | |
440 | break; | |
441 | } | |
442 | ||
443 | if (pd->pos == 0) { | |
444 | i2c_op(pd, OP_TX_TO_RX, 0); | |
445 | break; | |
446 | } | |
447 | ||
448 | real_pos = pd->pos - 2; | |
449 | ||
450 | if (pd->pos == pd->msg->len) { | |
451 | if (real_pos < 0) { | |
452 | i2c_op(pd, OP_RX_STOP, 0); | |
453 | break; | |
454 | } | |
455 | data = i2c_op(pd, OP_RX_STOP_DATA, 0); | |
456 | } else | |
457 | data = i2c_op(pd, OP_RX, 0); | |
458 | ||
bff4056c MD |
459 | if (real_pos >= 0) |
460 | pd->msg->buf[real_pos] = data; | |
4eb00c9f MD |
461 | } while (0); |
462 | ||
463 | pd->pos++; | |
464 | return pd->pos == (pd->msg->len + 2); | |
465 | } | |
466 | ||
da672773 MD |
467 | static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) |
468 | { | |
530834b1 | 469 | struct sh_mobile_i2c_data *pd = dev_id; |
4eb00c9f | 470 | unsigned char sr; |
2d09581b | 471 | int wakeup = 0; |
da672773 | 472 | |
12a55f2d | 473 | sr = iic_rd(pd, ICSR); |
4eb00c9f | 474 | pd->sr |= sr; /* remember state */ |
da672773 MD |
475 | |
476 | dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, | |
4eb00c9f MD |
477 | (pd->msg->flags & I2C_M_RD) ? "read" : "write", |
478 | pd->pos, pd->msg->len); | |
da672773 | 479 | |
2d09581b WS |
480 | /* Kick off TxDMA after preface was done */ |
481 | if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0) | |
482 | iic_set_clr(pd, ICIC, ICIC_TDMAE, 0); | |
483 | else if (sr & (ICSR_AL | ICSR_TACK)) | |
4eb00c9f | 484 | /* don't interrupt transaction - continue to issue stop */ |
12a55f2d | 485 | iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); |
2d09581b | 486 | else if (pd->msg->flags & I2C_M_RD) |
4eb00c9f MD |
487 | wakeup = sh_mobile_i2c_isr_rx(pd); |
488 | else | |
489 | wakeup = sh_mobile_i2c_isr_tx(pd); | |
da672773 | 490 | |
2d09581b WS |
491 | /* Kick off RxDMA after preface was done */ |
492 | if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1) | |
493 | iic_set_clr(pd, ICIC, ICIC_RDMAE, 0); | |
494 | ||
4eb00c9f | 495 | if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ |
12a55f2d | 496 | iic_wr(pd, ICSR, sr & ~ICSR_WAIT); |
da672773 | 497 | |
da672773 MD |
498 | if (wakeup) { |
499 | pd->sr |= SW_DONE; | |
500 | wake_up(&pd->wait); | |
501 | } | |
502 | ||
29fb08c3 SK |
503 | /* defeat write posting to avoid spurious WAIT interrupts */ |
504 | iic_rd(pd, ICSR); | |
505 | ||
da672773 MD |
506 | return IRQ_HANDLED; |
507 | } | |
508 | ||
8cfcae9f WS |
509 | static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd) |
510 | { | |
511 | struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE | |
512 | ? pd->dma_rx : pd->dma_tx; | |
513 | ||
514 | dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg), | |
515 | pd->msg->len, pd->dma_direction); | |
516 | ||
517 | pd->dma_direction = DMA_NONE; | |
518 | } | |
519 | ||
2d09581b WS |
520 | static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd) |
521 | { | |
522 | if (pd->dma_direction == DMA_NONE) | |
523 | return; | |
524 | else if (pd->dma_direction == DMA_FROM_DEVICE) | |
525 | dmaengine_terminate_all(pd->dma_rx); | |
526 | else if (pd->dma_direction == DMA_TO_DEVICE) | |
527 | dmaengine_terminate_all(pd->dma_tx); | |
528 | ||
8cfcae9f | 529 | sh_mobile_i2c_dma_unmap(pd); |
2d09581b WS |
530 | } |
531 | ||
532 | static void sh_mobile_i2c_dma_callback(void *data) | |
533 | { | |
534 | struct sh_mobile_i2c_data *pd = data; | |
535 | ||
8cfcae9f | 536 | sh_mobile_i2c_dma_unmap(pd); |
2d09581b WS |
537 | pd->pos = pd->msg->len; |
538 | ||
539 | iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE); | |
540 | } | |
541 | ||
542 | static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd) | |
543 | { | |
544 | bool read = pd->msg->flags & I2C_M_RD; | |
545 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
546 | struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx; | |
547 | struct dma_async_tx_descriptor *txdesc; | |
548 | dma_addr_t dma_addr; | |
549 | dma_cookie_t cookie; | |
550 | ||
551 | if (!chan) | |
552 | return; | |
553 | ||
8cfcae9f | 554 | dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir); |
2d09581b WS |
555 | if (dma_mapping_error(pd->dev, dma_addr)) { |
556 | dev_dbg(pd->dev, "dma map failed, using PIO\n"); | |
557 | return; | |
558 | } | |
559 | ||
560 | sg_dma_len(&pd->sg) = pd->msg->len; | |
561 | sg_dma_address(&pd->sg) = dma_addr; | |
562 | ||
563 | pd->dma_direction = dir; | |
564 | ||
565 | txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1, | |
566 | read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, | |
567 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
568 | if (!txdesc) { | |
569 | dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n"); | |
570 | sh_mobile_i2c_cleanup_dma(pd); | |
571 | return; | |
572 | } | |
573 | ||
574 | txdesc->callback = sh_mobile_i2c_dma_callback; | |
575 | txdesc->callback_param = pd; | |
576 | ||
577 | cookie = dmaengine_submit(txdesc); | |
578 | if (dma_submit_error(cookie)) { | |
579 | dev_dbg(pd->dev, "submitting dma failed, using PIO\n"); | |
580 | sh_mobile_i2c_cleanup_dma(pd); | |
581 | return; | |
582 | } | |
583 | ||
584 | dma_async_issue_pending(chan); | |
585 | } | |
586 | ||
e7890297 GL |
587 | static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, |
588 | bool do_init) | |
da672773 | 589 | { |
4eb00c9f MD |
590 | if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { |
591 | dev_err(pd->dev, "Unsupported zero length i2c read\n"); | |
5a72b25e | 592 | return -EOPNOTSUPP; |
4eb00c9f MD |
593 | } |
594 | ||
e7890297 GL |
595 | if (do_init) { |
596 | /* Initialize channel registers */ | |
597 | iic_set_clr(pd, ICCR, 0, ICCR_ICE); | |
da672773 | 598 | |
e7890297 GL |
599 | /* Enable channel and configure rx ack */ |
600 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); | |
da672773 | 601 | |
e7890297 GL |
602 | /* Set the clock */ |
603 | iic_wr(pd, ICCL, pd->iccl & 0xff); | |
604 | iic_wr(pd, ICCH, pd->icch & 0xff); | |
605 | } | |
da672773 MD |
606 | |
607 | pd->msg = usr_msg; | |
608 | pd->pos = -1; | |
609 | pd->sr = 0; | |
610 | ||
2d09581b WS |
611 | if (pd->msg->len > 8) |
612 | sh_mobile_i2c_xfer_dma(pd); | |
613 | ||
4eb00c9f | 614 | /* Enable all interrupts to begin with */ |
12a55f2d | 615 | iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); |
da672773 MD |
616 | return 0; |
617 | } | |
618 | ||
e7890297 GL |
619 | static int poll_dte(struct sh_mobile_i2c_data *pd) |
620 | { | |
621 | int i; | |
622 | ||
623 | for (i = 1000; i; i--) { | |
624 | u_int8_t val = iic_rd(pd, ICSR); | |
625 | ||
626 | if (val & ICSR_DTE) | |
627 | break; | |
628 | ||
629 | if (val & ICSR_TACK) | |
5a72b25e | 630 | return -ENXIO; |
e7890297 GL |
631 | |
632 | udelay(10); | |
633 | } | |
634 | ||
5a72b25e | 635 | return i ? 0 : -ETIMEDOUT; |
e7890297 GL |
636 | } |
637 | ||
4b382318 GL |
638 | static int poll_busy(struct sh_mobile_i2c_data *pd) |
639 | { | |
640 | int i; | |
641 | ||
642 | for (i = 1000; i; i--) { | |
643 | u_int8_t val = iic_rd(pd, ICSR); | |
644 | ||
645 | dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); | |
646 | ||
647 | /* the interrupt handler may wake us up before the | |
648 | * transfer is finished, so poll the hardware | |
649 | * until we're done. | |
650 | */ | |
651 | if (!(val & ICSR_BUSY)) { | |
652 | /* handle missing acknowledge and arbitration lost */ | |
5a72b25e WS |
653 | val |= pd->sr; |
654 | if (val & ICSR_TACK) | |
655 | return -ENXIO; | |
656 | if (val & ICSR_AL) | |
657 | return -EAGAIN; | |
4b382318 GL |
658 | break; |
659 | } | |
660 | ||
661 | udelay(10); | |
662 | } | |
663 | ||
5a72b25e | 664 | return i ? 0 : -ETIMEDOUT; |
4b382318 GL |
665 | } |
666 | ||
da672773 MD |
667 | static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, |
668 | struct i2c_msg *msgs, | |
669 | int num) | |
670 | { | |
671 | struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); | |
672 | struct i2c_msg *msg; | |
673 | int err = 0; | |
4b382318 | 674 | int i, k; |
da672773 MD |
675 | |
676 | activate_ch(pd); | |
677 | ||
678 | /* Process all messages */ | |
679 | for (i = 0; i < num; i++) { | |
e7890297 | 680 | bool do_start = pd->send_stop || !i; |
da672773 | 681 | msg = &msgs[i]; |
e7890297 | 682 | pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; |
da672773 | 683 | |
e7890297 | 684 | err = start_ch(pd, msg, do_start); |
da672773 MD |
685 | if (err) |
686 | break; | |
687 | ||
e7890297 GL |
688 | if (do_start) |
689 | i2c_op(pd, OP_START, 0); | |
da672773 MD |
690 | |
691 | /* The interrupt handler takes care of the rest... */ | |
692 | k = wait_event_timeout(pd->wait, | |
693 | pd->sr & (ICSR_TACK | SW_DONE), | |
694 | 5 * HZ); | |
5687265b | 695 | if (!k) { |
da672773 | 696 | dev_err(pd->dev, "Transfer request timed out\n"); |
2d09581b WS |
697 | if (pd->dma_direction != DMA_NONE) |
698 | sh_mobile_i2c_cleanup_dma(pd); | |
699 | ||
5687265b GL |
700 | err = -ETIMEDOUT; |
701 | break; | |
702 | } | |
da672773 | 703 | |
e7890297 GL |
704 | if (pd->send_stop) |
705 | err = poll_busy(pd); | |
706 | else | |
707 | err = poll_dte(pd); | |
4b382318 | 708 | if (err < 0) |
da672773 | 709 | break; |
da672773 MD |
710 | } |
711 | ||
712 | deactivate_ch(pd); | |
713 | ||
714 | if (!err) | |
715 | err = num; | |
716 | return err; | |
717 | } | |
718 | ||
719 | static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) | |
720 | { | |
e7890297 | 721 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; |
da672773 MD |
722 | } |
723 | ||
724 | static struct i2c_algorithm sh_mobile_i2c_algorithm = { | |
725 | .functionality = sh_mobile_i2c_func, | |
726 | .master_xfer = sh_mobile_i2c_xfer, | |
727 | }; | |
728 | ||
67240dfc WS |
729 | static const struct sh_mobile_dt_config default_dt_config = { |
730 | .clks_per_count = 1, | |
731 | }; | |
732 | ||
78df445e | 733 | static const struct sh_mobile_dt_config fast_clock_dt_config = { |
67240dfc WS |
734 | .clks_per_count = 2, |
735 | }; | |
736 | ||
737 | static const struct of_device_id sh_mobile_i2c_dt_ids[] = { | |
738 | { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, | |
78df445e GU |
739 | { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, |
740 | { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config }, | |
741 | { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, | |
742 | { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, | |
743 | { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config }, | |
744 | { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config }, | |
745 | { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, | |
67240dfc WS |
746 | {}, |
747 | }; | |
748 | MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); | |
749 | ||
2d09581b WS |
750 | static int sh_mobile_i2c_request_dma_chan(struct device *dev, enum dma_transfer_direction dir, |
751 | dma_addr_t port_addr, struct dma_chan **chan_ptr) | |
752 | { | |
2d09581b WS |
753 | struct dma_chan *chan; |
754 | struct dma_slave_config cfg; | |
755 | char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; | |
756 | int ret; | |
757 | ||
2d09581b WS |
758 | *chan_ptr = NULL; |
759 | ||
760 | chan = dma_request_slave_channel_reason(dev, chan_name); | |
761 | if (IS_ERR(chan)) { | |
762 | ret = PTR_ERR(chan); | |
763 | dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret); | |
764 | return ret; | |
765 | } | |
766 | ||
767 | memset(&cfg, 0, sizeof(cfg)); | |
768 | cfg.direction = dir; | |
769 | if (dir == DMA_MEM_TO_DEV) { | |
770 | cfg.dst_addr = port_addr; | |
771 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
772 | } else { | |
773 | cfg.src_addr = port_addr; | |
774 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
775 | } | |
776 | ||
777 | ret = dmaengine_slave_config(chan, &cfg); | |
778 | if (ret) { | |
779 | dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret); | |
780 | dma_release_channel(chan); | |
781 | return ret; | |
782 | } | |
783 | ||
784 | *chan_ptr = chan; | |
785 | ||
786 | dev_dbg(dev, "got DMA channel for %s\n", chan_name); | |
787 | return 0; | |
788 | } | |
789 | ||
790 | static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd) | |
791 | { | |
792 | if (pd->dma_tx) { | |
793 | dma_release_channel(pd->dma_tx); | |
794 | pd->dma_tx = NULL; | |
795 | } | |
796 | ||
797 | if (pd->dma_rx) { | |
798 | dma_release_channel(pd->dma_rx); | |
799 | pd->dma_rx = NULL; | |
800 | } | |
801 | } | |
802 | ||
530834b1 | 803 | static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd) |
da672773 MD |
804 | { |
805 | struct resource *res; | |
7fe8a999 WS |
806 | resource_size_t n; |
807 | int k = 0, ret; | |
da672773 MD |
808 | |
809 | while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { | |
7fe8a999 WS |
810 | for (n = res->start; n <= res->end; n++) { |
811 | ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, | |
530834b1 | 812 | 0, dev_name(&dev->dev), pd); |
7fe8a999 WS |
813 | if (ret) { |
814 | dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); | |
815 | return ret; | |
82b20d8b | 816 | } |
da672773 MD |
817 | } |
818 | k++; | |
819 | } | |
820 | ||
7fe8a999 | 821 | return k > 0 ? 0 : -ENOENT; |
da672773 MD |
822 | } |
823 | ||
824 | static int sh_mobile_i2c_probe(struct platform_device *dev) | |
825 | { | |
6d4028c6 | 826 | struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); |
da672773 MD |
827 | struct sh_mobile_i2c_data *pd; |
828 | struct i2c_adapter *adap; | |
829 | struct resource *res; | |
da672773 | 830 | int ret; |
88c289ec | 831 | u32 bus_speed; |
da672773 | 832 | |
4fd31c2e WS |
833 | pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); |
834 | if (!pd) | |
da672773 | 835 | return -ENOMEM; |
da672773 | 836 | |
4fd31c2e | 837 | pd->clk = devm_clk_get(&dev->dev, NULL); |
da672773 | 838 | if (IS_ERR(pd->clk)) { |
1082d5d2 | 839 | dev_err(&dev->dev, "cannot get clock\n"); |
4fd31c2e | 840 | return PTR_ERR(pd->clk); |
da672773 MD |
841 | } |
842 | ||
530834b1 | 843 | ret = sh_mobile_i2c_hook_irqs(dev, pd); |
7fe8a999 | 844 | if (ret) |
4fd31c2e | 845 | return ret; |
da672773 MD |
846 | |
847 | pd->dev = &dev->dev; | |
848 | platform_set_drvdata(dev, pd); | |
849 | ||
850 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
da672773 | 851 | |
4fd31c2e | 852 | pd->reg = devm_ioremap_resource(&dev->dev, res); |
7fe8a999 WS |
853 | if (IS_ERR(pd->reg)) |
854 | return PTR_ERR(pd->reg); | |
da672773 | 855 | |
23a61291 | 856 | /* Use platform data bus speed or STANDARD_MODE */ |
88c289ec WS |
857 | ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); |
858 | pd->bus_speed = ret ? STANDARD_MODE : bus_speed; | |
859 | ||
ebd5ac16 | 860 | pd->clks_per_count = 1; |
67240dfc WS |
861 | |
862 | if (dev->dev.of_node) { | |
863 | const struct of_device_id *match; | |
864 | ||
865 | match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev); | |
866 | if (match) { | |
867 | const struct sh_mobile_dt_config *config; | |
868 | ||
869 | config = match->data; | |
870 | pd->clks_per_count = config->clks_per_count; | |
871 | } | |
872 | } else { | |
873 | if (pdata && pdata->bus_speed) | |
874 | pd->bus_speed = pdata->bus_speed; | |
875 | if (pdata && pdata->clks_per_count) | |
876 | pd->clks_per_count = pdata->clks_per_count; | |
877 | } | |
81f81153 | 878 | |
962b6032 MD |
879 | /* The IIC blocks on SH-Mobile ARM processors |
880 | * come with two new bits in ICIC. | |
881 | */ | |
4fd31c2e | 882 | if (resource_size(res) > 0x17) |
962b6032 MD |
883 | pd->flags |= IIC_FLAG_HAS_ICIC67; |
884 | ||
6ed7053c WS |
885 | ret = sh_mobile_i2c_init(pd); |
886 | if (ret) | |
887 | return ret; | |
7b0e6292 | 888 | |
2d09581b WS |
889 | /* Init DMA */ |
890 | sg_init_table(&pd->sg, 1); | |
891 | pd->dma_direction = DMA_NONE; | |
892 | ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM, | |
893 | res->start + ICDR, &pd->dma_rx); | |
894 | if (ret == -EPROBE_DEFER) | |
895 | return ret; | |
896 | ||
897 | ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV, | |
898 | res->start + ICDR, &pd->dma_tx); | |
899 | if (ret == -EPROBE_DEFER) { | |
900 | sh_mobile_i2c_release_dma(pd); | |
901 | return ret; | |
902 | } | |
903 | ||
f1a3b994 MD |
904 | /* Enable Runtime PM for this device. |
905 | * | |
906 | * Also tell the Runtime PM core to ignore children | |
907 | * for this device since it is valid for us to suspend | |
908 | * this I2C master driver even though the slave devices | |
909 | * on the I2C bus may not be suspended. | |
910 | * | |
911 | * The state of the I2C hardware bus is unaffected by | |
912 | * the Runtime PM state. | |
913 | */ | |
914 | pm_suspend_ignore_children(&dev->dev, true); | |
915 | pm_runtime_enable(&dev->dev); | |
916 | ||
da672773 MD |
917 | /* setup the private data */ |
918 | adap = &pd->adap; | |
919 | i2c_set_adapdata(adap, pd); | |
920 | ||
921 | adap->owner = THIS_MODULE; | |
922 | adap->algo = &sh_mobile_i2c_algorithm; | |
923 | adap->dev.parent = &dev->dev; | |
924 | adap->retries = 5; | |
925 | adap->nr = dev->id; | |
ad337074 | 926 | adap->dev.of_node = dev->dev.of_node; |
da672773 MD |
927 | |
928 | strlcpy(adap->name, dev->name, sizeof(adap->name)); | |
929 | ||
a5616bd0 MD |
930 | spin_lock_init(&pd->lock); |
931 | init_waitqueue_head(&pd->wait); | |
da672773 MD |
932 | |
933 | ret = i2c_add_numbered_adapter(adap); | |
934 | if (ret < 0) { | |
2d09581b | 935 | sh_mobile_i2c_release_dma(pd); |
da672773 | 936 | dev_err(&dev->dev, "cannot add numbered adapter\n"); |
7fe8a999 | 937 | return ret; |
da672773 MD |
938 | } |
939 | ||
7ca01864 WS |
940 | dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz, DMA=%c\n", |
941 | adap->nr, pd->bus_speed, (pd->dma_rx || pd->dma_tx) ? 'y' : 'n'); | |
ad337074 | 942 | |
da672773 | 943 | return 0; |
da672773 MD |
944 | } |
945 | ||
946 | static int sh_mobile_i2c_remove(struct platform_device *dev) | |
947 | { | |
948 | struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); | |
949 | ||
950 | i2c_del_adapter(&pd->adap); | |
2d09581b | 951 | sh_mobile_i2c_release_dma(pd); |
f1a3b994 | 952 | pm_runtime_disable(&dev->dev); |
da672773 MD |
953 | return 0; |
954 | } | |
955 | ||
f1a3b994 MD |
956 | static int sh_mobile_i2c_runtime_nop(struct device *dev) |
957 | { | |
958 | /* Runtime PM callback shared between ->runtime_suspend() | |
959 | * and ->runtime_resume(). Simply returns success. | |
960 | * | |
961 | * This driver re-initializes all registers after | |
962 | * pm_runtime_get_sync() anyway so there is no need | |
963 | * to save and restore registers here. | |
964 | */ | |
965 | return 0; | |
966 | } | |
967 | ||
47145210 | 968 | static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { |
f1a3b994 MD |
969 | .runtime_suspend = sh_mobile_i2c_runtime_nop, |
970 | .runtime_resume = sh_mobile_i2c_runtime_nop, | |
971 | }; | |
972 | ||
da672773 MD |
973 | static struct platform_driver sh_mobile_i2c_driver = { |
974 | .driver = { | |
975 | .name = "i2c-sh_mobile", | |
f1a3b994 | 976 | .pm = &sh_mobile_i2c_dev_pm_ops, |
ad337074 | 977 | .of_match_table = sh_mobile_i2c_dt_ids, |
da672773 MD |
978 | }, |
979 | .probe = sh_mobile_i2c_probe, | |
980 | .remove = sh_mobile_i2c_remove, | |
981 | }; | |
982 | ||
983 | static int __init sh_mobile_i2c_adap_init(void) | |
984 | { | |
985 | return platform_driver_register(&sh_mobile_i2c_driver); | |
986 | } | |
2d09581b | 987 | subsys_initcall(sh_mobile_i2c_adap_init); |
da672773 MD |
988 | |
989 | static void __exit sh_mobile_i2c_adap_exit(void) | |
990 | { | |
991 | platform_driver_unregister(&sh_mobile_i2c_driver); | |
992 | } | |
da672773 MD |
993 | module_exit(sh_mobile_i2c_adap_exit); |
994 | ||
995 | MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); | |
2d09581b | 996 | MODULE_AUTHOR("Magnus Damm and Wolfram Sang"); |
da672773 | 997 | MODULE_LICENSE("GPL v2"); |
7ef0c12a | 998 | MODULE_ALIAS("platform:i2c-sh_mobile"); |