]>
Commit | Line | Data |
---|---|---|
da672773 MD |
1 | /* |
2 | * SuperH Mobile I2C Controller | |
3 | * | |
2d09581b WS |
4 | * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> |
5 | * | |
da672773 MD |
6 | * Copyright (C) 2008 Magnus Damm |
7 | * | |
8 | * Portions of the code based on out-of-tree driver i2c-sh7343.c | |
9 | * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
da672773 MD |
19 | */ |
20 | ||
5bbe6879 WS |
21 | #include <linux/clk.h> |
22 | #include <linux/delay.h> | |
2d09581b WS |
23 | #include <linux/dmaengine.h> |
24 | #include <linux/dma-mapping.h> | |
5bbe6879 WS |
25 | #include <linux/err.h> |
26 | #include <linux/i2c.h> | |
5bbe6879 WS |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/io.h> | |
da672773 MD |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
5bbe6879 | 32 | #include <linux/of_device.h> |
da672773 | 33 | #include <linux/platform_device.h> |
f1a3b994 | 34 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
da672773 | 36 | |
4eb00c9f MD |
37 | /* Transmit operation: */ |
38 | /* */ | |
39 | /* 0 byte transmit */ | |
e7890297 | 40 | /* BUS: S A8 ACK P(*) */ |
4eb00c9f MD |
41 | /* IRQ: DTE WAIT */ |
42 | /* ICIC: */ | |
43 | /* ICCR: 0x94 0x90 */ | |
44 | /* ICDR: A8 */ | |
45 | /* */ | |
46 | /* 1 byte transmit */ | |
e7890297 | 47 | /* BUS: S A8 ACK D8(1) ACK P(*) */ |
4eb00c9f MD |
48 | /* IRQ: DTE WAIT WAIT */ |
49 | /* ICIC: -DTE */ | |
50 | /* ICCR: 0x94 0x90 */ | |
51 | /* ICDR: A8 D8(1) */ | |
52 | /* */ | |
53 | /* 2 byte transmit */ | |
e7890297 | 54 | /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ |
4eb00c9f MD |
55 | /* IRQ: DTE WAIT WAIT WAIT */ |
56 | /* ICIC: -DTE */ | |
57 | /* ICCR: 0x94 0x90 */ | |
58 | /* ICDR: A8 D8(1) D8(2) */ | |
59 | /* */ | |
60 | /* 3 bytes or more, +---------+ gets repeated */ | |
61 | /* */ | |
62 | /* */ | |
63 | /* Receive operation: */ | |
64 | /* */ | |
65 | /* 0 byte receive - not supported since slave may hold SDA low */ | |
66 | /* */ | |
67 | /* 1 byte receive [TX] | [RX] */ | |
e7890297 | 68 | /* BUS: S A8 ACK | D8(1) ACK P(*) */ |
4eb00c9f MD |
69 | /* IRQ: DTE WAIT | WAIT DTE */ |
70 | /* ICIC: -DTE | +DTE */ | |
71 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
72 | /* ICDR: A8 | D8(1) */ | |
73 | /* */ | |
74 | /* 2 byte receive [TX]| [RX] */ | |
e7890297 | 75 | /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ |
4eb00c9f MD |
76 | /* IRQ: DTE WAIT | WAIT WAIT DTE */ |
77 | /* ICIC: -DTE | +DTE */ | |
78 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
79 | /* ICDR: A8 | D8(1) D8(2) */ | |
80 | /* */ | |
e7890297 | 81 | /* 3 byte receive [TX] | [RX] (*) */ |
4eb00c9f MD |
82 | /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ |
83 | /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ | |
84 | /* ICIC: -DTE | +DTE */ | |
85 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
86 | /* ICDR: A8 | D8(1) D8(2) D8(3) */ | |
87 | /* */ | |
88 | /* 4 bytes or more, this part is repeated +---------+ */ | |
89 | /* */ | |
90 | /* */ | |
91 | /* Interrupt order and BUSY flag */ | |
92 | /* ___ _ */ | |
93 | /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ | |
94 | /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ | |
95 | /* */ | |
e7890297 | 96 | /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ |
4eb00c9f MD |
97 | /* ___ */ |
98 | /* WAIT IRQ ________________________________/ \___________ */ | |
99 | /* TACK IRQ ____________________________________/ \_______ */ | |
100 | /* DTE IRQ __________________________________________/ \_ */ | |
101 | /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ | |
102 | /* _______________________________________________ */ | |
103 | /* BUSY __/ \_ */ | |
104 | /* */ | |
e7890297 GL |
105 | /* (*) The STOP condition is only sent by the master at the end of the last */ |
106 | /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ | |
107 | /* only cleared after the STOP condition, so, between messages we have to */ | |
108 | /* poll for the DTE bit. */ | |
109 | /* */ | |
4eb00c9f | 110 | |
da672773 MD |
111 | enum sh_mobile_i2c_op { |
112 | OP_START = 0, | |
4eb00c9f MD |
113 | OP_TX_FIRST, |
114 | OP_TX, | |
da672773 | 115 | OP_TX_STOP, |
2d09581b | 116 | OP_TX_STOP_DATA, |
da672773 | 117 | OP_TX_TO_RX, |
4eb00c9f | 118 | OP_RX, |
da672773 | 119 | OP_RX_STOP, |
4eb00c9f | 120 | OP_RX_STOP_DATA, |
da672773 MD |
121 | }; |
122 | ||
123 | struct sh_mobile_i2c_data { | |
124 | struct device *dev; | |
125 | void __iomem *reg; | |
126 | struct i2c_adapter adap; | |
81f81153 | 127 | unsigned long bus_speed; |
ebd5ac16 | 128 | unsigned int clks_per_count; |
da672773 | 129 | struct clk *clk; |
962b6032 | 130 | u_int8_t icic; |
962b6032 | 131 | u_int8_t flags; |
23a61291 SK |
132 | u_int16_t iccl; |
133 | u_int16_t icch; | |
da672773 MD |
134 | |
135 | spinlock_t lock; | |
136 | wait_queue_head_t wait; | |
137 | struct i2c_msg *msg; | |
138 | int pos; | |
139 | int sr; | |
e7890297 | 140 | bool send_stop; |
32e22409 | 141 | bool stop_after_dma; |
2d09581b | 142 | |
55f5f986 | 143 | struct resource *res; |
2d09581b WS |
144 | struct dma_chan *dma_tx; |
145 | struct dma_chan *dma_rx; | |
146 | struct scatterlist sg; | |
147 | enum dma_data_direction dma_direction; | |
da672773 MD |
148 | }; |
149 | ||
67240dfc WS |
150 | struct sh_mobile_dt_config { |
151 | int clks_per_count; | |
3ded3743 | 152 | void (*setup)(struct sh_mobile_i2c_data *pd); |
67240dfc WS |
153 | }; |
154 | ||
962b6032 MD |
155 | #define IIC_FLAG_HAS_ICIC67 (1 << 0) |
156 | ||
23a61291 SK |
157 | #define STANDARD_MODE 100000 |
158 | #define FAST_MODE 400000 | |
da672773 MD |
159 | |
160 | /* Register offsets */ | |
12a55f2d MD |
161 | #define ICDR 0x00 |
162 | #define ICCR 0x04 | |
163 | #define ICSR 0x08 | |
164 | #define ICIC 0x0c | |
165 | #define ICCL 0x10 | |
166 | #define ICCH 0x14 | |
3ded3743 | 167 | #define ICSTART 0x70 |
da672773 MD |
168 | |
169 | /* Register bits */ | |
170 | #define ICCR_ICE 0x80 | |
171 | #define ICCR_RACK 0x40 | |
172 | #define ICCR_TRS 0x10 | |
173 | #define ICCR_BBSY 0x04 | |
174 | #define ICCR_SCP 0x01 | |
175 | ||
176 | #define ICSR_SCLM 0x80 | |
177 | #define ICSR_SDAM 0x40 | |
178 | #define SW_DONE 0x20 | |
179 | #define ICSR_BUSY 0x10 | |
180 | #define ICSR_AL 0x08 | |
181 | #define ICSR_TACK 0x04 | |
182 | #define ICSR_WAIT 0x02 | |
183 | #define ICSR_DTE 0x01 | |
184 | ||
962b6032 MD |
185 | #define ICIC_ICCLB8 0x80 |
186 | #define ICIC_ICCHB8 0x40 | |
2d09581b WS |
187 | #define ICIC_TDMAE 0x20 |
188 | #define ICIC_RDMAE 0x10 | |
da672773 MD |
189 | #define ICIC_ALE 0x08 |
190 | #define ICIC_TACKE 0x04 | |
191 | #define ICIC_WAITE 0x02 | |
192 | #define ICIC_DTEE 0x01 | |
193 | ||
3ded3743 WS |
194 | #define ICSTART_ICSTART 0x10 |
195 | ||
12a55f2d MD |
196 | static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) |
197 | { | |
962b6032 MD |
198 | if (offs == ICIC) |
199 | data |= pd->icic; | |
200 | ||
12a55f2d MD |
201 | iowrite8(data, pd->reg + offs); |
202 | } | |
203 | ||
204 | static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) | |
205 | { | |
206 | return ioread8(pd->reg + offs); | |
207 | } | |
208 | ||
209 | static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, | |
210 | unsigned char set, unsigned char clr) | |
211 | { | |
212 | iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); | |
213 | } | |
214 | ||
ed4121e1 | 215 | static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) |
23a61291 SK |
216 | { |
217 | /* | |
218 | * Conditional expression: | |
219 | * ICCL >= COUNT_CLK * (tLOW + tf) | |
220 | * | |
221 | * SH-Mobile IIC hardware starts counting the LOW period of | |
222 | * the SCL signal (tLOW) as soon as it pulls the SCL line. | |
223 | * In order to meet the tLOW timing spec, we need to take into | |
224 | * account the fall time of SCL signal (tf). Default tf value | |
225 | * should be 0.3 us, for safety. | |
226 | */ | |
ed4121e1 | 227 | return (((count_khz * (tLOW + tf)) + 5000) / 10000); |
23a61291 SK |
228 | } |
229 | ||
ed4121e1 | 230 | static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) |
23a61291 SK |
231 | { |
232 | /* | |
233 | * Conditional expression: | |
234 | * ICCH >= COUNT_CLK * (tHIGH + tf) | |
235 | * | |
236 | * SH-Mobile IIC hardware is aware of SCL transition period 'tr', | |
237 | * and can ignore it. SH-Mobile IIC controller starts counting | |
238 | * the HIGH period of the SCL signal (tHIGH) after the SCL input | |
239 | * voltage increases at VIH. | |
240 | * | |
241 | * Afterward it turned out calculating ICCH using only tHIGH spec | |
242 | * will result in violation of the tHD;STA timing spec. We need | |
243 | * to take into account the fall time of SDA signal (tf) at START | |
244 | * condition, in order to meet both tHIGH and tHD;STA specs. | |
245 | */ | |
ed4121e1 | 246 | return (((count_khz * (tHIGH + tf)) + 5000) / 10000); |
23a61291 SK |
247 | } |
248 | ||
6ed7053c | 249 | static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) |
da672773 | 250 | { |
23a61291 SK |
251 | unsigned long i2c_clk_khz; |
252 | u32 tHIGH, tLOW, tf; | |
7663ebef | 253 | uint16_t max_val; |
a5616bd0 | 254 | |
a5616bd0 | 255 | /* Get clock rate after clock is enabled */ |
f887605d | 256 | clk_prepare_enable(pd->clk); |
23a61291 | 257 | i2c_clk_khz = clk_get_rate(pd->clk) / 1000; |
6ed7053c | 258 | clk_disable_unprepare(pd->clk); |
ebd5ac16 | 259 | i2c_clk_khz /= pd->clks_per_count; |
23a61291 SK |
260 | |
261 | if (pd->bus_speed == STANDARD_MODE) { | |
262 | tLOW = 47; /* tLOW = 4.7 us */ | |
263 | tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ | |
264 | tf = 3; /* tf = 0.3 us */ | |
23a61291 SK |
265 | } else if (pd->bus_speed == FAST_MODE) { |
266 | tLOW = 13; /* tLOW = 1.3 us */ | |
267 | tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ | |
268 | tf = 3; /* tf = 0.3 us */ | |
23a61291 SK |
269 | } else { |
270 | dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", | |
271 | pd->bus_speed); | |
6ed7053c | 272 | return -EINVAL; |
962b6032 MD |
273 | } |
274 | ||
ed4121e1 | 275 | pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); |
7663ebef WS |
276 | pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); |
277 | ||
278 | max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; | |
279 | if (pd->iccl > max_val || pd->icch > max_val) { | |
280 | dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", | |
281 | pd->iccl, pd->icch); | |
282 | return -EINVAL; | |
283 | } | |
284 | ||
23a61291 | 285 | /* one more bit of ICCL in ICIC */ |
7663ebef | 286 | if (pd->iccl & 0x100) |
23a61291 | 287 | pd->icic |= ICIC_ICCLB8; |
a5616bd0 | 288 | else |
23a61291 | 289 | pd->icic &= ~ICIC_ICCLB8; |
a5616bd0 | 290 | |
962b6032 | 291 | /* one more bit of ICCH in ICIC */ |
7663ebef | 292 | if (pd->icch & 0x100) |
23a61291 SK |
293 | pd->icic |= ICIC_ICCHB8; |
294 | else | |
295 | pd->icic &= ~ICIC_ICCHB8; | |
962b6032 | 296 | |
7ca01864 | 297 | dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch); |
6ed7053c | 298 | return 0; |
7b0e6292 SK |
299 | } |
300 | ||
301 | static void activate_ch(struct sh_mobile_i2c_data *pd) | |
302 | { | |
303 | /* Wake up device and enable clock */ | |
304 | pm_runtime_get_sync(pd->dev); | |
f887605d | 305 | clk_prepare_enable(pd->clk); |
7b0e6292 | 306 | |
da672773 | 307 | /* Enable channel and configure rx ack */ |
12a55f2d | 308 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); |
da672773 MD |
309 | |
310 | /* Mask all interrupts */ | |
12a55f2d | 311 | iic_wr(pd, ICIC, 0); |
da672773 MD |
312 | |
313 | /* Set the clock */ | |
23a61291 SK |
314 | iic_wr(pd, ICCL, pd->iccl & 0xff); |
315 | iic_wr(pd, ICCH, pd->icch & 0xff); | |
da672773 MD |
316 | } |
317 | ||
318 | static void deactivate_ch(struct sh_mobile_i2c_data *pd) | |
319 | { | |
320 | /* Clear/disable interrupts */ | |
12a55f2d MD |
321 | iic_wr(pd, ICSR, 0); |
322 | iic_wr(pd, ICIC, 0); | |
da672773 MD |
323 | |
324 | /* Disable channel */ | |
12a55f2d | 325 | iic_set_clr(pd, ICCR, 0, ICCR_ICE); |
da672773 | 326 | |
f1a3b994 | 327 | /* Disable clock and mark device as idle */ |
f887605d | 328 | clk_disable_unprepare(pd->clk); |
f1a3b994 | 329 | pm_runtime_put_sync(pd->dev); |
da672773 MD |
330 | } |
331 | ||
332 | static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, | |
333 | enum sh_mobile_i2c_op op, unsigned char data) | |
334 | { | |
335 | unsigned char ret = 0; | |
336 | unsigned long flags; | |
337 | ||
338 | dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); | |
339 | ||
340 | spin_lock_irqsave(&pd->lock, flags); | |
341 | ||
342 | switch (op) { | |
4eb00c9f | 343 | case OP_START: /* issue start and trigger DTE interrupt */ |
a78f6a41 | 344 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); |
da672773 | 345 | break; |
4eb00c9f | 346 | case OP_TX_FIRST: /* disable DTE interrupt and write data */ |
12a55f2d MD |
347 | iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); |
348 | iic_wr(pd, ICDR, data); | |
da672773 | 349 | break; |
4eb00c9f | 350 | case OP_TX: /* write data */ |
12a55f2d | 351 | iic_wr(pd, ICDR, data); |
da672773 | 352 | break; |
2d09581b | 353 | case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */ |
12a55f2d | 354 | iic_wr(pd, ICDR, data); |
2d09581b WS |
355 | /* fallthrough */ |
356 | case OP_TX_STOP: /* issue a stop */ | |
a78f6a41 WS |
357 | iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS |
358 | : ICCR_ICE | ICCR_TRS | ICCR_BBSY); | |
4eb00c9f MD |
359 | break; |
360 | case OP_TX_TO_RX: /* select read mode */ | |
a78f6a41 | 361 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); |
da672773 | 362 | break; |
4eb00c9f | 363 | case OP_RX: /* just read data */ |
12a55f2d | 364 | ret = iic_rd(pd, ICDR); |
da672773 | 365 | break; |
4eb00c9f | 366 | case OP_RX_STOP: /* enable DTE interrupt, issue stop */ |
12a55f2d MD |
367 | iic_wr(pd, ICIC, |
368 | ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); | |
a78f6a41 | 369 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); |
4eb00c9f MD |
370 | break; |
371 | case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ | |
12a55f2d MD |
372 | iic_wr(pd, ICIC, |
373 | ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); | |
374 | ret = iic_rd(pd, ICDR); | |
a78f6a41 | 375 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); |
da672773 MD |
376 | break; |
377 | } | |
378 | ||
379 | spin_unlock_irqrestore(&pd->lock, flags); | |
380 | ||
381 | dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); | |
382 | return ret; | |
383 | } | |
384 | ||
05cf9368 | 385 | static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) |
4eb00c9f | 386 | { |
05cf9368 | 387 | return pd->pos == -1; |
4eb00c9f MD |
388 | } |
389 | ||
05cf9368 | 390 | static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) |
4eb00c9f | 391 | { |
05cf9368 | 392 | return pd->pos == pd->msg->len - 1; |
4eb00c9f MD |
393 | } |
394 | ||
395 | static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, | |
396 | unsigned char *buf) | |
397 | { | |
398 | switch (pd->pos) { | |
399 | case -1: | |
3f8a57bb | 400 | *buf = i2c_8bit_addr_from_msg(pd->msg); |
4eb00c9f MD |
401 | break; |
402 | default: | |
403 | *buf = pd->msg->buf[pd->pos]; | |
404 | } | |
405 | } | |
406 | ||
407 | static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) | |
408 | { | |
409 | unsigned char data; | |
410 | ||
2d09581b WS |
411 | if (pd->pos == pd->msg->len) { |
412 | /* Send stop if we haven't yet (DMA case) */ | |
32e22409 | 413 | if (pd->send_stop && pd->stop_after_dma) |
2d09581b | 414 | i2c_op(pd, OP_TX_STOP, 0); |
4eb00c9f | 415 | return 1; |
2d09581b | 416 | } |
4eb00c9f MD |
417 | |
418 | sh_mobile_i2c_get_data(pd, &data); | |
419 | ||
420 | if (sh_mobile_i2c_is_last_byte(pd)) | |
2d09581b | 421 | i2c_op(pd, OP_TX_STOP_DATA, data); |
4eb00c9f MD |
422 | else if (sh_mobile_i2c_is_first_byte(pd)) |
423 | i2c_op(pd, OP_TX_FIRST, data); | |
424 | else | |
425 | i2c_op(pd, OP_TX, data); | |
426 | ||
427 | pd->pos++; | |
428 | return 0; | |
429 | } | |
430 | ||
431 | static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) | |
432 | { | |
433 | unsigned char data; | |
434 | int real_pos; | |
435 | ||
436 | do { | |
437 | if (pd->pos <= -1) { | |
438 | sh_mobile_i2c_get_data(pd, &data); | |
439 | ||
440 | if (sh_mobile_i2c_is_first_byte(pd)) | |
441 | i2c_op(pd, OP_TX_FIRST, data); | |
442 | else | |
443 | i2c_op(pd, OP_TX, data); | |
444 | break; | |
445 | } | |
446 | ||
447 | if (pd->pos == 0) { | |
448 | i2c_op(pd, OP_TX_TO_RX, 0); | |
449 | break; | |
450 | } | |
451 | ||
452 | real_pos = pd->pos - 2; | |
453 | ||
454 | if (pd->pos == pd->msg->len) { | |
32e22409 WS |
455 | if (pd->stop_after_dma) { |
456 | /* Simulate PIO end condition after DMA transfer */ | |
457 | i2c_op(pd, OP_RX_STOP, 0); | |
458 | pd->pos++; | |
459 | break; | |
460 | } | |
461 | ||
4eb00c9f MD |
462 | if (real_pos < 0) { |
463 | i2c_op(pd, OP_RX_STOP, 0); | |
464 | break; | |
465 | } | |
466 | data = i2c_op(pd, OP_RX_STOP_DATA, 0); | |
467 | } else | |
468 | data = i2c_op(pd, OP_RX, 0); | |
469 | ||
bff4056c MD |
470 | if (real_pos >= 0) |
471 | pd->msg->buf[real_pos] = data; | |
4eb00c9f MD |
472 | } while (0); |
473 | ||
474 | pd->pos++; | |
475 | return pd->pos == (pd->msg->len + 2); | |
476 | } | |
477 | ||
da672773 MD |
478 | static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) |
479 | { | |
530834b1 | 480 | struct sh_mobile_i2c_data *pd = dev_id; |
4eb00c9f | 481 | unsigned char sr; |
2d09581b | 482 | int wakeup = 0; |
da672773 | 483 | |
12a55f2d | 484 | sr = iic_rd(pd, ICSR); |
4eb00c9f | 485 | pd->sr |= sr; /* remember state */ |
da672773 MD |
486 | |
487 | dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, | |
4eb00c9f MD |
488 | (pd->msg->flags & I2C_M_RD) ? "read" : "write", |
489 | pd->pos, pd->msg->len); | |
da672773 | 490 | |
2d09581b WS |
491 | /* Kick off TxDMA after preface was done */ |
492 | if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0) | |
493 | iic_set_clr(pd, ICIC, ICIC_TDMAE, 0); | |
494 | else if (sr & (ICSR_AL | ICSR_TACK)) | |
4eb00c9f | 495 | /* don't interrupt transaction - continue to issue stop */ |
12a55f2d | 496 | iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); |
2d09581b | 497 | else if (pd->msg->flags & I2C_M_RD) |
4eb00c9f MD |
498 | wakeup = sh_mobile_i2c_isr_rx(pd); |
499 | else | |
500 | wakeup = sh_mobile_i2c_isr_tx(pd); | |
da672773 | 501 | |
2d09581b WS |
502 | /* Kick off RxDMA after preface was done */ |
503 | if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1) | |
504 | iic_set_clr(pd, ICIC, ICIC_RDMAE, 0); | |
505 | ||
4eb00c9f | 506 | if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ |
12a55f2d | 507 | iic_wr(pd, ICSR, sr & ~ICSR_WAIT); |
da672773 | 508 | |
da672773 MD |
509 | if (wakeup) { |
510 | pd->sr |= SW_DONE; | |
511 | wake_up(&pd->wait); | |
512 | } | |
513 | ||
29fb08c3 SK |
514 | /* defeat write posting to avoid spurious WAIT interrupts */ |
515 | iic_rd(pd, ICSR); | |
516 | ||
da672773 MD |
517 | return IRQ_HANDLED; |
518 | } | |
519 | ||
8cfcae9f WS |
520 | static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd) |
521 | { | |
522 | struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE | |
523 | ? pd->dma_rx : pd->dma_tx; | |
524 | ||
525 | dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg), | |
526 | pd->msg->len, pd->dma_direction); | |
527 | ||
528 | pd->dma_direction = DMA_NONE; | |
529 | } | |
530 | ||
2d09581b WS |
531 | static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd) |
532 | { | |
533 | if (pd->dma_direction == DMA_NONE) | |
534 | return; | |
535 | else if (pd->dma_direction == DMA_FROM_DEVICE) | |
536 | dmaengine_terminate_all(pd->dma_rx); | |
537 | else if (pd->dma_direction == DMA_TO_DEVICE) | |
538 | dmaengine_terminate_all(pd->dma_tx); | |
539 | ||
8cfcae9f | 540 | sh_mobile_i2c_dma_unmap(pd); |
2d09581b WS |
541 | } |
542 | ||
543 | static void sh_mobile_i2c_dma_callback(void *data) | |
544 | { | |
545 | struct sh_mobile_i2c_data *pd = data; | |
546 | ||
8cfcae9f | 547 | sh_mobile_i2c_dma_unmap(pd); |
2d09581b | 548 | pd->pos = pd->msg->len; |
32e22409 | 549 | pd->stop_after_dma = true; |
2d09581b WS |
550 | |
551 | iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE); | |
552 | } | |
553 | ||
55f5f986 WS |
554 | static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev, |
555 | enum dma_transfer_direction dir, dma_addr_t port_addr) | |
556 | { | |
557 | struct dma_chan *chan; | |
558 | struct dma_slave_config cfg; | |
559 | char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; | |
560 | int ret; | |
561 | ||
562 | chan = dma_request_slave_channel_reason(dev, chan_name); | |
563 | if (IS_ERR(chan)) { | |
fe07adec | 564 | ret = PTR_ERR(chan); |
55f5f986 WS |
565 | dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret); |
566 | return chan; | |
567 | } | |
568 | ||
569 | memset(&cfg, 0, sizeof(cfg)); | |
570 | cfg.direction = dir; | |
571 | if (dir == DMA_MEM_TO_DEV) { | |
572 | cfg.dst_addr = port_addr; | |
573 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
574 | } else { | |
575 | cfg.src_addr = port_addr; | |
576 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
577 | } | |
578 | ||
579 | ret = dmaengine_slave_config(chan, &cfg); | |
580 | if (ret) { | |
581 | dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret); | |
582 | dma_release_channel(chan); | |
583 | return ERR_PTR(ret); | |
584 | } | |
585 | ||
586 | dev_dbg(dev, "got DMA channel for %s\n", chan_name); | |
587 | return chan; | |
588 | } | |
589 | ||
2d09581b WS |
590 | static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd) |
591 | { | |
592 | bool read = pd->msg->flags & I2C_M_RD; | |
593 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
594 | struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx; | |
595 | struct dma_async_tx_descriptor *txdesc; | |
596 | dma_addr_t dma_addr; | |
597 | dma_cookie_t cookie; | |
598 | ||
55f5f986 WS |
599 | if (PTR_ERR(chan) == -EPROBE_DEFER) { |
600 | if (read) | |
601 | chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM, | |
602 | pd->res->start + ICDR); | |
603 | else | |
604 | chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV, | |
605 | pd->res->start + ICDR); | |
606 | } | |
607 | ||
e844a799 | 608 | if (IS_ERR(chan)) |
2d09581b WS |
609 | return; |
610 | ||
8cfcae9f | 611 | dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir); |
488d69ea | 612 | if (dma_mapping_error(chan->device->dev, dma_addr)) { |
2d09581b WS |
613 | dev_dbg(pd->dev, "dma map failed, using PIO\n"); |
614 | return; | |
615 | } | |
616 | ||
617 | sg_dma_len(&pd->sg) = pd->msg->len; | |
618 | sg_dma_address(&pd->sg) = dma_addr; | |
619 | ||
620 | pd->dma_direction = dir; | |
621 | ||
622 | txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1, | |
623 | read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, | |
624 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
625 | if (!txdesc) { | |
626 | dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n"); | |
627 | sh_mobile_i2c_cleanup_dma(pd); | |
628 | return; | |
629 | } | |
630 | ||
631 | txdesc->callback = sh_mobile_i2c_dma_callback; | |
632 | txdesc->callback_param = pd; | |
633 | ||
634 | cookie = dmaengine_submit(txdesc); | |
635 | if (dma_submit_error(cookie)) { | |
636 | dev_dbg(pd->dev, "submitting dma failed, using PIO\n"); | |
637 | sh_mobile_i2c_cleanup_dma(pd); | |
638 | return; | |
639 | } | |
640 | ||
641 | dma_async_issue_pending(chan); | |
642 | } | |
643 | ||
e7890297 GL |
644 | static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, |
645 | bool do_init) | |
da672773 | 646 | { |
4eb00c9f MD |
647 | if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { |
648 | dev_err(pd->dev, "Unsupported zero length i2c read\n"); | |
5a72b25e | 649 | return -EOPNOTSUPP; |
4eb00c9f MD |
650 | } |
651 | ||
e7890297 GL |
652 | if (do_init) { |
653 | /* Initialize channel registers */ | |
654 | iic_set_clr(pd, ICCR, 0, ICCR_ICE); | |
da672773 | 655 | |
e7890297 GL |
656 | /* Enable channel and configure rx ack */ |
657 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); | |
da672773 | 658 | |
e7890297 GL |
659 | /* Set the clock */ |
660 | iic_wr(pd, ICCL, pd->iccl & 0xff); | |
661 | iic_wr(pd, ICCH, pd->icch & 0xff); | |
662 | } | |
da672773 MD |
663 | |
664 | pd->msg = usr_msg; | |
665 | pd->pos = -1; | |
666 | pd->sr = 0; | |
667 | ||
2d09581b WS |
668 | if (pd->msg->len > 8) |
669 | sh_mobile_i2c_xfer_dma(pd); | |
670 | ||
4eb00c9f | 671 | /* Enable all interrupts to begin with */ |
12a55f2d | 672 | iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); |
da672773 MD |
673 | return 0; |
674 | } | |
675 | ||
e7890297 GL |
676 | static int poll_dte(struct sh_mobile_i2c_data *pd) |
677 | { | |
678 | int i; | |
679 | ||
680 | for (i = 1000; i; i--) { | |
681 | u_int8_t val = iic_rd(pd, ICSR); | |
682 | ||
683 | if (val & ICSR_DTE) | |
684 | break; | |
685 | ||
686 | if (val & ICSR_TACK) | |
5a72b25e | 687 | return -ENXIO; |
e7890297 GL |
688 | |
689 | udelay(10); | |
690 | } | |
691 | ||
5a72b25e | 692 | return i ? 0 : -ETIMEDOUT; |
e7890297 GL |
693 | } |
694 | ||
4b382318 GL |
695 | static int poll_busy(struct sh_mobile_i2c_data *pd) |
696 | { | |
697 | int i; | |
698 | ||
699 | for (i = 1000; i; i--) { | |
700 | u_int8_t val = iic_rd(pd, ICSR); | |
701 | ||
702 | dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); | |
703 | ||
704 | /* the interrupt handler may wake us up before the | |
705 | * transfer is finished, so poll the hardware | |
706 | * until we're done. | |
707 | */ | |
708 | if (!(val & ICSR_BUSY)) { | |
709 | /* handle missing acknowledge and arbitration lost */ | |
5a72b25e WS |
710 | val |= pd->sr; |
711 | if (val & ICSR_TACK) | |
712 | return -ENXIO; | |
713 | if (val & ICSR_AL) | |
714 | return -EAGAIN; | |
4b382318 GL |
715 | break; |
716 | } | |
717 | ||
718 | udelay(10); | |
719 | } | |
720 | ||
5a72b25e | 721 | return i ? 0 : -ETIMEDOUT; |
4b382318 GL |
722 | } |
723 | ||
da672773 MD |
724 | static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, |
725 | struct i2c_msg *msgs, | |
726 | int num) | |
727 | { | |
728 | struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); | |
729 | struct i2c_msg *msg; | |
730 | int err = 0; | |
365322fb WS |
731 | int i; |
732 | long timeout; | |
da672773 MD |
733 | |
734 | activate_ch(pd); | |
735 | ||
736 | /* Process all messages */ | |
737 | for (i = 0; i < num; i++) { | |
e7890297 | 738 | bool do_start = pd->send_stop || !i; |
da672773 | 739 | msg = &msgs[i]; |
e7890297 | 740 | pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; |
32e22409 | 741 | pd->stop_after_dma = false; |
da672773 | 742 | |
e7890297 | 743 | err = start_ch(pd, msg, do_start); |
da672773 MD |
744 | if (err) |
745 | break; | |
746 | ||
e7890297 GL |
747 | if (do_start) |
748 | i2c_op(pd, OP_START, 0); | |
da672773 MD |
749 | |
750 | /* The interrupt handler takes care of the rest... */ | |
365322fb | 751 | timeout = wait_event_timeout(pd->wait, |
da672773 | 752 | pd->sr & (ICSR_TACK | SW_DONE), |
41bdbd28 | 753 | adapter->timeout); |
365322fb | 754 | if (!timeout) { |
da672773 | 755 | dev_err(pd->dev, "Transfer request timed out\n"); |
2d09581b WS |
756 | if (pd->dma_direction != DMA_NONE) |
757 | sh_mobile_i2c_cleanup_dma(pd); | |
758 | ||
5687265b GL |
759 | err = -ETIMEDOUT; |
760 | break; | |
761 | } | |
da672773 | 762 | |
e7890297 GL |
763 | if (pd->send_stop) |
764 | err = poll_busy(pd); | |
765 | else | |
766 | err = poll_dte(pd); | |
4b382318 | 767 | if (err < 0) |
da672773 | 768 | break; |
da672773 MD |
769 | } |
770 | ||
771 | deactivate_ch(pd); | |
772 | ||
773 | if (!err) | |
774 | err = num; | |
775 | return err; | |
776 | } | |
777 | ||
778 | static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) | |
779 | { | |
e7890297 | 780 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; |
da672773 MD |
781 | } |
782 | ||
92d9d0df | 783 | static const struct i2c_algorithm sh_mobile_i2c_algorithm = { |
da672773 MD |
784 | .functionality = sh_mobile_i2c_func, |
785 | .master_xfer = sh_mobile_i2c_xfer, | |
786 | }; | |
787 | ||
3ded3743 WS |
788 | /* |
789 | * r8a7740 chip has lasting errata on I2C I/O pad reset. | |
790 | * this is work-around for it. | |
791 | */ | |
792 | static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd) | |
793 | { | |
794 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); | |
795 | iic_rd(pd, ICCR); /* dummy read */ | |
796 | ||
797 | iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0); | |
798 | iic_rd(pd, ICSTART); /* dummy read */ | |
799 | ||
800 | udelay(10); | |
801 | ||
802 | iic_wr(pd, ICCR, ICCR_SCP); | |
803 | iic_wr(pd, ICSTART, 0); | |
804 | ||
805 | udelay(10); | |
806 | ||
807 | iic_wr(pd, ICCR, ICCR_TRS); | |
808 | udelay(10); | |
809 | iic_wr(pd, ICCR, 0); | |
810 | udelay(10); | |
811 | iic_wr(pd, ICCR, ICCR_TRS); | |
812 | udelay(10); | |
813 | } | |
814 | ||
67240dfc WS |
815 | static const struct sh_mobile_dt_config default_dt_config = { |
816 | .clks_per_count = 1, | |
817 | }; | |
818 | ||
78df445e | 819 | static const struct sh_mobile_dt_config fast_clock_dt_config = { |
67240dfc WS |
820 | .clks_per_count = 2, |
821 | }; | |
822 | ||
3ded3743 WS |
823 | static const struct sh_mobile_dt_config r8a7740_dt_config = { |
824 | .clks_per_count = 1, | |
825 | .setup = sh_mobile_i2c_r8a7740_workaround, | |
826 | }; | |
827 | ||
67240dfc | 828 | static const struct of_device_id sh_mobile_i2c_dt_ids[] = { |
78df445e | 829 | { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, |
3ded3743 | 830 | { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config }, |
78df445e GU |
831 | { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config }, |
832 | { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, | |
833 | { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, | |
834 | { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config }, | |
835 | { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config }, | |
b880ccaf | 836 | { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config }, |
7bb6da5a | 837 | { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config }, |
b880ccaf | 838 | { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config }, |
78df445e | 839 | { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, |
b880ccaf | 840 | { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, |
67240dfc WS |
841 | {}, |
842 | }; | |
843 | MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); | |
844 | ||
2d09581b WS |
845 | static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd) |
846 | { | |
e844a799 | 847 | if (!IS_ERR(pd->dma_tx)) { |
2d09581b | 848 | dma_release_channel(pd->dma_tx); |
e844a799 | 849 | pd->dma_tx = ERR_PTR(-EPROBE_DEFER); |
2d09581b WS |
850 | } |
851 | ||
e844a799 | 852 | if (!IS_ERR(pd->dma_rx)) { |
2d09581b | 853 | dma_release_channel(pd->dma_rx); |
e844a799 | 854 | pd->dma_rx = ERR_PTR(-EPROBE_DEFER); |
2d09581b WS |
855 | } |
856 | } | |
857 | ||
530834b1 | 858 | static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd) |
da672773 MD |
859 | { |
860 | struct resource *res; | |
7fe8a999 WS |
861 | resource_size_t n; |
862 | int k = 0, ret; | |
da672773 MD |
863 | |
864 | while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { | |
7fe8a999 WS |
865 | for (n = res->start; n <= res->end; n++) { |
866 | ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, | |
530834b1 | 867 | 0, dev_name(&dev->dev), pd); |
7fe8a999 WS |
868 | if (ret) { |
869 | dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); | |
870 | return ret; | |
82b20d8b | 871 | } |
da672773 MD |
872 | } |
873 | k++; | |
874 | } | |
875 | ||
7fe8a999 | 876 | return k > 0 ? 0 : -ENOENT; |
da672773 MD |
877 | } |
878 | ||
879 | static int sh_mobile_i2c_probe(struct platform_device *dev) | |
880 | { | |
881 | struct sh_mobile_i2c_data *pd; | |
882 | struct i2c_adapter *adap; | |
883 | struct resource *res; | |
90b84c05 | 884 | const struct of_device_id *match; |
da672773 | 885 | int ret; |
88c289ec | 886 | u32 bus_speed; |
da672773 | 887 | |
4fd31c2e WS |
888 | pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); |
889 | if (!pd) | |
da672773 | 890 | return -ENOMEM; |
da672773 | 891 | |
4fd31c2e | 892 | pd->clk = devm_clk_get(&dev->dev, NULL); |
da672773 | 893 | if (IS_ERR(pd->clk)) { |
1082d5d2 | 894 | dev_err(&dev->dev, "cannot get clock\n"); |
4fd31c2e | 895 | return PTR_ERR(pd->clk); |
da672773 MD |
896 | } |
897 | ||
530834b1 | 898 | ret = sh_mobile_i2c_hook_irqs(dev, pd); |
7fe8a999 | 899 | if (ret) |
4fd31c2e | 900 | return ret; |
da672773 MD |
901 | |
902 | pd->dev = &dev->dev; | |
903 | platform_set_drvdata(dev, pd); | |
904 | ||
905 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
da672773 | 906 | |
55f5f986 | 907 | pd->res = res; |
4fd31c2e | 908 | pd->reg = devm_ioremap_resource(&dev->dev, res); |
7fe8a999 WS |
909 | if (IS_ERR(pd->reg)) |
910 | return PTR_ERR(pd->reg); | |
da672773 | 911 | |
88c289ec WS |
912 | ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); |
913 | pd->bus_speed = ret ? STANDARD_MODE : bus_speed; | |
ebd5ac16 | 914 | pd->clks_per_count = 1; |
67240dfc | 915 | |
90b84c05 WS |
916 | match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev); |
917 | if (match) { | |
918 | const struct sh_mobile_dt_config *config = match->data; | |
67240dfc | 919 | |
90b84c05 | 920 | pd->clks_per_count = config->clks_per_count; |
3ded3743 | 921 | |
90b84c05 WS |
922 | if (config->setup) |
923 | config->setup(pd); | |
67240dfc | 924 | } |
81f81153 | 925 | |
962b6032 MD |
926 | /* The IIC blocks on SH-Mobile ARM processors |
927 | * come with two new bits in ICIC. | |
928 | */ | |
4fd31c2e | 929 | if (resource_size(res) > 0x17) |
962b6032 MD |
930 | pd->flags |= IIC_FLAG_HAS_ICIC67; |
931 | ||
6ed7053c WS |
932 | ret = sh_mobile_i2c_init(pd); |
933 | if (ret) | |
934 | return ret; | |
7b0e6292 | 935 | |
2d09581b WS |
936 | /* Init DMA */ |
937 | sg_init_table(&pd->sg, 1); | |
938 | pd->dma_direction = DMA_NONE; | |
55f5f986 | 939 | pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER); |
2d09581b | 940 | |
f1a3b994 MD |
941 | /* Enable Runtime PM for this device. |
942 | * | |
943 | * Also tell the Runtime PM core to ignore children | |
944 | * for this device since it is valid for us to suspend | |
945 | * this I2C master driver even though the slave devices | |
946 | * on the I2C bus may not be suspended. | |
947 | * | |
948 | * The state of the I2C hardware bus is unaffected by | |
949 | * the Runtime PM state. | |
950 | */ | |
951 | pm_suspend_ignore_children(&dev->dev, true); | |
952 | pm_runtime_enable(&dev->dev); | |
953 | ||
da672773 MD |
954 | /* setup the private data */ |
955 | adap = &pd->adap; | |
956 | i2c_set_adapdata(adap, pd); | |
957 | ||
958 | adap->owner = THIS_MODULE; | |
959 | adap->algo = &sh_mobile_i2c_algorithm; | |
960 | adap->dev.parent = &dev->dev; | |
961 | adap->retries = 5; | |
962 | adap->nr = dev->id; | |
ad337074 | 963 | adap->dev.of_node = dev->dev.of_node; |
da672773 MD |
964 | |
965 | strlcpy(adap->name, dev->name, sizeof(adap->name)); | |
966 | ||
a5616bd0 MD |
967 | spin_lock_init(&pd->lock); |
968 | init_waitqueue_head(&pd->wait); | |
da672773 MD |
969 | |
970 | ret = i2c_add_numbered_adapter(adap); | |
971 | if (ret < 0) { | |
2d09581b | 972 | sh_mobile_i2c_release_dma(pd); |
7fe8a999 | 973 | return ret; |
da672773 MD |
974 | } |
975 | ||
55f5f986 | 976 | dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed); |
ad337074 | 977 | |
da672773 | 978 | return 0; |
da672773 MD |
979 | } |
980 | ||
981 | static int sh_mobile_i2c_remove(struct platform_device *dev) | |
982 | { | |
983 | struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); | |
984 | ||
985 | i2c_del_adapter(&pd->adap); | |
2d09581b | 986 | sh_mobile_i2c_release_dma(pd); |
f1a3b994 | 987 | pm_runtime_disable(&dev->dev); |
da672773 MD |
988 | return 0; |
989 | } | |
990 | ||
f1a3b994 MD |
991 | static int sh_mobile_i2c_runtime_nop(struct device *dev) |
992 | { | |
993 | /* Runtime PM callback shared between ->runtime_suspend() | |
994 | * and ->runtime_resume(). Simply returns success. | |
995 | * | |
996 | * This driver re-initializes all registers after | |
997 | * pm_runtime_get_sync() anyway so there is no need | |
998 | * to save and restore registers here. | |
999 | */ | |
1000 | return 0; | |
1001 | } | |
1002 | ||
47145210 | 1003 | static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { |
f1a3b994 MD |
1004 | .runtime_suspend = sh_mobile_i2c_runtime_nop, |
1005 | .runtime_resume = sh_mobile_i2c_runtime_nop, | |
1006 | }; | |
1007 | ||
da672773 MD |
1008 | static struct platform_driver sh_mobile_i2c_driver = { |
1009 | .driver = { | |
1010 | .name = "i2c-sh_mobile", | |
f1a3b994 | 1011 | .pm = &sh_mobile_i2c_dev_pm_ops, |
ad337074 | 1012 | .of_match_table = sh_mobile_i2c_dt_ids, |
da672773 MD |
1013 | }, |
1014 | .probe = sh_mobile_i2c_probe, | |
1015 | .remove = sh_mobile_i2c_remove, | |
1016 | }; | |
1017 | ||
1018 | static int __init sh_mobile_i2c_adap_init(void) | |
1019 | { | |
1020 | return platform_driver_register(&sh_mobile_i2c_driver); | |
1021 | } | |
2d09581b | 1022 | subsys_initcall(sh_mobile_i2c_adap_init); |
da672773 MD |
1023 | |
1024 | static void __exit sh_mobile_i2c_adap_exit(void) | |
1025 | { | |
1026 | platform_driver_unregister(&sh_mobile_i2c_driver); | |
1027 | } | |
da672773 MD |
1028 | module_exit(sh_mobile_i2c_adap_exit); |
1029 | ||
1030 | MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); | |
2d09581b | 1031 | MODULE_AUTHOR("Magnus Damm and Wolfram Sang"); |
da672773 | 1032 | MODULE_LICENSE("GPL v2"); |
7ef0c12a | 1033 | MODULE_ALIAS("platform:i2c-sh_mobile"); |