[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-sirf.c

/*
 * I2C bus driver for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#define SIRFSOC_I2C_CLK_CTRL		0x00
#define SIRFSOC_I2C_STATUS		0x0C
#define SIRFSOC_I2C_CTRL		0x10
#define SIRFSOC_I2C_IO_CTRL		0x14
#define SIRFSOC_I2C_SDA_DELAY		0x18
#define SIRFSOC_I2C_CMD_START		0x1C
#define SIRFSOC_I2C_CMD_BUF		0x30
#define SIRFSOC_I2C_DATA_BUF		0x80

#define SIRFSOC_I2C_CMD_BUF_MAX		16
#define SIRFSOC_I2C_DATA_BUF_MAX	16

#define SIRFSOC_I2C_CMD(x)		(SIRFSOC_I2C_CMD_BUF + (x)*0x04)
#define SIRFSOC_I2C_DATA_MASK(x)        (0xFF<<(((x)&3)*8))
#define SIRFSOC_I2C_DATA_SHIFT(x)       (((x)&3)*8)

#define SIRFSOC_I2C_DIV_MASK		(0xFFFF)

/* I2C status flags */
#define SIRFSOC_I2C_STAT_BUSY		BIT(0)
#define SIRFSOC_I2C_STAT_TIP		BIT(1)
#define SIRFSOC_I2C_STAT_NACK		BIT(2)
#define SIRFSOC_I2C_STAT_TR_INT		BIT(4)
#define SIRFSOC_I2C_STAT_STOP		BIT(6)
#define SIRFSOC_I2C_STAT_CMD_DONE	BIT(8)
#define SIRFSOC_I2C_STAT_ERR		BIT(9)
#define SIRFSOC_I2C_CMD_INDEX		(0x1F<<16)

/* I2C control flags */
#define SIRFSOC_I2C_RESET		BIT(0)
#define SIRFSOC_I2C_CORE_EN		BIT(1)
#define SIRFSOC_I2C_MASTER_MODE		BIT(2)
#define SIRFSOC_I2C_CMD_DONE_EN		BIT(11)
#define SIRFSOC_I2C_ERR_INT_EN		BIT(12)

#define SIRFSOC_I2C_SDA_DELAY_MASK	(0xFF)
#define SIRFSOC_I2C_SCLF_FILTER		(3<<8)

#define SIRFSOC_I2C_START_CMD		BIT(0)

#define SIRFSOC_I2C_CMD_RP(x)		((x)&0x7)
#define SIRFSOC_I2C_NACK		BIT(3)
#define SIRFSOC_I2C_WRITE		BIT(4)
#define SIRFSOC_I2C_READ		BIT(5)
#define SIRFSOC_I2C_STOP		BIT(6)
#define SIRFSOC_I2C_START		BIT(7)

#define SIRFSOC_I2C_DEFAULT_SPEED 100000
#define SIRFSOC_I2C_ERR_NOACK      1
#define SIRFSOC_I2C_ERR_TIMEOUT    2

struct sirfsoc_i2c {
	void __iomem *base;
	struct clk *clk;
	u32 cmd_ptr;		/* Current position in CMD buffer */
	u8 *buf;		/* Buffer passed by user */
	u32 msg_len;		/* Message length */
	u32 finished_len;	/* number of bytes read/written */
	u32 read_cmd_len;	/* number of read cmd sent */
	int msg_read;		/* 1 indicates a read message */
	int err_status;		/* 1 indicates an error on bus */

	u32 sda_delay;		/* For suspend/resume */
	u32 clk_div;
	int last;		/* Last message in transfer, STOP cmd can be sent */

	struct completion done;	/* indicates completion of message transfer */
	struct i2c_adapter adapter;
};

static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
{
	u32 data = 0;
	int i;

	for (i = 0; i < siic->read_cmd_len; i++) {
		if (!(i & 0x3))
			data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
		siic->buf[siic->finished_len++] =
			(u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
				SIRFSOC_I2C_DATA_SHIFT(i));
	}
}

static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
{
	u32 regval;
	int i = 0;

	if (siic->msg_read) {
		while (((siic->finished_len + i) < siic->msg_len)
				&& (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
			regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
			if (((siic->finished_len + i) ==
					(siic->msg_len - 1)) && siic->last)
				regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
			writel(regval,
				siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
			i++;
		}

		siic->read_cmd_len = i;
	} else {
		while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
				&& (siic->finished_len < siic->msg_len)) {
			regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
			if ((siic->finished_len == (siic->msg_len - 1))
				&& siic->last)
				regval |= SIRFSOC_I2C_STOP;
			writel(regval,
				siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
			writel(siic->buf[siic->finished_len++],
				siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
		}
	}
	siic->cmd_ptr = 0;

	/* Trigger the transfer */
	writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
}

static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
{
	struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
	u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);

	if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
		/* Error conditions */
		siic->err_status = SIRFSOC_I2C_ERR_NOACK;
		writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);

		if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
			dev_dbg(&siic->adapter.dev, "ACK not received\n");
		else
			dev_err(&siic->adapter.dev, "I2C error\n");

		/*
		 * Due to hardware ANOMALY, we need to reset I2C earlier after
		 * we get NOACK while accessing non-existing clients, otherwise
		 * we will get errors even we access existing clients later
		 */
		writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
				siic->base + SIRFSOC_I2C_CTRL);
		while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
			cpu_relax();

		complete(&siic->done);
	} else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
		/* CMD buffer execution complete */
		if (siic->msg_read)
			i2c_sirfsoc_read_data(siic);
		if (siic->finished_len == siic->msg_len)
			complete(&siic->done);
		else /* Fill a new CMD buffer for left data */
			i2c_sirfsoc_queue_cmd(siic);

		writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
	}

	return IRQ_HANDLED;
}

static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
	struct i2c_msg *msg)
{
	unsigned char addr;
	u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;

	/* no data and last message -> add STOP */
	if (siic->last && (msg->len == 0))
		regval |= SIRFSOC_I2C_STOP;

	writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));

	addr = msg->addr << 1;	/* Generate address */
	if (msg->flags & I2C_M_RD)
		addr |= 1;

	/* Reverse direction bit */
	if (msg->flags & I2C_M_REV_DIR_ADDR)
		addr ^= 1;

	writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
}

static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
{
	u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
	/* timeout waiting for the xfer to finish or fail */
	int timeout = msecs_to_jiffies((msg->len + 1) * 50);

	i2c_sirfsoc_set_address(siic, msg);

	writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
		siic->base + SIRFSOC_I2C_CTRL);
	i2c_sirfsoc_queue_cmd(siic);

	if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
		siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
		dev_err(&siic->adapter.dev, "Transfer timeout\n");
	}

	writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
		siic->base + SIRFSOC_I2C_CTRL);
	writel(0, siic->base + SIRFSOC_I2C_CMD_START);

	/* i2c control doesn't response, reset it */
	if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
		writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
			siic->base + SIRFSOC_I2C_CTRL);
		while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
			cpu_relax();
	}
	return siic->err_status ? -EAGAIN : 0;
}

static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
	int num)
{
	struct sirfsoc_i2c *siic = adap->algo_data;
	int i, ret;

	clk_enable(siic->clk);

	for (i = 0; i < num; i++) {
		siic->buf = msgs[i].buf;
		siic->msg_len = msgs[i].len;
		siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
		siic->err_status = 0;
		siic->cmd_ptr = 0;
		siic->finished_len = 0;
		siic->last = (i == (num - 1));

		ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
		if (ret) {
			clk_disable(siic->clk);
			return ret;
		}
	}

	clk_disable(siic->clk);
	return num;
}

/* I2C algorithms associated with this master controller driver */
static const struct i2c_algorithm i2c_sirfsoc_algo = {
	.master_xfer = i2c_sirfsoc_xfer,
	.functionality = i2c_sirfsoc_func,
};

static int i2c_sirfsoc_probe(struct platform_device *pdev)
{
	struct sirfsoc_i2c *siic;
	struct i2c_adapter *adap;
	struct resource *mem_res;
	struct clk *clk;
	int bitrate;
	int ctrl_speed;
	int irq;

	int err;
	u32 regval;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		err = PTR_ERR(clk);
		dev_err(&pdev->dev, "Clock get failed\n");
		goto err_get_clk;
	}

	err = clk_prepare(clk);
	if (err) {
		dev_err(&pdev->dev, "Clock prepare failed\n");
		goto err_clk_prep;
	}

	err = clk_enable(clk);
	if (err) {
		dev_err(&pdev->dev, "Clock enable failed\n");
		goto err_clk_en;
	}

	ctrl_speed = clk_get_rate(clk);

	siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
	if (!siic) {
		err = -ENOMEM;
		goto out;
	}
	adap = &siic->adapter;
	adap->class = I2C_CLASS_DEPRECATED;

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
	if (IS_ERR(siic->base)) {
		err = PTR_ERR(siic->base);
		goto out;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		err = irq;
		goto out;
	}
	err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
		dev_name(&pdev->dev), siic);
	if (err)
		goto out;

	adap->algo = &i2c_sirfsoc_algo;
	adap->algo_data = siic;
	adap->retries = 3;

	adap->dev.of_node = pdev->dev.of_node;
	adap->dev.parent = &pdev->dev;
	adap->nr = pdev->id;

	strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));

	platform_set_drvdata(pdev, adap);
	init_completion(&siic->done);

	/* Controller Initalisation */

	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
		cpu_relax();
	writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
		siic->base + SIRFSOC_I2C_CTRL);

	siic->clk = clk;

	err = of_property_read_u32(pdev->dev.of_node,
		"clock-frequency", &bitrate);
	if (err < 0)
		bitrate = SIRFSOC_I2C_DEFAULT_SPEED;

	/*
	 * Due to some hardware design issues, we need to tune the formula.
	 * Since i2c is open drain interface that allows the slave to
	 * stall the transaction by holding the SCL line at '0', the RTL
	 * implementation is waiting for SCL feedback from the pin after
	 * setting it to High-Z ('1'). This wait adds to the high-time
	 * interval counter few cycles of the input synchronization
	 * (depending on the SCL_FILTER_REG field), and also the time it
	 * takes for the board pull-up resistor to rise the SCL line.
	 * For slow SCL settings these additions are negligible,
	 * but they start to affect the speed when clock is set to faster
	 * frequencies.
	 * Through the actual tests, use the different user_div value(which
	 * in the divider formular 'Fio / (Fi2c * user_div)') to adapt
	 * the different ranges of i2c bus clock frequency, to make the SCL
	 * more accurate.
	 */
	if (bitrate <= 30000)
		regval = ctrl_speed / (bitrate * 5);
	else if (bitrate > 30000 && bitrate <= 280000)
		regval = (2 * ctrl_speed) / (bitrate * 11);
	else
		regval = ctrl_speed / (bitrate * 6);

	writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
	if (regval > 0xFF)
		writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
	else
		writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);

	err = i2c_add_numbered_adapter(adap);
	if (err < 0) {
		dev_err(&pdev->dev, "Can't add new i2c adapter\n");
		goto out;
	}

	clk_disable(clk);

	dev_info(&pdev->dev, " I2C adapter ready to operate\n");

	return 0;

out:
	clk_disable(clk);
err_clk_en:
	clk_unprepare(clk);
err_clk_prep:
	clk_put(clk);
err_get_clk:
	return err;
}

static int i2c_sirfsoc_remove(struct platform_device *pdev)
{
	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	struct sirfsoc_i2c *siic = adapter->algo_data;

	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	i2c_del_adapter(adapter);
	clk_unprepare(siic->clk);
	clk_put(siic->clk);
	return 0;
}

#ifdef CONFIG_PM
static int i2c_sirfsoc_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	struct sirfsoc_i2c *siic = adapter->algo_data;

	clk_enable(siic->clk);
	siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
	siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
	clk_disable(siic->clk);
	return 0;
}

static int i2c_sirfsoc_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	struct sirfsoc_i2c *siic = adapter->algo_data;

	clk_enable(siic->clk);
	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
		cpu_relax();
	writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
		siic->base + SIRFSOC_I2C_CTRL);
	writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
	writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
	clk_disable(siic->clk);
	return 0;
}

static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
	.suspend = i2c_sirfsoc_suspend,
	.resume = i2c_sirfsoc_resume,
};
#endif

static const struct of_device_id sirfsoc_i2c_of_match[] = {
	{ .compatible = "sirf,prima2-i2c", },
	{},
};
MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);

static struct platform_driver i2c_sirfsoc_driver = {
	.driver = {
		.name = "sirfsoc_i2c",
#ifdef CONFIG_PM
		.pm = &i2c_sirfsoc_pm_ops,
#endif
		.of_match_table = sirfsoc_i2c_of_match,
	},
	.probe = i2c_sirfsoc_probe,
	.remove = i2c_sirfsoc_remove,
};
module_platform_driver(i2c_sirfsoc_driver);

MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
	"Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
979b907f ZS	1	/*
	2	* I2C bus driver for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/interrupt.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/slab.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/i2c.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18
	19	#define SIRFSOC_I2C_CLK_CTRL 0x00
	20	#define SIRFSOC_I2C_STATUS 0x0C
	21	#define SIRFSOC_I2C_CTRL 0x10
	22	#define SIRFSOC_I2C_IO_CTRL 0x14
	23	#define SIRFSOC_I2C_SDA_DELAY 0x18
	24	#define SIRFSOC_I2C_CMD_START 0x1C
	25	#define SIRFSOC_I2C_CMD_BUF 0x30
	26	#define SIRFSOC_I2C_DATA_BUF 0x80
	27
	28	#define SIRFSOC_I2C_CMD_BUF_MAX 16
	29	#define SIRFSOC_I2C_DATA_BUF_MAX 16
	30
	31	#define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
	32	#define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
	33	#define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
	34
	35	#define SIRFSOC_I2C_DIV_MASK (0xFFFF)
	36
	37	/* I2C status flags */
	38	#define SIRFSOC_I2C_STAT_BUSY BIT(0)
	39	#define SIRFSOC_I2C_STAT_TIP BIT(1)
	40	#define SIRFSOC_I2C_STAT_NACK BIT(2)
	41	#define SIRFSOC_I2C_STAT_TR_INT BIT(4)
	42	#define SIRFSOC_I2C_STAT_STOP BIT(6)
	43	#define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
	44	#define SIRFSOC_I2C_STAT_ERR BIT(9)
	45	#define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
	46
	47	/* I2C control flags */
	48	#define SIRFSOC_I2C_RESET BIT(0)
	49	#define SIRFSOC_I2C_CORE_EN BIT(1)
	50	#define SIRFSOC_I2C_MASTER_MODE BIT(2)
	51	#define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
	52	#define SIRFSOC_I2C_ERR_INT_EN BIT(12)
	53
	54	#define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
	55	#define SIRFSOC_I2C_SCLF_FILTER (3<<8)
	56
	57	#define SIRFSOC_I2C_START_CMD BIT(0)
	58
	59	#define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
	60	#define SIRFSOC_I2C_NACK BIT(3)
	61	#define SIRFSOC_I2C_WRITE BIT(4)
	62	#define SIRFSOC_I2C_READ BIT(5)
	63	#define SIRFSOC_I2C_STOP BIT(6)
	64	#define SIRFSOC_I2C_START BIT(7)
65
66	#define SIRFSOC_I2C_DEFAULT_SPEED 100000
c984319a ZS	67	#define SIRFSOC_I2C_ERR_NOACK 1
c984319a ZS	68	#define SIRFSOC_I2C_ERR_TIMEOUT 2
979b907f ZS	69
	70	struct sirfsoc_i2c {
	71	void __iomem *base;
	72	struct clk *clk;
	73	u32 cmd_ptr; /* Current position in CMD buffer */
	74	u8 buf; / Buffer passed by user */
	75	u32 msg_len; /* Message length */
	76	u32 finished_len; /* number of bytes read/written */
	77	u32 read_cmd_len; /* number of read cmd sent */
	78	int msg_read; /* 1 indicates a read message */
	79	int err_status; /* 1 indicates an error on bus */
	80
	81	u32 sda_delay; /* For suspend/resume */
	82	u32 clk_div;
	83	int last; /* Last message in transfer, STOP cmd can be sent */
	84
	85	struct completion done; /* indicates completion of message transfer */
	86	struct i2c_adapter adapter;
	87	};
	88
	89	static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
	90	{
	91	u32 data = 0;
	92	int i;
	93
	94	for (i = 0; i < siic->read_cmd_len; i++) {
	95	if (!(i & 0x3))
	96	data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
	97	siic->buf[siic->finished_len++] =
	98	(u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
	99	SIRFSOC_I2C_DATA_SHIFT(i));
	100	}
	101	}
	102
	103	static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
	104	{
	105	u32 regval;
	106	int i = 0;
	107
	108	if (siic->msg_read) {
	109	while (((siic->finished_len + i) < siic->msg_len)
	110	&& (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
	111	regval = SIRFSOC_I2C_READ \| SIRFSOC_I2C_CMD_RP(0);
	112	if (((siic->finished_len + i) ==
	113	(siic->msg_len - 1)) && siic->last)
	114	regval \|= SIRFSOC_I2C_STOP \| SIRFSOC_I2C_NACK;
	115	writel(regval,
	116	siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
	117	i++;
	118	}
	119
	120	siic->read_cmd_len = i;
	121	} else {
	122	while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
	123	&& (siic->finished_len < siic->msg_len)) {
	124	regval = SIRFSOC_I2C_WRITE \| SIRFSOC_I2C_CMD_RP(0);
	125	if ((siic->finished_len == (siic->msg_len - 1))
	126	&& siic->last)
	127	regval \|= SIRFSOC_I2C_STOP;
	128	writel(regval,
	129	siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
	130	writel(siic->buf[siic->finished_len++],
	131	siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
	132	}
133	}
134	siic->cmd_ptr = 0;
135
136	/* Trigger the transfer */
137	writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
138	}
139
140	static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
141	{
142	struct sirfsoc_i2c siic = (struct sirfsoc_i2c )dev_id;
143	u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
144
145	if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
146	/* Error conditions */
c984319a	147	siic->err_status = SIRFSOC_I2C_ERR_NOACK;
979b907f ZS	148	writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
	149
	150	if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
c984319a	151	dev_dbg(&siic->adapter.dev, "ACK not received\n");
979b907f ZS	152	else
	153	dev_err(&siic->adapter.dev, "I2C error\n");
	154
c984319a ZS	155	/*
	156	* Due to hardware ANOMALY, we need to reset I2C earlier after
	157	* we get NOACK while accessing non-existing clients, otherwise
	158	* we will get errors even we access existing clients later
	159	*/
	160	writel(readl(siic->base + SIRFSOC_I2C_CTRL) \| SIRFSOC_I2C_RESET,
	161	siic->base + SIRFSOC_I2C_CTRL);
	162	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
	163	cpu_relax();
	164
979b907f ZS	165	complete(&siic->done);
	166	} else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
	167	/* CMD buffer execution complete */
	168	if (siic->msg_read)
	169	i2c_sirfsoc_read_data(siic);
	170	if (siic->finished_len == siic->msg_len)
	171	complete(&siic->done);
	172	else /* Fill a new CMD buffer for left data */
	173	i2c_sirfsoc_queue_cmd(siic);
	174
	175	writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
	176	}
	177
	178	return IRQ_HANDLED;
	179	}
	180
	181	static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
	182	struct i2c_msg *msg)
	183	{
	184	unsigned char addr;
	185	u32 regval = SIRFSOC_I2C_START \| SIRFSOC_I2C_CMD_RP(0) \| SIRFSOC_I2C_WRITE;
	186
	187	/* no data and last message -> add STOP */
	188	if (siic->last && (msg->len == 0))
	189	regval \|= SIRFSOC_I2C_STOP;
	190
	191	writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
	192
	193	addr = msg->addr << 1; /* Generate address */
	194	if (msg->flags & I2C_M_RD)
	195	addr \|= 1;
	196
5ebffa6b ZS	197	/* Reverse direction bit */
	198	if (msg->flags & I2C_M_REV_DIR_ADDR)
	199	addr ^= 1;
	200
979b907f ZS	201	writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
	202	}
	203
	204	static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c siic, struct i2c_msg msg)
	205	{
	206	u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
	207	/* timeout waiting for the xfer to finish or fail */
	208	int timeout = msecs_to_jiffies((msg->len + 1) * 50);
979b907f ZS	209
	210	i2c_sirfsoc_set_address(siic, msg);
	211
	212	writel(regval \| SIRFSOC_I2C_CMD_DONE_EN \| SIRFSOC_I2C_ERR_INT_EN,
	213	siic->base + SIRFSOC_I2C_CTRL);
	214	i2c_sirfsoc_queue_cmd(siic);
	215
	216	if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
c984319a	217	siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
979b907f ZS	218	dev_err(&siic->adapter.dev, "Transfer timeout\n");
	219	}
	220
	221	writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN \| SIRFSOC_I2C_ERR_INT_EN),
	222	siic->base + SIRFSOC_I2C_CTRL);
	223	writel(0, siic->base + SIRFSOC_I2C_CMD_START);
	224
c984319a ZS	225	/* i2c control doesn't response, reset it */
c984319a ZS	226	if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
979b907f ZS	227	writel(readl(siic->base + SIRFSOC_I2C_CTRL) \| SIRFSOC_I2C_RESET,
	228	siic->base + SIRFSOC_I2C_CTRL);
	229	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
	230	cpu_relax();
979b907f	231	}
617da00c	232	return siic->err_status ? -EAGAIN : 0;
979b907f ZS	233	}
	234
	235	static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
	236	{
	237	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	238	}
	239
	240	static int i2c_sirfsoc_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
	241	int num)
	242	{
	243	struct sirfsoc_i2c *siic = adap->algo_data;
	244	int i, ret;
	245
	246	clk_enable(siic->clk);
	247
	248	for (i = 0; i < num; i++) {
	249	siic->buf = msgs[i].buf;
	250	siic->msg_len = msgs[i].len;
	251	siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
	252	siic->err_status = 0;
	253	siic->cmd_ptr = 0;
	254	siic->finished_len = 0;
	255	siic->last = (i == (num - 1));
	256
	257	ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
	258	if (ret) {
	259	clk_disable(siic->clk);
	260	return ret;
	261	}
	262	}
	263
	264	clk_disable(siic->clk);
	265	return num;
	266	}
	267
	268	/* I2C algorithms associated with this master controller driver */
	269	static const struct i2c_algorithm i2c_sirfsoc_algo = {
	270	.master_xfer = i2c_sirfsoc_xfer,
	271	.functionality = i2c_sirfsoc_func,
	272	};
	273
0b255e92	274	static int i2c_sirfsoc_probe(struct platform_device *pdev)
979b907f ZS	275	{
	276	struct sirfsoc_i2c *siic;
	277	struct i2c_adapter *adap;
	278	struct resource *mem_res;
	279	struct clk *clk;
	280	int bitrate;
	281	int ctrl_speed;
	282	int irq;
	283
	284	int err;
	285	u32 regval;
	286
	287	clk = clk_get(&pdev->dev, NULL);
	288	if (IS_ERR(clk)) {
	289	err = PTR_ERR(clk);
	290	dev_err(&pdev->dev, "Clock get failed\n");
	291	goto err_get_clk;
	292	}
	293
	294	err = clk_prepare(clk);
	295	if (err) {
	296	dev_err(&pdev->dev, "Clock prepare failed\n");
	297	goto err_clk_prep;
	298	}
	299
	300	err = clk_enable(clk);
	301	if (err) {
	302	dev_err(&pdev->dev, "Clock enable failed\n");
	303	goto err_clk_en;
	304	}
	305
	306	ctrl_speed = clk_get_rate(clk);
	307
	308	siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
	309	if (!siic) {
979b907f ZS	310	err = -ENOMEM;
	311	goto out;
	312	}
	313	adap = &siic->adapter;
ca9c77cd	314	adap->class = I2C_CLASS_DEPRECATED;
979b907f ZS	315
979b907f ZS	316	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809 TR	317	siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
	318	if (IS_ERR(siic->base)) {
	319	err = PTR_ERR(siic->base);
979b907f ZS	320	goto out;
	321	}
	322
	323	irq = platform_get_irq(pdev, 0);
	324	if (irq < 0) {
	325	err = irq;
	326	goto out;
	327	}
	328	err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
	329	dev_name(&pdev->dev), siic);
	330	if (err)
	331	goto out;
	332
	333	adap->algo = &i2c_sirfsoc_algo;
	334	adap->algo_data = siic;
617da00c	335	adap->retries = 3;
979b907f	336
bfd059da	337	adap->dev.of_node = pdev->dev.of_node;
979b907f ZS	338	adap->dev.parent = &pdev->dev;
	339	adap->nr = pdev->id;
	340
	341	strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
	342
	343	platform_set_drvdata(pdev, adap);
	344	init_completion(&siic->done);
	345
	346	/* Controller Initalisation */
	347
	348	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	349	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
	350	cpu_relax();
	351	writel(SIRFSOC_I2C_CORE_EN \| SIRFSOC_I2C_MASTER_MODE,
	352	siic->base + SIRFSOC_I2C_CTRL);
	353
	354	siic->clk = clk;
	355
	356	err = of_property_read_u32(pdev->dev.of_node,
	357	"clock-frequency", &bitrate);
	358	if (err < 0)
	359	bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
	360
d64d45cb GZ	361	/*
	362	* Due to some hardware design issues, we need to tune the formula.
	363	* Since i2c is open drain interface that allows the slave to
	364	* stall the transaction by holding the SCL line at '0', the RTL
	365	* implementation is waiting for SCL feedback from the pin after
	366	* setting it to High-Z ('1'). This wait adds to the high-time
	367	* interval counter few cycles of the input synchronization
	368	* (depending on the SCL_FILTER_REG field), and also the time it
	369	* takes for the board pull-up resistor to rise the SCL line.
	370	* For slow SCL settings these additions are negligible,
	371	* but they start to affect the speed when clock is set to faster
	372	* frequencies.
	373	* Through the actual tests, use the different user_div value(which
	374	* in the divider formular 'Fio / (Fi2c * user_div)') to adapt
	375	* the different ranges of i2c bus clock frequency, to make the SCL
	376	* more accurate.
	377	*/
	378	if (bitrate <= 30000)
979b907f	379	regval = ctrl_speed / (bitrate * 5);
d64d45cb GZ	380	else if (bitrate > 30000 && bitrate <= 280000)
	381	regval = (2 * ctrl_speed) / (bitrate * 11);
	382	else
	383	regval = ctrl_speed / (bitrate * 6);
979b907f ZS	384
	385	writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
	386	if (regval > 0xFF)
	387	writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
	388	else
	389	writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
	390
	391	err = i2c_add_numbered_adapter(adap);
	392	if (err < 0) {
	393	dev_err(&pdev->dev, "Can't add new i2c adapter\n");
	394	goto out;
	395	}
	396
	397	clk_disable(clk);
	398
	399	dev_info(&pdev->dev, " I2C adapter ready to operate\n");
	400
	401	return 0;
	402
	403	out:
	404	clk_disable(clk);
	405	err_clk_en:
	406	clk_unprepare(clk);
	407	err_clk_prep:
	408	clk_put(clk);
	409	err_get_clk:
	410	return err;
	411	}
	412
0b255e92	413	static int i2c_sirfsoc_remove(struct platform_device *pdev)
979b907f ZS	414	{
	415	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	416	struct sirfsoc_i2c *siic = adapter->algo_data;
	417
	418	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	419	i2c_del_adapter(adapter);
	420	clk_unprepare(siic->clk);
	421	clk_put(siic->clk);
	422	return 0;
	423	}
	424
	425	#ifdef CONFIG_PM
	426	static int i2c_sirfsoc_suspend(struct device *dev)
	427	{
	428	struct platform_device *pdev = to_platform_device(dev);
	429	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	430	struct sirfsoc_i2c *siic = adapter->algo_data;
	431
	432	clk_enable(siic->clk);
	433	siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
	434	siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
	435	clk_disable(siic->clk);
	436	return 0;
	437	}
	438
	439	static int i2c_sirfsoc_resume(struct device *dev)
	440	{
	441	struct platform_device *pdev = to_platform_device(dev);
	442	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	443	struct sirfsoc_i2c *siic = adapter->algo_data;
	444
	445	clk_enable(siic->clk);
	446	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
ebae7dfa ZS	447	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
ebae7dfa ZS	448	cpu_relax();
979b907f ZS	449	writel(SIRFSOC_I2C_CORE_EN \| SIRFSOC_I2C_MASTER_MODE,
	450	siic->base + SIRFSOC_I2C_CTRL);
	451	writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
	452	writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
	453	clk_disable(siic->clk);
	454	return 0;
	455	}
	456
	457	static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
	458	.suspend = i2c_sirfsoc_suspend,
	459	.resume = i2c_sirfsoc_resume,
	460	};
	461	#endif
	462
0b255e92	463	static const struct of_device_id sirfsoc_i2c_of_match[] = {
979b907f ZS	464	{ .compatible = "sirf,prima2-i2c", },
	465	{},
	466	};
	467	MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
	468
	469	static struct platform_driver i2c_sirfsoc_driver = {
	470	.driver = {
	471	.name = "sirfsoc_i2c",
979b907f ZS	472	#ifdef CONFIG_PM
	473	.pm = &i2c_sirfsoc_pm_ops,
	474	#endif
	475	.of_match_table = sirfsoc_i2c_of_match,
	476	},
	477	.probe = i2c_sirfsoc_probe,
0b255e92	478	.remove = i2c_sirfsoc_remove,
979b907f ZS	479	};
	480	module_platform_driver(i2c_sirfsoc_driver);
	481
	482	MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
	483	MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
	484	"Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
	485	MODULE_LICENSE("GPL v2");