[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-sirf.c

/*
 * I2C bus driver for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#define SIRFSOC_I2C_CLK_CTRL		0x00
#define SIRFSOC_I2C_STATUS		0x0C
#define SIRFSOC_I2C_CTRL		0x10
#define SIRFSOC_I2C_IO_CTRL		0x14
#define SIRFSOC_I2C_SDA_DELAY		0x18
#define SIRFSOC_I2C_CMD_START		0x1C
#define SIRFSOC_I2C_CMD_BUF		0x30
#define SIRFSOC_I2C_DATA_BUF		0x80

#define SIRFSOC_I2C_CMD_BUF_MAX		16
#define SIRFSOC_I2C_DATA_BUF_MAX	16

#define SIRFSOC_I2C_CMD(x)		(SIRFSOC_I2C_CMD_BUF + (x)*0x04)
#define SIRFSOC_I2C_DATA_MASK(x)        (0xFF<<(((x)&3)*8))
#define SIRFSOC_I2C_DATA_SHIFT(x)       (((x)&3)*8)

#define SIRFSOC_I2C_DIV_MASK		(0xFFFF)

/* I2C status flags */
#define SIRFSOC_I2C_STAT_BUSY		BIT(0)
#define SIRFSOC_I2C_STAT_TIP		BIT(1)
#define SIRFSOC_I2C_STAT_NACK		BIT(2)
#define SIRFSOC_I2C_STAT_TR_INT		BIT(4)
#define SIRFSOC_I2C_STAT_STOP		BIT(6)
#define SIRFSOC_I2C_STAT_CMD_DONE	BIT(8)
#define SIRFSOC_I2C_STAT_ERR		BIT(9)
#define SIRFSOC_I2C_CMD_INDEX		(0x1F<<16)

/* I2C control flags */
#define SIRFSOC_I2C_RESET		BIT(0)
#define SIRFSOC_I2C_CORE_EN		BIT(1)
#define SIRFSOC_I2C_MASTER_MODE		BIT(2)
#define SIRFSOC_I2C_CMD_DONE_EN		BIT(11)
#define SIRFSOC_I2C_ERR_INT_EN		BIT(12)

#define SIRFSOC_I2C_SDA_DELAY_MASK	(0xFF)
#define SIRFSOC_I2C_SCLF_FILTER		(3<<8)

#define SIRFSOC_I2C_START_CMD		BIT(0)

#define SIRFSOC_I2C_CMD_RP(x)		((x)&0x7)
#define SIRFSOC_I2C_NACK		BIT(3)
#define SIRFSOC_I2C_WRITE		BIT(4)
#define SIRFSOC_I2C_READ		BIT(5)
#define SIRFSOC_I2C_STOP		BIT(6)
#define SIRFSOC_I2C_START		BIT(7)

#define SIRFSOC_I2C_DEFAULT_SPEED 100000

struct sirfsoc_i2c {
	void __iomem *base;
	struct clk *clk;
	u32 cmd_ptr;		/* Current position in CMD buffer */
	u8 *buf;		/* Buffer passed by user */
	u32 msg_len;		/* Message length */
	u32 finished_len;	/* number of bytes read/written */
	u32 read_cmd_len;	/* number of read cmd sent */
	int msg_read;		/* 1 indicates a read message */
	int err_status;		/* 1 indicates an error on bus */

	u32 sda_delay;		/* For suspend/resume */
	u32 clk_div;
	int last;		/* Last message in transfer, STOP cmd can be sent */

	struct completion done;	/* indicates completion of message transfer */
	struct i2c_adapter adapter;
};

static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
{
	u32 data = 0;
	int i;

	for (i = 0; i < siic->read_cmd_len; i++) {
		if (!(i & 0x3))
			data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
		siic->buf[siic->finished_len++] =
			(u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
				SIRFSOC_I2C_DATA_SHIFT(i));
	}
}

static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
{
	u32 regval;
	int i = 0;

	if (siic->msg_read) {
		while (((siic->finished_len + i) < siic->msg_len)
				&& (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
			regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
			if (((siic->finished_len + i) ==
					(siic->msg_len - 1)) && siic->last)
				regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
			writel(regval,
				siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
			i++;
		}

		siic->read_cmd_len = i;
	} else {
		while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
				&& (siic->finished_len < siic->msg_len)) {
			regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
			if ((siic->finished_len == (siic->msg_len - 1))
				&& siic->last)
				regval |= SIRFSOC_I2C_STOP;
			writel(regval,
				siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
			writel(siic->buf[siic->finished_len++],
				siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
		}
	}
	siic->cmd_ptr = 0;

	/* Trigger the transfer */
	writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
}

static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
{
	struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
	u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);

	if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
		/* Error conditions */
		siic->err_status = 1;
		writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);

		if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
			dev_err(&siic->adapter.dev, "ACK not received\n");
		else
			dev_err(&siic->adapter.dev, "I2C error\n");

		complete(&siic->done);
	} else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
		/* CMD buffer execution complete */
		if (siic->msg_read)
			i2c_sirfsoc_read_data(siic);
		if (siic->finished_len == siic->msg_len)
			complete(&siic->done);
		else /* Fill a new CMD buffer for left data */
			i2c_sirfsoc_queue_cmd(siic);

		writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
	}

	return IRQ_HANDLED;
}

static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
	struct i2c_msg *msg)
{
	unsigned char addr;
	u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;

	/* no data and last message -> add STOP */
	if (siic->last && (msg->len == 0))
		regval |= SIRFSOC_I2C_STOP;

	writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));

	addr = msg->addr << 1;	/* Generate address */
	if (msg->flags & I2C_M_RD)
		addr |= 1;

	writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
}

static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
{
	u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
	/* timeout waiting for the xfer to finish or fail */
	int timeout = msecs_to_jiffies((msg->len + 1) * 50);
	int ret = 0;

	i2c_sirfsoc_set_address(siic, msg);

	writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
		siic->base + SIRFSOC_I2C_CTRL);
	i2c_sirfsoc_queue_cmd(siic);

	if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
		siic->err_status = 1;
		dev_err(&siic->adapter.dev, "Transfer timeout\n");
	}

	writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
		siic->base + SIRFSOC_I2C_CTRL);
	writel(0, siic->base + SIRFSOC_I2C_CMD_START);

	if (siic->err_status) {
		writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
			siic->base + SIRFSOC_I2C_CTRL);
		while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
			cpu_relax();

		ret = -EIO;
	}

	return ret;
}

static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
	int num)
{
	struct sirfsoc_i2c *siic = adap->algo_data;
	int i, ret;

	clk_enable(siic->clk);

	for (i = 0; i < num; i++) {
		siic->buf = msgs[i].buf;
		siic->msg_len = msgs[i].len;
		siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
		siic->err_status = 0;
		siic->cmd_ptr = 0;
		siic->finished_len = 0;
		siic->last = (i == (num - 1));

		ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
		if (ret) {
			clk_disable(siic->clk);
			return ret;
		}
	}

	clk_disable(siic->clk);
	return num;
}

/* I2C algorithms associated with this master controller driver */
static const struct i2c_algorithm i2c_sirfsoc_algo = {
	.master_xfer = i2c_sirfsoc_xfer,
	.functionality = i2c_sirfsoc_func,
};

static int i2c_sirfsoc_probe(struct platform_device *pdev)
{
	struct sirfsoc_i2c *siic;
	struct i2c_adapter *adap;
	struct resource *mem_res;
	struct clk *clk;
	int bitrate;
	int ctrl_speed;
	int irq;

	int err;
	u32 regval;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		err = PTR_ERR(clk);
		dev_err(&pdev->dev, "Clock get failed\n");
		goto err_get_clk;
	}

	err = clk_prepare(clk);
	if (err) {
		dev_err(&pdev->dev, "Clock prepare failed\n");
		goto err_clk_prep;
	}

	err = clk_enable(clk);
	if (err) {
		dev_err(&pdev->dev, "Clock enable failed\n");
		goto err_clk_en;
	}

	ctrl_speed = clk_get_rate(clk);

	siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
	if (!siic) {
		dev_err(&pdev->dev, "Can't allocate driver data\n");
		err = -ENOMEM;
		goto out;
	}
	adap = &siic->adapter;
	adap->class = I2C_CLASS_HWMON;

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (mem_res == NULL) {
		dev_err(&pdev->dev, "Unable to get MEM resource\n");
		err = -EINVAL;
		goto out;
	}

	siic->base = devm_request_and_ioremap(&pdev->dev, mem_res);
	if (siic->base == NULL) {
		dev_err(&pdev->dev, "IO remap failed!\n");
		err = -ENOMEM;
		goto out;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		err = irq;
		goto out;
	}
	err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
		dev_name(&pdev->dev), siic);
	if (err)
		goto out;

	adap->algo = &i2c_sirfsoc_algo;
	adap->algo_data = siic;

	adap->dev.parent = &pdev->dev;
	adap->nr = pdev->id;

	strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));

	platform_set_drvdata(pdev, adap);
	init_completion(&siic->done);

	/* Controller Initalisation */

	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
		cpu_relax();
	writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
		siic->base + SIRFSOC_I2C_CTRL);

	siic->clk = clk;

	err = of_property_read_u32(pdev->dev.of_node,
		"clock-frequency", &bitrate);
	if (err < 0)
		bitrate = SIRFSOC_I2C_DEFAULT_SPEED;

	if (bitrate < 100000)
		regval =
			(2 * ctrl_speed) / (2 * bitrate * 11);
	else
		regval = ctrl_speed / (bitrate * 5);

	writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
	if (regval > 0xFF)
		writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
	else
		writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);

	err = i2c_add_numbered_adapter(adap);
	if (err < 0) {
		dev_err(&pdev->dev, "Can't add new i2c adapter\n");
		goto out;
	}

	clk_disable(clk);

	dev_info(&pdev->dev, " I2C adapter ready to operate\n");

	return 0;

out:
	clk_disable(clk);
err_clk_en:
	clk_unprepare(clk);
err_clk_prep:
	clk_put(clk);
err_get_clk:
	return err;
}

static int i2c_sirfsoc_remove(struct platform_device *pdev)
{
	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	struct sirfsoc_i2c *siic = adapter->algo_data;

	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	i2c_del_adapter(adapter);
	clk_unprepare(siic->clk);
	clk_put(siic->clk);
	return 0;
}

#ifdef CONFIG_PM
static int i2c_sirfsoc_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	struct sirfsoc_i2c *siic = adapter->algo_data;

	clk_enable(siic->clk);
	siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
	siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
	clk_disable(siic->clk);
	return 0;
}

static int i2c_sirfsoc_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	struct sirfsoc_i2c *siic = adapter->algo_data;

	clk_enable(siic->clk);
	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
		siic->base + SIRFSOC_I2C_CTRL);
	writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
	writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
	clk_disable(siic->clk);
	return 0;
}

static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
	.suspend = i2c_sirfsoc_suspend,
	.resume = i2c_sirfsoc_resume,
};
#endif

static const struct of_device_id sirfsoc_i2c_of_match[] = {
	{ .compatible = "sirf,prima2-i2c", },
	{},
};
MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);

static struct platform_driver i2c_sirfsoc_driver = {
	.driver = {
		.name = "sirfsoc_i2c",
		.owner = THIS_MODULE,
#ifdef CONFIG_PM
		.pm = &i2c_sirfsoc_pm_ops,
#endif
		.of_match_table = sirfsoc_i2c_of_match,
	},
	.probe = i2c_sirfsoc_probe,
	.remove = i2c_sirfsoc_remove,
};
module_platform_driver(i2c_sirfsoc_driver);

MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
	"Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
979b907f ZS	1	/*
	2	* I2C bus driver for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/interrupt.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/slab.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/i2c.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18
	19	#define SIRFSOC_I2C_CLK_CTRL 0x00
	20	#define SIRFSOC_I2C_STATUS 0x0C
	21	#define SIRFSOC_I2C_CTRL 0x10
	22	#define SIRFSOC_I2C_IO_CTRL 0x14
	23	#define SIRFSOC_I2C_SDA_DELAY 0x18
	24	#define SIRFSOC_I2C_CMD_START 0x1C
	25	#define SIRFSOC_I2C_CMD_BUF 0x30
	26	#define SIRFSOC_I2C_DATA_BUF 0x80
	27
	28	#define SIRFSOC_I2C_CMD_BUF_MAX 16
	29	#define SIRFSOC_I2C_DATA_BUF_MAX 16
	30
	31	#define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
	32	#define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
	33	#define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
	34
	35	#define SIRFSOC_I2C_DIV_MASK (0xFFFF)
	36
	37	/* I2C status flags */
	38	#define SIRFSOC_I2C_STAT_BUSY BIT(0)
	39	#define SIRFSOC_I2C_STAT_TIP BIT(1)
	40	#define SIRFSOC_I2C_STAT_NACK BIT(2)
	41	#define SIRFSOC_I2C_STAT_TR_INT BIT(4)
	42	#define SIRFSOC_I2C_STAT_STOP BIT(6)
	43	#define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
	44	#define SIRFSOC_I2C_STAT_ERR BIT(9)
	45	#define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
	46
	47	/* I2C control flags */
	48	#define SIRFSOC_I2C_RESET BIT(0)
	49	#define SIRFSOC_I2C_CORE_EN BIT(1)
	50	#define SIRFSOC_I2C_MASTER_MODE BIT(2)
	51	#define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
	52	#define SIRFSOC_I2C_ERR_INT_EN BIT(12)
	53
	54	#define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
	55	#define SIRFSOC_I2C_SCLF_FILTER (3<<8)
	56
	57	#define SIRFSOC_I2C_START_CMD BIT(0)
	58
	59	#define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
	60	#define SIRFSOC_I2C_NACK BIT(3)
	61	#define SIRFSOC_I2C_WRITE BIT(4)
	62	#define SIRFSOC_I2C_READ BIT(5)
	63	#define SIRFSOC_I2C_STOP BIT(6)
	64	#define SIRFSOC_I2C_START BIT(7)
65
66	#define SIRFSOC_I2C_DEFAULT_SPEED 100000
67
68	struct sirfsoc_i2c {
69	void __iomem *base;
70	struct clk *clk;
71	u32 cmd_ptr; /* Current position in CMD buffer */
72	u8 buf; / Buffer passed by user */
73	u32 msg_len; /* Message length */
74	u32 finished_len; /* number of bytes read/written */
75	u32 read_cmd_len; /* number of read cmd sent */
76	int msg_read; /* 1 indicates a read message */
77	int err_status; /* 1 indicates an error on bus */
78
79	u32 sda_delay; /* For suspend/resume */
80	u32 clk_div;
81	int last; /* Last message in transfer, STOP cmd can be sent */
82
83	struct completion done; /* indicates completion of message transfer */
84	struct i2c_adapter adapter;
85	};
86
87	static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
88	{
89	u32 data = 0;
90	int i;
91
92	for (i = 0; i < siic->read_cmd_len; i++) {
93	if (!(i & 0x3))
94	data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
95	siic->buf[siic->finished_len++] =
96	(u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
97	SIRFSOC_I2C_DATA_SHIFT(i));
98	}
99	}
100
101	static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
102	{
103	u32 regval;
104	int i = 0;
105
106	if (siic->msg_read) {
107	while (((siic->finished_len + i) < siic->msg_len)
108	&& (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
109	regval = SIRFSOC_I2C_READ \| SIRFSOC_I2C_CMD_RP(0);
110	if (((siic->finished_len + i) ==
111	(siic->msg_len - 1)) && siic->last)
112	regval \|= SIRFSOC_I2C_STOP \| SIRFSOC_I2C_NACK;
113	writel(regval,
114	siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
115	i++;
116	}
117
118	siic->read_cmd_len = i;
119	} else {
120	while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
121	&& (siic->finished_len < siic->msg_len)) {
122	regval = SIRFSOC_I2C_WRITE \| SIRFSOC_I2C_CMD_RP(0);
123	if ((siic->finished_len == (siic->msg_len - 1))
124	&& siic->last)
125	regval \|= SIRFSOC_I2C_STOP;
126	writel(regval,
127	siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
128	writel(siic->buf[siic->finished_len++],
129	siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
130	}
131	}
132	siic->cmd_ptr = 0;
133
134	/* Trigger the transfer */
135	writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
136	}
137
138	static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
139	{
140	struct sirfsoc_i2c siic = (struct sirfsoc_i2c )dev_id;
141	u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
142
143	if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
144	/* Error conditions */
145	siic->err_status = 1;
146	writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
147
148	if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
149	dev_err(&siic->adapter.dev, "ACK not received\n");
150	else
151	dev_err(&siic->adapter.dev, "I2C error\n");
152
153	complete(&siic->done);
154	} else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
155	/* CMD buffer execution complete */
156	if (siic->msg_read)
157	i2c_sirfsoc_read_data(siic);
158	if (siic->finished_len == siic->msg_len)
159	complete(&siic->done);
160	else /* Fill a new CMD buffer for left data */
161	i2c_sirfsoc_queue_cmd(siic);
162
163	writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
164	}
165
166	return IRQ_HANDLED;
167	}
168
169	static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
170	struct i2c_msg *msg)
171	{
172	unsigned char addr;
173	u32 regval = SIRFSOC_I2C_START \| SIRFSOC_I2C_CMD_RP(0) \| SIRFSOC_I2C_WRITE;
174
175	/* no data and last message -> add STOP */
176	if (siic->last && (msg->len == 0))
177	regval \|= SIRFSOC_I2C_STOP;
178
179	writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
180
181	addr = msg->addr << 1; /* Generate address */
182	if (msg->flags & I2C_M_RD)
183	addr \|= 1;
184
185	writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
186	}
187
188	static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c siic, struct i2c_msg msg)
189	{
190	u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
191	/* timeout waiting for the xfer to finish or fail */
192	int timeout = msecs_to_jiffies((msg->len + 1) * 50);
193	int ret = 0;
194
195	i2c_sirfsoc_set_address(siic, msg);
196
197	writel(regval \| SIRFSOC_I2C_CMD_DONE_EN \| SIRFSOC_I2C_ERR_INT_EN,
198	siic->base + SIRFSOC_I2C_CTRL);
199	i2c_sirfsoc_queue_cmd(siic);
200
201	if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
202	siic->err_status = 1;
203	dev_err(&siic->adapter.dev, "Transfer timeout\n");
204	}
205
206	writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN \| SIRFSOC_I2C_ERR_INT_EN),
207	siic->base + SIRFSOC_I2C_CTRL);
208	writel(0, siic->base + SIRFSOC_I2C_CMD_START);
209
210	if (siic->err_status) {
211	writel(readl(siic->base + SIRFSOC_I2C_CTRL) \| SIRFSOC_I2C_RESET,
212	siic->base + SIRFSOC_I2C_CTRL);
213	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
214	cpu_relax();
215
216	ret = -EIO;
217	}
218
219	return ret;
220	}
221
222	static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
223	{
224	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
225	}
226
227	static int i2c_sirfsoc_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
228	int num)
229	{
230	struct sirfsoc_i2c *siic = adap->algo_data;
231	int i, ret;
232
233	clk_enable(siic->clk);
234
235	for (i = 0; i < num; i++) {
236	siic->buf = msgs[i].buf;
237	siic->msg_len = msgs[i].len;
238	siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
239	siic->err_status = 0;
240	siic->cmd_ptr = 0;
241	siic->finished_len = 0;
242	siic->last = (i == (num - 1));
243
244	ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
245	if (ret) {
246	clk_disable(siic->clk);
247	return ret;
248	}
249	}
250
251	clk_disable(siic->clk);
252	return num;
253	}
254
255	/* I2C algorithms associated with this master controller driver */
256	static const struct i2c_algorithm i2c_sirfsoc_algo = {
257	.master_xfer = i2c_sirfsoc_xfer,
258	.functionality = i2c_sirfsoc_func,
259	};
260
0b255e92	261	static int i2c_sirfsoc_probe(struct platform_device *pdev)
979b907f ZS	262	{
	263	struct sirfsoc_i2c *siic;
	264	struct i2c_adapter *adap;
	265	struct resource *mem_res;
	266	struct clk *clk;
	267	int bitrate;
	268	int ctrl_speed;
	269	int irq;
	270
	271	int err;
	272	u32 regval;
	273
	274	clk = clk_get(&pdev->dev, NULL);
	275	if (IS_ERR(clk)) {
	276	err = PTR_ERR(clk);
	277	dev_err(&pdev->dev, "Clock get failed\n");
	278	goto err_get_clk;
	279	}
	280
	281	err = clk_prepare(clk);
	282	if (err) {
	283	dev_err(&pdev->dev, "Clock prepare failed\n");
	284	goto err_clk_prep;
	285	}
	286
	287	err = clk_enable(clk);
	288	if (err) {
	289	dev_err(&pdev->dev, "Clock enable failed\n");
	290	goto err_clk_en;
	291	}
	292
	293	ctrl_speed = clk_get_rate(clk);
	294
	295	siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
	296	if (!siic) {
	297	dev_err(&pdev->dev, "Can't allocate driver data\n");
	298	err = -ENOMEM;
	299	goto out;
	300	}
	301	adap = &siic->adapter;
	302	adap->class = I2C_CLASS_HWMON;
	303
	304	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	305	if (mem_res == NULL) {
	306	dev_err(&pdev->dev, "Unable to get MEM resource\n");
	307	err = -EINVAL;
	308	goto out;
	309	}
	310
	311	siic->base = devm_request_and_ioremap(&pdev->dev, mem_res);
	312	if (siic->base == NULL) {
	313	dev_err(&pdev->dev, "IO remap failed!\n");
	314	err = -ENOMEM;
	315	goto out;
	316	}
	317
	318	irq = platform_get_irq(pdev, 0);
	319	if (irq < 0) {
	320	err = irq;
	321	goto out;
	322	}
	323	err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
	324	dev_name(&pdev->dev), siic);
	325	if (err)
326	goto out;
327
328	adap->algo = &i2c_sirfsoc_algo;
329	adap->algo_data = siic;
330
331	adap->dev.parent = &pdev->dev;
332	adap->nr = pdev->id;
333
334	strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
335
336	platform_set_drvdata(pdev, adap);
337	init_completion(&siic->done);
338
339	/* Controller Initalisation */
340
341	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
342	while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
343	cpu_relax();
344	writel(SIRFSOC_I2C_CORE_EN \| SIRFSOC_I2C_MASTER_MODE,
345	siic->base + SIRFSOC_I2C_CTRL);
346
347	siic->clk = clk;
348
349	err = of_property_read_u32(pdev->dev.of_node,
350	"clock-frequency", &bitrate);
351	if (err < 0)
352	bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
353
354	if (bitrate < 100000)
355	regval =
356	(2 * ctrl_speed) / (2 * bitrate * 11);
357	else
358	regval = ctrl_speed / (bitrate * 5);
359
360	writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
361	if (regval > 0xFF)
362	writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
363	else
364	writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
365
366	err = i2c_add_numbered_adapter(adap);
367	if (err < 0) {
368	dev_err(&pdev->dev, "Can't add new i2c adapter\n");
369	goto out;
370	}
371
372	clk_disable(clk);
373
374	dev_info(&pdev->dev, " I2C adapter ready to operate\n");
375
376	return 0;
377
378	out:
379	clk_disable(clk);
380	err_clk_en:
381	clk_unprepare(clk);
382	err_clk_prep:
383	clk_put(clk);
384	err_get_clk:
385	return err;
386	}
387
0b255e92	388	static int i2c_sirfsoc_remove(struct platform_device *pdev)
979b907f ZS	389	{
	390	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	391	struct sirfsoc_i2c *siic = adapter->algo_data;
	392
	393	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	394	i2c_del_adapter(adapter);
	395	clk_unprepare(siic->clk);
	396	clk_put(siic->clk);
	397	return 0;
	398	}
	399
	400	#ifdef CONFIG_PM
	401	static int i2c_sirfsoc_suspend(struct device *dev)
	402	{
	403	struct platform_device *pdev = to_platform_device(dev);
	404	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	405	struct sirfsoc_i2c *siic = adapter->algo_data;
	406
	407	clk_enable(siic->clk);
	408	siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
	409	siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
	410	clk_disable(siic->clk);
	411	return 0;
	412	}
	413
	414	static int i2c_sirfsoc_resume(struct device *dev)
	415	{
	416	struct platform_device *pdev = to_platform_device(dev);
	417	struct i2c_adapter *adapter = platform_get_drvdata(pdev);
	418	struct sirfsoc_i2c *siic = adapter->algo_data;
	419
	420	clk_enable(siic->clk);
	421	writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
	422	writel(SIRFSOC_I2C_CORE_EN \| SIRFSOC_I2C_MASTER_MODE,
	423	siic->base + SIRFSOC_I2C_CTRL);
	424	writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
	425	writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
	426	clk_disable(siic->clk);
	427	return 0;
	428	}
	429
	430	static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
	431	.suspend = i2c_sirfsoc_suspend,
	432	.resume = i2c_sirfsoc_resume,
	433	};
	434	#endif
	435
0b255e92	436	static const struct of_device_id sirfsoc_i2c_of_match[] = {
979b907f ZS	437	{ .compatible = "sirf,prima2-i2c", },
	438	{},
	439	};
	440	MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
	441
	442	static struct platform_driver i2c_sirfsoc_driver = {
	443	.driver = {
	444	.name = "sirfsoc_i2c",
	445	.owner = THIS_MODULE,
	446	#ifdef CONFIG_PM
	447	.pm = &i2c_sirfsoc_pm_ops,
	448	#endif
	449	.of_match_table = sirfsoc_i2c_of_match,
	450	},
	451	.probe = i2c_sirfsoc_probe,
0b255e92	452	.remove = i2c_sirfsoc_remove,
979b907f ZS	453	};
	454	module_platform_driver(i2c_sirfsoc_driver);
	455
	456	MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
	457	MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
	458	"Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
	459	MODULE_LICENSE("GPL v2");