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[mirror_ubuntu-hirsute-kernel.git] / drivers / i2c / busses / i2c-stm32f7.c
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9c41e452 1// SPDX-License-Identifier: GPL-2.0
aeb068c5
PYM		 2/*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
9c41e452 11 * Copyright (C) STMicroelectronics 2017
aeb068c5
PYM		 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
aeb068c5
PYM		 16 */
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/iopoll.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/reset.h>
31#include <linux/slab.h>
32
33#include "i2c-stm32.h"
34
35/* STM32F7 I2C registers */
36#define STM32F7_I2C_CR1 0x00
37#define STM32F7_I2C_CR2 0x04
38#define STM32F7_I2C_TIMINGR 0x10
39#define STM32F7_I2C_ISR 0x18
40#define STM32F7_I2C_ICR 0x1C
41#define STM32F7_I2C_RXDR 0x24
42#define STM32F7_I2C_TXDR 0x28
43
44/* STM32F7 I2C control 1 */
45#define STM32F7_I2C_CR1_ANFOFF BIT(12)
46#define STM32F7_I2C_CR1_ERRIE BIT(7)
47#define STM32F7_I2C_CR1_TCIE BIT(6)
48#define STM32F7_I2C_CR1_STOPIE BIT(5)
49#define STM32F7_I2C_CR1_NACKIE BIT(4)
50#define STM32F7_I2C_CR1_ADDRIE BIT(3)
51#define STM32F7_I2C_CR1_RXIE BIT(2)
52#define STM32F7_I2C_CR1_TXIE BIT(1)
53#define STM32F7_I2C_CR1_PE BIT(0)
54#define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
55 | STM32F7_I2C_CR1_TCIE \
56 | STM32F7_I2C_CR1_STOPIE \
57 | STM32F7_I2C_CR1_NACKIE \
58 | STM32F7_I2C_CR1_RXIE \
59 | STM32F7_I2C_CR1_TXIE)
60
61/* STM32F7 I2C control 2 */
62#define STM32F7_I2C_CR2_RELOAD BIT(24)
63#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
64#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
65#define STM32F7_I2C_CR2_NACK BIT(15)
66#define STM32F7_I2C_CR2_STOP BIT(14)
67#define STM32F7_I2C_CR2_START BIT(13)
68#define STM32F7_I2C_CR2_RD_WRN BIT(10)
69#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
70#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
71
72/* STM32F7 I2C Interrupt Status */
73#define STM32F7_I2C_ISR_BUSY BIT(15)
74#define STM32F7_I2C_ISR_ARLO BIT(9)
75#define STM32F7_I2C_ISR_BERR BIT(8)
76#define STM32F7_I2C_ISR_TCR BIT(7)
77#define STM32F7_I2C_ISR_TC BIT(6)
78#define STM32F7_I2C_ISR_STOPF BIT(5)
79#define STM32F7_I2C_ISR_NACKF BIT(4)
80#define STM32F7_I2C_ISR_RXNE BIT(2)
81#define STM32F7_I2C_ISR_TXIS BIT(1)
82
83/* STM32F7 I2C Interrupt Clear */
84#define STM32F7_I2C_ICR_ARLOCF BIT(9)
85#define STM32F7_I2C_ICR_BERRCF BIT(8)
86#define STM32F7_I2C_ICR_STOPCF BIT(5)
87#define STM32F7_I2C_ICR_NACKCF BIT(4)
88
89/* STM32F7 I2C Timing */
90#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
91#define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
92#define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
93#define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
94#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
95
96#define STM32F7_I2C_MAX_LEN 0xff
97
98#define STM32F7_I2C_DNF_DEFAULT 0
99#define STM32F7_I2C_DNF_MAX 16
100
101#define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
102#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
103#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
104
105#define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
106#define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
107
108#define STM32F7_PRESC_MAX BIT(4)
109#define STM32F7_SCLDEL_MAX BIT(4)
110#define STM32F7_SDADEL_MAX BIT(4)
111#define STM32F7_SCLH_MAX BIT(8)
112#define STM32F7_SCLL_MAX BIT(8)
113
114/**
115 * struct stm32f7_i2c_spec - private i2c specification timing
116 * @rate: I2C bus speed (Hz)
117 * @rate_min: 80% of I2C bus speed (Hz)
118 * @rate_max: 100% of I2C bus speed (Hz)
119 * @fall_max: Max fall time of both SDA and SCL signals (ns)
120 * @rise_max: Max rise time of both SDA and SCL signals (ns)
121 * @hddat_min: Min data hold time (ns)
122 * @vddat_max: Max data valid time (ns)
123 * @sudat_min: Min data setup time (ns)
124 * @l_min: Min low period of the SCL clock (ns)
125 * @h_min: Min high period of the SCL clock (ns)
126 */
127struct stm32f7_i2c_spec {
128 u32 rate;
129 u32 rate_min;
130 u32 rate_max;
131 u32 fall_max;
132 u32 rise_max;
133 u32 hddat_min;
134 u32 vddat_max;
135 u32 sudat_min;
136 u32 l_min;
137 u32 h_min;
138};
139
140/**
141 * struct stm32f7_i2c_setup - private I2C timing setup parameters
142 * @speed: I2C speed mode (standard, Fast Plus)
143 * @speed_freq: I2C speed frequency (Hz)
144 * @clock_src: I2C clock source frequency (Hz)
145 * @rise_time: Rise time (ns)
146 * @fall_time: Fall time (ns)
147 * @dnf: Digital filter coefficient (0-16)
148 * @analog_filter: Analog filter delay (On/Off)
149 */
150struct stm32f7_i2c_setup {
151 enum stm32_i2c_speed speed;
152 u32 speed_freq;
153 u32 clock_src;
154 u32 rise_time;
155 u32 fall_time;
156 u8 dnf;
157 bool analog_filter;
158};
159
160/**
161 * struct stm32f7_i2c_timings - private I2C output parameters
162 * @prec: Prescaler value
163 * @scldel: Data setup time
164 * @sdadel: Data hold time
165 * @sclh: SCL high period (master mode)
166 * @sclh: SCL low period (master mode)
167 */
168struct stm32f7_i2c_timings {
169 struct list_head node;
170 u8 presc;
171 u8 scldel;
172 u8 sdadel;
173 u8 sclh;
174 u8 scll;
175};
176
177/**
178 * struct stm32f7_i2c_msg - client specific data
179 * @addr: 8-bit slave addr, including r/w bit
180 * @count: number of bytes to be transferred
181 * @buf: data buffer
182 * @result: result of the transfer
183 * @stop: last I2C msg to be sent, i.e. STOP to be generated
184 */
185struct stm32f7_i2c_msg {
186 u8 addr;
187 u32 count;
188 u8 *buf;
189 int result;
190 bool stop;
191};
192
193/**
194 * struct stm32f7_i2c_dev - private data of the controller
195 * @adap: I2C adapter for this controller
196 * @dev: device for this controller
197 * @base: virtual memory area
198 * @complete: completion of I2C message
199 * @clk: hw i2c clock
200 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
201 * @msg: Pointer to data to be written
202 * @msg_num: number of I2C messages to be executed
203 * @msg_id: message identifiant
204 * @f7_msg: customized i2c msg for driver usage
205 * @setup: I2C timing input setup
206 * @timing: I2C computed timings
207 */
208struct stm32f7_i2c_dev {
209 struct i2c_adapter adap;
210 struct device *dev;
211 void __iomem *base;
212 struct completion complete;
213 struct clk *clk;
214 int speed;
215 struct i2c_msg *msg;
216 unsigned int msg_num;
217 unsigned int msg_id;
218 struct stm32f7_i2c_msg f7_msg;
463a9215 219 struct stm32f7_i2c_setup setup;
aeb068c5
PYM		 220 struct stm32f7_i2c_timings timing;
221};
222
223/**
224 * All these values are coming from I2C Specification, Version 6.0, 4th of
225 * April 2014.
226 *
227 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
228 * and Fast-mode Plus I2C-bus devices
229 */
230static struct stm32f7_i2c_spec i2c_specs[] = {
231 [STM32_I2C_SPEED_STANDARD] = {
232 .rate = 100000,
233 .rate_min = 80000,
234 .rate_max = 100000,
235 .fall_max = 300,
236 .rise_max = 1000,
237 .hddat_min = 0,
238 .vddat_max = 3450,
239 .sudat_min = 250,
240 .l_min = 4700,
241 .h_min = 4000,
242 },
243 [STM32_I2C_SPEED_FAST] = {
244 .rate = 400000,
245 .rate_min = 320000,
246 .rate_max = 400000,
247 .fall_max = 300,
248 .rise_max = 300,
249 .hddat_min = 0,
250 .vddat_max = 900,
251 .sudat_min = 100,
252 .l_min = 1300,
253 .h_min = 600,
254 },
255 [STM32_I2C_SPEED_FAST_PLUS] = {
256 .rate = 1000000,
257 .rate_min = 800000,
258 .rate_max = 1000000,
259 .fall_max = 100,
260 .rise_max = 120,
261 .hddat_min = 0,
262 .vddat_max = 450,
263 .sudat_min = 50,
264 .l_min = 500,
265 .h_min = 260,
266 },
267};
268
25f2f440 269static const struct stm32f7_i2c_setup stm32f7_setup = {
aeb068c5
PYM		 270 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
271 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
272 .dnf = STM32F7_I2C_DNF_DEFAULT,
273 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
274};
275
276static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
277{
278 writel_relaxed(readl_relaxed(reg) | mask, reg);
279}
280
281static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
282{
283 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
284}
285
286static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
287 struct stm32f7_i2c_setup *setup,
288 struct stm32f7_i2c_timings *output)
289{
290 u32 p_prev = STM32F7_PRESC_MAX;
291 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
292 setup->clock_src);
293 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
294 setup->speed_freq);
295 u32 clk_error_prev = i2cbus;
296 u32 tsync;
297 u32 af_delay_min, af_delay_max;
298 u32 dnf_delay;
299 u32 clk_min, clk_max;
300 int sdadel_min, sdadel_max;
301 int scldel_min;
302 struct stm32f7_i2c_timings *v, *_v, *s;
303 struct list_head solutions;
304 u16 p, l, a, h;
305 int ret = 0;
306
307 if (setup->speed >= STM32_I2C_SPEED_END) {
308 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
309 setup->speed, STM32_I2C_SPEED_END - 1);
310 return -EINVAL;
311 }
312
313 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
314 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
315 dev_err(i2c_dev->dev,
316 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
317 setup->rise_time, i2c_specs[setup->speed].rise_max,
318 setup->fall_time, i2c_specs[setup->speed].fall_max);
319 return -EINVAL;
320 }
321
322 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
323 dev_err(i2c_dev->dev,
324 "DNF out of bound %d/%d\n",
325 setup->dnf, STM32F7_I2C_DNF_MAX);
326 return -EINVAL;
327 }
328
329 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
330 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
331 setup->speed_freq, i2c_specs[setup->speed].rate);
332 return -EINVAL;
333 }
334
335 /* Analog and Digital Filters */
336 af_delay_min =
337 (setup->analog_filter ?
338 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
339 af_delay_max =
340 (setup->analog_filter ?
341 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
342 dnf_delay = setup->dnf * i2cclk;
343
344 sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
345 af_delay_min - (setup->dnf + 3) * i2cclk;
346
347 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
348 af_delay_max - (setup->dnf + 4) * i2cclk;
349
350 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
351
352 if (sdadel_min < 0)
353 sdadel_min = 0;
354 if (sdadel_max < 0)
355 sdadel_max = 0;
356
357 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
358 sdadel_min, sdadel_max, scldel_min);
359
360 INIT_LIST_HEAD(&solutions);
361 /* Compute possible values for PRESC, SCLDEL and SDADEL */
362 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
363 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
364 u32 scldel = (l + 1) * (p + 1) * i2cclk;
365
366 if (scldel < scldel_min)
367 continue;
368
369 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
370 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
371
372 if (((sdadel >= sdadel_min) &&
373 (sdadel <= sdadel_max)) &&
374 (p != p_prev)) {
375 v = kmalloc(sizeof(*v), GFP_KERNEL);
376 if (!v) {
377 ret = -ENOMEM;
378 goto exit;
379 }
380
381 v->presc = p;
382 v->scldel = l;
383 v->sdadel = a;
384 p_prev = p;
385
386 list_add_tail(&v->node,
387 &solutions);
388 }
389 }
390 }
391 }
392
393 if (list_empty(&solutions)) {
394 dev_err(i2c_dev->dev, "no Prescaler solution\n");
395 ret = -EPERM;
396 goto exit;
397 }
398
399 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
400 s = NULL;
401 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
402 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
403
404 /*
405 * Among Prescaler possibilities discovered above figures out SCL Low
406 * and High Period. Provided:
407 * - SCL Low Period has to be higher than SCL Clock Low Period
408 * defined by I2C Specification. I2C Clock has to be lower than
409 * (SCL Low Period - Analog/Digital filters) / 4.
410 * - SCL High Period has to be lower than SCL Clock High Period
411 * defined by I2C Specification
412 * - I2C Clock has to be lower than SCL High Period
413 */
414 list_for_each_entry(v, &solutions, node) {
415 u32 prescaler = (v->presc + 1) * i2cclk;
416
417 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
418 u32 tscl_l = (l + 1) * prescaler + tsync;
419
420 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
421 (i2cclk >=
422 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
423 continue;
424 }
425
426 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
427 u32 tscl_h = (h + 1) * prescaler + tsync;
428 u32 tscl = tscl_l + tscl_h +
429 setup->rise_time + setup->fall_time;
430
431 if ((tscl >= clk_min) && (tscl <= clk_max) &&
432 (tscl_h >= i2c_specs[setup->speed].h_min) &&
433 (i2cclk < tscl_h)) {
434 int clk_error = tscl - i2cbus;
435
436 if (clk_error < 0)
437 clk_error = -clk_error;
438
439 if (clk_error < clk_error_prev) {
440 clk_error_prev = clk_error;
441 v->scll = l;
442 v->sclh = h;
443 s = v;
444 }
445 }
446 }
447 }
448 }
449
450 if (!s) {
451 dev_err(i2c_dev->dev, "no solution at all\n");
452 ret = -EPERM;
453 goto exit;
454 }
455
456 output->presc = s->presc;
457 output->scldel = s->scldel;
458 output->sdadel = s->sdadel;
459 output->scll = s->scll;
460 output->sclh = s->sclh;
461
462 dev_dbg(i2c_dev->dev,
463 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
464 output->presc,
465 output->scldel, output->sdadel,
466 output->scll, output->sclh);
467
468exit:
469 /* Release list and memory */
470 list_for_each_entry_safe(v, _v, &solutions, node) {
471 list_del(&v->node);
472 kfree(v);
473 }
474
475 return ret;
476}
477
478static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
479 struct stm32f7_i2c_setup *setup)
480{
481 int ret = 0;
482
483 setup->speed = i2c_dev->speed;
484 setup->speed_freq = i2c_specs[setup->speed].rate;
485 setup->clock_src = clk_get_rate(i2c_dev->clk);
486
487 if (!setup->clock_src) {
488 dev_err(i2c_dev->dev, "clock rate is 0\n");
489 return -EINVAL;
490 }
491
492 do {
493 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
494 &i2c_dev->timing);
495 if (ret) {
496 dev_err(i2c_dev->dev,
497 "failed to compute I2C timings.\n");
498 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
499 i2c_dev->speed--;
500 setup->speed = i2c_dev->speed;
501 setup->speed_freq =
502 i2c_specs[setup->speed].rate;
503 dev_warn(i2c_dev->dev,
504 "downgrade I2C Speed Freq to (%i)\n",
505 i2c_specs[setup->speed].rate);
506 } else {
507 break;
508 }
509 }
510 } while (ret);
511
512 if (ret) {
513 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
514 return ret;
515 }
516
517 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
518 setup->speed, setup->speed_freq, setup->clock_src);
519 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
520 setup->rise_time, setup->fall_time);
521 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
522 (setup->analog_filter ? "On" : "Off"), setup->dnf);
523
524 return 0;
525}
526
527static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
528{
529 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
530 u32 timing = 0;
531
532 /* Timing settings */
533 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
534 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
535 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
536 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
537 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
538 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
539
540 /* Enable I2C */
463a9215 541 if (i2c_dev->setup.analog_filter)
aeb068c5
PYM		 542 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
543 STM32F7_I2C_CR1_ANFOFF);
544 else
545 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
546 STM32F7_I2C_CR1_ANFOFF);
547 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
548 STM32F7_I2C_CR1_PE);
549}
550
551static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
552{
553 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
554 void __iomem *base = i2c_dev->base;
555
556 if (f7_msg->count) {
557 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
558 f7_msg->count--;
559 }
560}
561
562static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
563{
564 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
565 void __iomem *base = i2c_dev->base;
566
567 if (f7_msg->count) {
568 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
569 f7_msg->count--;
570 }
571}
572
573static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
574{
575 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
576 u32 cr2;
577
578 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
579
580 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
581 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
582 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
583 } else {
584 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
585 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
586 }
587
588 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
589}
590
591static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
592{
593 u32 status;
594 int ret;
595
596 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
597 status,
598 !(status & STM32F7_I2C_ISR_BUSY),
599 10, 1000);
600 if (ret) {
601 dev_dbg(i2c_dev->dev, "bus busy\n");
602 ret = -EBUSY;
603 }
604
605 return ret;
606}
607
608static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
609 struct i2c_msg *msg)
610{
611 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
612 void __iomem *base = i2c_dev->base;
613 u32 cr1, cr2;
614
615 f7_msg->addr = msg->addr;
616 f7_msg->buf = msg->buf;
617 f7_msg->count = msg->len;
618 f7_msg->result = 0;
619 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
620
621 reinit_completion(&i2c_dev->complete);
622
623 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
624 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
625
626 /* Set transfer direction */
627 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
628 if (msg->flags & I2C_M_RD)
629 cr2 |= STM32F7_I2C_CR2_RD_WRN;
630
631 /* Set slave address */
632 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
633 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
634
635 /* Set nb bytes to transfer and reload if needed */
636 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
637 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
638 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
639 cr2 |= STM32F7_I2C_CR2_RELOAD;
640 } else {
641 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
642 }
643
644 /* Enable NACK, STOP, error and transfer complete interrupts */
645 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
646 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
647
648 /* Clear TX/RX interrupt */
649 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
650
651 /* Enable RX/TX interrupt according to msg direction */
652 if (msg->flags & I2C_M_RD)
653 cr1 |= STM32F7_I2C_CR1_RXIE;
654 else
655 cr1 |= STM32F7_I2C_CR1_TXIE;
656
657 /* Configure Start/Repeated Start */
658 cr2 |= STM32F7_I2C_CR2_START;
659
660 /* Write configurations registers */
661 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
662 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
663}
664
665static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
666{
667 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
668}
669
670static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
671{
672 struct stm32f7_i2c_dev *i2c_dev = data;
673 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
674 void __iomem *base = i2c_dev->base;
675 u32 status, mask;
676
677 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
678
679 /* Tx empty */
680 if (status & STM32F7_I2C_ISR_TXIS)
681 stm32f7_i2c_write_tx_data(i2c_dev);
682
683 /* RX not empty */
684 if (status & STM32F7_I2C_ISR_RXNE)
685 stm32f7_i2c_read_rx_data(i2c_dev);
686
687 /* NACK received */
688 if (status & STM32F7_I2C_ISR_NACKF) {
689 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
690 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
691 f7_msg->result = -ENXIO;
692 }
693
694 /* STOP detection flag */
695 if (status & STM32F7_I2C_ISR_STOPF) {
696 /* Disable interrupts */
697 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
698
699 /* Clear STOP flag */
700 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
701
702 complete(&i2c_dev->complete);
703 }
704
705 /* Transfer complete */
706 if (status & STM32F7_I2C_ISR_TC) {
707 if (f7_msg->stop) {
708 mask = STM32F7_I2C_CR2_STOP;
709 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
710 } else {
711 i2c_dev->msg_id++;
712 i2c_dev->msg++;
713 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
714 }
715 }
716
717 /*
718 * Transfer Complete Reload: 255 data bytes have been transferred
719 * We have to prepare the I2C controller to transfer the remaining
720 * data.
721 */
722 if (status & STM32F7_I2C_ISR_TCR)
723 stm32f7_i2c_reload(i2c_dev);
724
725 return IRQ_HANDLED;
726}
727
728static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
729{
730 struct stm32f7_i2c_dev *i2c_dev = data;
731 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
732 void __iomem *base = i2c_dev->base;
733 struct device *dev = i2c_dev->dev;
734 u32 status;
735
736 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
737
738 /* Bus error */
739 if (status & STM32F7_I2C_ISR_BERR) {
740 dev_err(dev, "<%s>: Bus error\n", __func__);
741 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
742 f7_msg->result = -EIO;
743 }
744
745 /* Arbitration loss */
746 if (status & STM32F7_I2C_ISR_ARLO) {
747 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
748 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
749 f7_msg->result = -EAGAIN;
750 }
751
752 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
753
754 complete(&i2c_dev->complete);
755
756 return IRQ_HANDLED;
757}
758
759static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
760 struct i2c_msg msgs[], int num)
761{
762 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
763 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
764 unsigned long time_left;
765 int ret;
766
767 i2c_dev->msg = msgs;
768 i2c_dev->msg_num = num;
769 i2c_dev->msg_id = 0;
770
771 ret = clk_enable(i2c_dev->clk);
772 if (ret) {
773 dev_err(i2c_dev->dev, "Failed to enable clock\n");
774 return ret;
775 }
776
777 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
778 if (ret)
779 goto clk_free;
780
781 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
782
783 time_left = wait_for_completion_timeout(&i2c_dev->complete,
784 i2c_dev->adap.timeout);
785 ret = f7_msg->result;
786
787 if (!time_left) {
788 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
789 i2c_dev->msg->addr);
790 ret = -ETIMEDOUT;
791 }
792
793clk_free:
794 clk_disable(i2c_dev->clk);
795
796 return (ret < 0) ? ret : num;
797}
798
799static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
800{
801 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
802}
803
804static struct i2c_algorithm stm32f7_i2c_algo = {
805 .master_xfer = stm32f7_i2c_xfer,
806 .functionality = stm32f7_i2c_func,
807};
808
809static int stm32f7_i2c_probe(struct platform_device *pdev)
810{
811 struct device_node *np = pdev->dev.of_node;
812 struct stm32f7_i2c_dev *i2c_dev;
813 const struct stm32f7_i2c_setup *setup;
814 struct resource *res;
815 u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
816 struct i2c_adapter *adap;
817 struct reset_control *rst;
818 int ret;
819
820 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
821 if (!i2c_dev)
822 return -ENOMEM;
823
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
826 if (IS_ERR(i2c_dev->base))
827 return PTR_ERR(i2c_dev->base);
828
829 irq_event = irq_of_parse_and_map(np, 0);
830 if (!irq_event) {
831 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
832 return -EINVAL;
833 }
834
835 irq_error = irq_of_parse_and_map(np, 1);
836 if (!irq_error) {
837 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
838 return -EINVAL;
839 }
840
841 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
842 if (IS_ERR(i2c_dev->clk)) {
843 dev_err(&pdev->dev, "Error: Missing controller clock\n");
844 return PTR_ERR(i2c_dev->clk);
845 }
846 ret = clk_prepare_enable(i2c_dev->clk);
847 if (ret) {
848 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
849 return ret;
850 }
851
852 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
853 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
854 &clk_rate);
855 if (!ret && clk_rate >= 1000000)
856 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
857 else if (!ret && clk_rate >= 400000)
858 i2c_dev->speed = STM32_I2C_SPEED_FAST;
859 else if (!ret && clk_rate >= 100000)
860 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
861
862 rst = devm_reset_control_get(&pdev->dev, NULL);
863 if (IS_ERR(rst)) {
864 dev_err(&pdev->dev, "Error: Missing controller reset\n");
865 ret = PTR_ERR(rst);
866 goto clk_free;
867 }
868 reset_control_assert(rst);
869 udelay(2);
870 reset_control_deassert(rst);
871
872 i2c_dev->dev = &pdev->dev;
873
874 ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0,
875 pdev->name, i2c_dev);
876 if (ret) {
877 dev_err(&pdev->dev, "Failed to request irq event %i\n",
878 irq_event);
879 goto clk_free;
880 }
881
882 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
883 pdev->name, i2c_dev);
884 if (ret) {
885 dev_err(&pdev->dev, "Failed to request irq error %i\n",
886 irq_error);
887 goto clk_free;
888 }
889
890 setup = of_device_get_match_data(&pdev->dev);
463a9215 891 i2c_dev->setup = *setup;
aeb068c5
PYM		 892
893 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
894 &rise_time);
895 if (!ret)
463a9215 896 i2c_dev->setup.rise_time = rise_time;
aeb068c5
PYM		 897
898 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
899 &fall_time);
900 if (!ret)
463a9215 901 i2c_dev->setup.fall_time = fall_time;
aeb068c5 902
463a9215 903 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
aeb068c5
PYM		 904 if (ret)
905 goto clk_free;
906
907 stm32f7_i2c_hw_config(i2c_dev);
908
909 adap = &i2c_dev->adap;
910 i2c_set_adapdata(adap, i2c_dev);
911 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
912 &res->start);
913 adap->owner = THIS_MODULE;
914 adap->timeout = 2 * HZ;
915 adap->retries = 3;
916 adap->algo = &stm32f7_i2c_algo;
917 adap->dev.parent = &pdev->dev;
918 adap->dev.of_node = pdev->dev.of_node;
919
920 init_completion(&i2c_dev->complete);
921
922 ret = i2c_add_adapter(adap);
923 if (ret)
924 goto clk_free;
925
926 platform_set_drvdata(pdev, i2c_dev);
927
928 clk_disable(i2c_dev->clk);
929
930 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
931
932 return 0;
933
934clk_free:
935 clk_disable_unprepare(i2c_dev->clk);
936
937 return ret;
938}
939
940static int stm32f7_i2c_remove(struct platform_device *pdev)
941{
942 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
943
944 i2c_del_adapter(&i2c_dev->adap);
945
946 clk_unprepare(i2c_dev->clk);
947
948 return 0;
949}
950
951static const struct of_device_id stm32f7_i2c_match[] = {
952 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
953 {},
954};
955MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
956
957static struct platform_driver stm32f7_i2c_driver = {
958 .driver = {
959 .name = "stm32f7-i2c",
960 .of_match_table = stm32f7_i2c_match,
961 },
962 .probe = stm32f7_i2c_probe,
963 .remove = stm32f7_i2c_remove,
964};
965
966module_platform_driver(stm32f7_i2c_driver);
967
968MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
969MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
970MODULE_LICENSE("GPL v2");
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