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db811ca0 CC |
1 | /* |
2 | * drivers/i2c/busses/i2c-tegra.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * Author: Colin Cross <ccross@android.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/slab.h> | |
6ad068ed | 28 | #include <linux/of_device.h> |
93cf5d75 | 29 | #include <linux/module.h> |
dda9d6a8 | 30 | #include <linux/reset.h> |
db811ca0 CC |
31 | |
32 | #include <asm/unaligned.h> | |
33 | ||
db811ca0 CC |
34 | #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
35 | #define BYTES_PER_FIFO_WORD 4 | |
36 | ||
37 | #define I2C_CNFG 0x000 | |
40abcf77 | 38 | #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 |
db811ca0 CC |
39 | #define I2C_CNFG_PACKET_MODE_EN (1<<10) |
40 | #define I2C_CNFG_NEW_MASTER_FSM (1<<11) | |
cb63c62d | 41 | #define I2C_STATUS 0x01C |
db811ca0 | 42 | #define I2C_SL_CNFG 0x020 |
5afa9d35 | 43 | #define I2C_SL_CNFG_NACK (1<<1) |
db811ca0 CC |
44 | #define I2C_SL_CNFG_NEWSL (1<<2) |
45 | #define I2C_SL_ADDR1 0x02c | |
5afa9d35 | 46 | #define I2C_SL_ADDR2 0x030 |
db811ca0 CC |
47 | #define I2C_TX_FIFO 0x050 |
48 | #define I2C_RX_FIFO 0x054 | |
49 | #define I2C_PACKET_TRANSFER_STATUS 0x058 | |
50 | #define I2C_FIFO_CONTROL 0x05c | |
51 | #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) | |
52 | #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) | |
53 | #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 | |
54 | #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 | |
55 | #define I2C_FIFO_STATUS 0x060 | |
56 | #define I2C_FIFO_STATUS_TX_MASK 0xF0 | |
57 | #define I2C_FIFO_STATUS_TX_SHIFT 4 | |
58 | #define I2C_FIFO_STATUS_RX_MASK 0x0F | |
59 | #define I2C_FIFO_STATUS_RX_SHIFT 0 | |
60 | #define I2C_INT_MASK 0x064 | |
61 | #define I2C_INT_STATUS 0x068 | |
62 | #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) | |
63 | #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) | |
64 | #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) | |
65 | #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) | |
66 | #define I2C_INT_NO_ACK (1<<3) | |
67 | #define I2C_INT_ARBITRATION_LOST (1<<2) | |
68 | #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) | |
69 | #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) | |
70 | #define I2C_CLK_DIVISOR 0x06c | |
2a2897ba LD |
71 | #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 |
72 | #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 | |
db811ca0 CC |
73 | |
74 | #define DVC_CTRL_REG1 0x000 | |
75 | #define DVC_CTRL_REG1_INTR_EN (1<<10) | |
76 | #define DVC_CTRL_REG2 0x004 | |
77 | #define DVC_CTRL_REG3 0x008 | |
78 | #define DVC_CTRL_REG3_SW_PROG (1<<26) | |
79 | #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) | |
80 | #define DVC_STATUS 0x00c | |
81 | #define DVC_STATUS_I2C_DONE_INTR (1<<30) | |
82 | ||
83 | #define I2C_ERR_NONE 0x00 | |
84 | #define I2C_ERR_NO_ACK 0x01 | |
85 | #define I2C_ERR_ARBITRATION_LOST 0x02 | |
cb63c62d | 86 | #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 |
db811ca0 CC |
87 | |
88 | #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 | |
89 | #define PACKET_HEADER0_PACKET_ID_SHIFT 16 | |
90 | #define PACKET_HEADER0_CONT_ID_SHIFT 12 | |
91 | #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) | |
92 | ||
93 | #define I2C_HEADER_HIGHSPEED_MODE (1<<22) | |
94 | #define I2C_HEADER_CONT_ON_NAK (1<<21) | |
95 | #define I2C_HEADER_SEND_START_BYTE (1<<20) | |
96 | #define I2C_HEADER_READ (1<<19) | |
97 | #define I2C_HEADER_10BIT_ADDR (1<<18) | |
98 | #define I2C_HEADER_IE_ENABLE (1<<17) | |
99 | #define I2C_HEADER_REPEAT_START (1<<16) | |
c8f5af2f | 100 | #define I2C_HEADER_CONTINUE_XFER (1<<15) |
db811ca0 CC |
101 | #define I2C_HEADER_MASTER_ADDR_SHIFT 12 |
102 | #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 | |
6f4664b2 LD |
103 | |
104 | #define I2C_CONFIG_LOAD 0x08C | |
105 | #define I2C_MSTR_CONFIG_LOAD (1 << 0) | |
106 | #define I2C_SLV_CONFIG_LOAD (1 << 1) | |
107 | #define I2C_TIMEOUT_CONFIG_LOAD (1 << 2) | |
108 | ||
c8f5af2f LD |
109 | /* |
110 | * msg_end_type: The bus control which need to be send at end of transfer. | |
111 | * @MSG_END_STOP: Send stop pulse at end of transfer. | |
112 | * @MSG_END_REPEAT_START: Send repeat start at end of transfer. | |
113 | * @MSG_END_CONTINUE: The following on message is coming and so do not send | |
114 | * stop or repeat start. | |
115 | */ | |
116 | enum msg_end_type { | |
117 | MSG_END_STOP, | |
118 | MSG_END_REPEAT_START, | |
119 | MSG_END_CONTINUE, | |
120 | }; | |
db811ca0 | 121 | |
6ad068ed LD |
122 | /** |
123 | * struct tegra_i2c_hw_feature : Different HW support on Tegra | |
124 | * @has_continue_xfer_support: Continue transfer supports. | |
2a2897ba LD |
125 | * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer |
126 | * complete interrupt per packet basis. | |
127 | * @has_single_clk_source: The i2c controller has single clock source. Tegra30 | |
128 | * and earlier Socs has two clock sources i.e. div-clk and | |
129 | * fast-clk. | |
6f4664b2 LD |
130 | * @has_config_load_reg: Has the config load register to load the new |
131 | * configuration. | |
2a2897ba LD |
132 | * @clk_divisor_hs_mode: Clock divisor in HS mode. |
133 | * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is | |
134 | * applicable if there is no fast clock source i.e. single clock | |
135 | * source. | |
6ad068ed LD |
136 | */ |
137 | ||
138 | struct tegra_i2c_hw_feature { | |
139 | bool has_continue_xfer_support; | |
2a2897ba LD |
140 | bool has_per_pkt_xfer_complete_irq; |
141 | bool has_single_clk_source; | |
6f4664b2 | 142 | bool has_config_load_reg; |
2a2897ba LD |
143 | int clk_divisor_hs_mode; |
144 | int clk_divisor_std_fast_mode; | |
d57f5ded | 145 | u16 clk_divisor_fast_plus_mode; |
6ad068ed LD |
146 | }; |
147 | ||
db811ca0 CC |
148 | /** |
149 | * struct tegra_i2c_dev - per device i2c context | |
150 | * @dev: device reference for power management | |
6ad068ed | 151 | * @hw: Tegra i2c hw feature. |
db811ca0 | 152 | * @adapter: core i2c layer adapter information |
14e92bd4 LD |
153 | * @div_clk: clock reference for div clock of i2c controller. |
154 | * @fast_clk: clock reference for fast clock of i2c controller. | |
db811ca0 CC |
155 | * @base: ioremapped registers cookie |
156 | * @cont_id: i2c controller id, used for for packet header | |
157 | * @irq: irq number of transfer complete interrupt | |
158 | * @is_dvc: identifies the DVC i2c controller, has a different register layout | |
159 | * @msg_complete: transfer completion notifier | |
160 | * @msg_err: error code for completed message | |
161 | * @msg_buf: pointer to current message data | |
162 | * @msg_buf_remaining: size of unsent data in the message buffer | |
163 | * @msg_read: identifies read transfers | |
164 | * @bus_clk_rate: current i2c bus clock rate | |
165 | * @is_suspended: prevents i2c controller accesses after suspend is called | |
166 | */ | |
167 | struct tegra_i2c_dev { | |
168 | struct device *dev; | |
6ad068ed | 169 | const struct tegra_i2c_hw_feature *hw; |
db811ca0 | 170 | struct i2c_adapter adapter; |
14e92bd4 LD |
171 | struct clk *div_clk; |
172 | struct clk *fast_clk; | |
dda9d6a8 | 173 | struct reset_control *rst; |
db811ca0 CC |
174 | void __iomem *base; |
175 | int cont_id; | |
176 | int irq; | |
cb63c62d | 177 | bool irq_disabled; |
db811ca0 CC |
178 | int is_dvc; |
179 | struct completion msg_complete; | |
180 | int msg_err; | |
181 | u8 *msg_buf; | |
182 | size_t msg_buf_remaining; | |
183 | int msg_read; | |
49a64ac5 | 184 | u32 bus_clk_rate; |
d57f5ded | 185 | u16 clk_divisor_non_hs_mode; |
db811ca0 CC |
186 | bool is_suspended; |
187 | }; | |
188 | ||
189 | static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) | |
190 | { | |
191 | writel(val, i2c_dev->base + reg); | |
192 | } | |
193 | ||
194 | static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |
195 | { | |
196 | return readl(i2c_dev->base + reg); | |
197 | } | |
198 | ||
199 | /* | |
200 | * i2c_writel and i2c_readl will offset the register if necessary to talk | |
201 | * to the I2C block inside the DVC block | |
202 | */ | |
203 | static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, | |
204 | unsigned long reg) | |
205 | { | |
206 | if (i2c_dev->is_dvc) | |
207 | reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; | |
208 | return reg; | |
209 | } | |
210 | ||
211 | static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, | |
212 | unsigned long reg) | |
213 | { | |
214 | writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
ec7aaca2 LD |
215 | |
216 | /* Read back register to make sure that register writes completed */ | |
217 | if (reg != I2C_TX_FIFO) | |
218 | readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
db811ca0 CC |
219 | } |
220 | ||
221 | static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |
222 | { | |
223 | return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
224 | } | |
225 | ||
226 | static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, | |
227 | unsigned long reg, int len) | |
228 | { | |
229 | writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | |
230 | } | |
231 | ||
232 | static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, | |
233 | unsigned long reg, int len) | |
234 | { | |
235 | readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | |
236 | } | |
237 | ||
238 | static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) | |
239 | { | |
240 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); | |
241 | int_mask &= ~mask; | |
242 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); | |
243 | } | |
244 | ||
245 | static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) | |
246 | { | |
247 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); | |
248 | int_mask |= mask; | |
249 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); | |
250 | } | |
251 | ||
252 | static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) | |
253 | { | |
254 | unsigned long timeout = jiffies + HZ; | |
255 | u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); | |
256 | val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; | |
257 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); | |
258 | ||
259 | while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & | |
260 | (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { | |
261 | if (time_after(jiffies, timeout)) { | |
262 | dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); | |
263 | return -ETIMEDOUT; | |
264 | } | |
265 | msleep(1); | |
266 | } | |
267 | return 0; | |
268 | } | |
269 | ||
270 | static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) | |
271 | { | |
272 | u32 val; | |
273 | int rx_fifo_avail; | |
274 | u8 *buf = i2c_dev->msg_buf; | |
275 | size_t buf_remaining = i2c_dev->msg_buf_remaining; | |
276 | int words_to_transfer; | |
277 | ||
278 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); | |
279 | rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> | |
280 | I2C_FIFO_STATUS_RX_SHIFT; | |
281 | ||
282 | /* Rounds down to not include partial word at the end of buf */ | |
283 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | |
284 | if (words_to_transfer > rx_fifo_avail) | |
285 | words_to_transfer = rx_fifo_avail; | |
286 | ||
287 | i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); | |
288 | ||
289 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | |
290 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | |
291 | rx_fifo_avail -= words_to_transfer; | |
292 | ||
293 | /* | |
294 | * If there is a partial word at the end of buf, handle it manually to | |
295 | * prevent overwriting past the end of buf | |
296 | */ | |
297 | if (rx_fifo_avail > 0 && buf_remaining > 0) { | |
298 | BUG_ON(buf_remaining > 3); | |
299 | val = i2c_readl(i2c_dev, I2C_RX_FIFO); | |
8c340f60 | 300 | val = cpu_to_le32(val); |
db811ca0 CC |
301 | memcpy(buf, &val, buf_remaining); |
302 | buf_remaining = 0; | |
303 | rx_fifo_avail--; | |
304 | } | |
305 | ||
306 | BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); | |
307 | i2c_dev->msg_buf_remaining = buf_remaining; | |
308 | i2c_dev->msg_buf = buf; | |
309 | return 0; | |
310 | } | |
311 | ||
312 | static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) | |
313 | { | |
314 | u32 val; | |
315 | int tx_fifo_avail; | |
316 | u8 *buf = i2c_dev->msg_buf; | |
317 | size_t buf_remaining = i2c_dev->msg_buf_remaining; | |
318 | int words_to_transfer; | |
319 | ||
320 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); | |
321 | tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> | |
322 | I2C_FIFO_STATUS_TX_SHIFT; | |
323 | ||
324 | /* Rounds down to not include partial word at the end of buf */ | |
325 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | |
db811ca0 | 326 | |
96219c3a DA |
327 | /* It's very common to have < 4 bytes, so optimize that case. */ |
328 | if (words_to_transfer) { | |
329 | if (words_to_transfer > tx_fifo_avail) | |
330 | words_to_transfer = tx_fifo_avail; | |
331 | ||
332 | /* | |
333 | * Update state before writing to FIFO. If this casues us | |
334 | * to finish writing all bytes (AKA buf_remaining goes to 0) we | |
335 | * have a potential for an interrupt (PACKET_XFER_COMPLETE is | |
336 | * not maskable). We need to make sure that the isr sees | |
337 | * buf_remaining as 0 and doesn't call us back re-entrantly. | |
338 | */ | |
339 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | |
340 | tx_fifo_avail -= words_to_transfer; | |
341 | i2c_dev->msg_buf_remaining = buf_remaining; | |
342 | i2c_dev->msg_buf = buf + | |
343 | words_to_transfer * BYTES_PER_FIFO_WORD; | |
344 | barrier(); | |
345 | ||
346 | i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); | |
347 | ||
348 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | |
349 | } | |
db811ca0 CC |
350 | |
351 | /* | |
352 | * If there is a partial word at the end of buf, handle it manually to | |
353 | * prevent reading past the end of buf, which could cross a page | |
354 | * boundary and fault. | |
355 | */ | |
356 | if (tx_fifo_avail > 0 && buf_remaining > 0) { | |
357 | BUG_ON(buf_remaining > 3); | |
358 | memcpy(&val, buf, buf_remaining); | |
8c340f60 | 359 | val = le32_to_cpu(val); |
96219c3a DA |
360 | |
361 | /* Again update before writing to FIFO to make sure isr sees. */ | |
362 | i2c_dev->msg_buf_remaining = 0; | |
363 | i2c_dev->msg_buf = NULL; | |
364 | barrier(); | |
365 | ||
db811ca0 | 366 | i2c_writel(i2c_dev, val, I2C_TX_FIFO); |
db811ca0 CC |
367 | } |
368 | ||
db811ca0 CC |
369 | return 0; |
370 | } | |
371 | ||
372 | /* | |
373 | * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) | |
374 | * block. This block is identical to the rest of the I2C blocks, except that | |
375 | * it only supports master mode, it has registers moved around, and it needs | |
376 | * some extra init to get it into I2C mode. The register moves are handled | |
377 | * by i2c_readl and i2c_writel | |
378 | */ | |
379 | static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) | |
380 | { | |
381 | u32 val = 0; | |
382 | val = dvc_readl(i2c_dev, DVC_CTRL_REG3); | |
383 | val |= DVC_CTRL_REG3_SW_PROG; | |
384 | val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; | |
385 | dvc_writel(i2c_dev, val, DVC_CTRL_REG3); | |
386 | ||
387 | val = dvc_readl(i2c_dev, DVC_CTRL_REG1); | |
388 | val |= DVC_CTRL_REG1_INTR_EN; | |
389 | dvc_writel(i2c_dev, val, DVC_CTRL_REG1); | |
390 | } | |
391 | ||
fd301cc4 LD |
392 | static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev) |
393 | { | |
394 | int ret; | |
2a2897ba | 395 | if (!i2c_dev->hw->has_single_clk_source) { |
c9a9ef41 | 396 | ret = clk_enable(i2c_dev->fast_clk); |
2a2897ba LD |
397 | if (ret < 0) { |
398 | dev_err(i2c_dev->dev, | |
399 | "Enabling fast clk failed, err %d\n", ret); | |
400 | return ret; | |
401 | } | |
fd301cc4 | 402 | } |
c9a9ef41 | 403 | ret = clk_enable(i2c_dev->div_clk); |
fd301cc4 LD |
404 | if (ret < 0) { |
405 | dev_err(i2c_dev->dev, | |
406 | "Enabling div clk failed, err %d\n", ret); | |
c9a9ef41 | 407 | clk_disable(i2c_dev->fast_clk); |
fd301cc4 LD |
408 | } |
409 | return ret; | |
410 | } | |
411 | ||
412 | static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev) | |
413 | { | |
c9a9ef41 | 414 | clk_disable(i2c_dev->div_clk); |
2a2897ba | 415 | if (!i2c_dev->hw->has_single_clk_source) |
c9a9ef41 | 416 | clk_disable(i2c_dev->fast_clk); |
fd301cc4 LD |
417 | } |
418 | ||
db811ca0 CC |
419 | static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) |
420 | { | |
421 | u32 val; | |
422 | int err = 0; | |
2a2897ba | 423 | u32 clk_divisor; |
6f4664b2 | 424 | unsigned long timeout = jiffies + HZ; |
db811ca0 | 425 | |
132c803f LD |
426 | err = tegra_i2c_clock_enable(i2c_dev); |
427 | if (err < 0) { | |
428 | dev_err(i2c_dev->dev, "Clock enable failed %d\n", err); | |
429 | return err; | |
430 | } | |
db811ca0 | 431 | |
dda9d6a8 | 432 | reset_control_assert(i2c_dev->rst); |
db811ca0 | 433 | udelay(2); |
dda9d6a8 | 434 | reset_control_deassert(i2c_dev->rst); |
db811ca0 CC |
435 | |
436 | if (i2c_dev->is_dvc) | |
437 | tegra_dvc_init(i2c_dev); | |
438 | ||
40abcf77 JC |
439 | val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | |
440 | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); | |
db811ca0 CC |
441 | i2c_writel(i2c_dev, val, I2C_CNFG); |
442 | i2c_writel(i2c_dev, 0, I2C_INT_MASK); | |
2a2897ba | 443 | |
2a2897ba LD |
444 | /* Make sure clock divisor programmed correctly */ |
445 | clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; | |
d57f5ded | 446 | clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << |
2a2897ba LD |
447 | I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; |
448 | i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); | |
db811ca0 | 449 | |
65a1a0ac KW |
450 | if (!i2c_dev->is_dvc) { |
451 | u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); | |
5afa9d35 SW |
452 | sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; |
453 | i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); | |
454 | i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); | |
455 | i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); | |
456 | ||
65a1a0ac KW |
457 | } |
458 | ||
db811ca0 CC |
459 | val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | |
460 | 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; | |
461 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); | |
462 | ||
463 | if (tegra_i2c_flush_fifos(i2c_dev)) | |
464 | err = -ETIMEDOUT; | |
465 | ||
6f4664b2 LD |
466 | if (i2c_dev->hw->has_config_load_reg) { |
467 | i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); | |
468 | while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) { | |
469 | if (time_after(jiffies, timeout)) { | |
470 | dev_warn(i2c_dev->dev, | |
471 | "timeout waiting for config load\n"); | |
472 | return -ETIMEDOUT; | |
473 | } | |
474 | msleep(1); | |
475 | } | |
476 | } | |
477 | ||
fd301cc4 | 478 | tegra_i2c_clock_disable(i2c_dev); |
cb63c62d TP |
479 | |
480 | if (i2c_dev->irq_disabled) { | |
481 | i2c_dev->irq_disabled = 0; | |
482 | enable_irq(i2c_dev->irq); | |
483 | } | |
484 | ||
db811ca0 CC |
485 | return err; |
486 | } | |
487 | ||
488 | static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) | |
489 | { | |
490 | u32 status; | |
491 | const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; | |
492 | struct tegra_i2c_dev *i2c_dev = dev_id; | |
493 | ||
494 | status = i2c_readl(i2c_dev, I2C_INT_STATUS); | |
495 | ||
496 | if (status == 0) { | |
cb63c62d TP |
497 | dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", |
498 | i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), | |
499 | i2c_readl(i2c_dev, I2C_STATUS), | |
500 | i2c_readl(i2c_dev, I2C_CNFG)); | |
501 | i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; | |
502 | ||
503 | if (!i2c_dev->irq_disabled) { | |
504 | disable_irq_nosync(i2c_dev->irq); | |
505 | i2c_dev->irq_disabled = 1; | |
506 | } | |
cb63c62d | 507 | goto err; |
db811ca0 CC |
508 | } |
509 | ||
510 | if (unlikely(status & status_err)) { | |
511 | if (status & I2C_INT_NO_ACK) | |
512 | i2c_dev->msg_err |= I2C_ERR_NO_ACK; | |
513 | if (status & I2C_INT_ARBITRATION_LOST) | |
514 | i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; | |
db811ca0 CC |
515 | goto err; |
516 | } | |
517 | ||
518 | if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { | |
519 | if (i2c_dev->msg_buf_remaining) | |
520 | tegra_i2c_empty_rx_fifo(i2c_dev); | |
521 | else | |
522 | BUG(); | |
523 | } | |
524 | ||
525 | if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { | |
526 | if (i2c_dev->msg_buf_remaining) | |
527 | tegra_i2c_fill_tx_fifo(i2c_dev); | |
528 | else | |
529 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); | |
530 | } | |
531 | ||
c889e91d LD |
532 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); |
533 | if (i2c_dev->is_dvc) | |
534 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); | |
535 | ||
96219c3a DA |
536 | if (status & I2C_INT_PACKET_XFER_COMPLETE) { |
537 | BUG_ON(i2c_dev->msg_buf_remaining); | |
db811ca0 | 538 | complete(&i2c_dev->msg_complete); |
96219c3a | 539 | } |
db811ca0 CC |
540 | return IRQ_HANDLED; |
541 | err: | |
25985edc | 542 | /* An error occurred, mask all interrupts */ |
db811ca0 CC |
543 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | |
544 | I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | | |
545 | I2C_INT_RX_FIFO_DATA_REQ); | |
546 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); | |
cb63c62d TP |
547 | if (i2c_dev->is_dvc) |
548 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); | |
c889e91d LD |
549 | |
550 | complete(&i2c_dev->msg_complete); | |
db811ca0 CC |
551 | return IRQ_HANDLED; |
552 | } | |
553 | ||
554 | static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, | |
c8f5af2f | 555 | struct i2c_msg *msg, enum msg_end_type end_state) |
db811ca0 CC |
556 | { |
557 | u32 packet_header; | |
558 | u32 int_mask; | |
6973a39c | 559 | unsigned long time_left; |
db811ca0 CC |
560 | |
561 | tegra_i2c_flush_fifos(i2c_dev); | |
db811ca0 CC |
562 | |
563 | if (msg->len == 0) | |
564 | return -EINVAL; | |
565 | ||
566 | i2c_dev->msg_buf = msg->buf; | |
567 | i2c_dev->msg_buf_remaining = msg->len; | |
568 | i2c_dev->msg_err = I2C_ERR_NONE; | |
569 | i2c_dev->msg_read = (msg->flags & I2C_M_RD); | |
16735d02 | 570 | reinit_completion(&i2c_dev->msg_complete); |
db811ca0 CC |
571 | |
572 | packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | | |
573 | PACKET_HEADER0_PROTOCOL_I2C | | |
574 | (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | | |
575 | (1 << PACKET_HEADER0_PACKET_ID_SHIFT); | |
576 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
577 | ||
578 | packet_header = msg->len - 1; | |
579 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
580 | ||
353f56b5 | 581 | packet_header = I2C_HEADER_IE_ENABLE; |
c8f5af2f LD |
582 | if (end_state == MSG_END_CONTINUE) |
583 | packet_header |= I2C_HEADER_CONTINUE_XFER; | |
584 | else if (end_state == MSG_END_REPEAT_START) | |
2078cf3b | 585 | packet_header |= I2C_HEADER_REPEAT_START; |
353f56b5 LD |
586 | if (msg->flags & I2C_M_TEN) { |
587 | packet_header |= msg->addr; | |
db811ca0 | 588 | packet_header |= I2C_HEADER_10BIT_ADDR; |
353f56b5 LD |
589 | } else { |
590 | packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; | |
591 | } | |
db811ca0 CC |
592 | if (msg->flags & I2C_M_IGNORE_NAK) |
593 | packet_header |= I2C_HEADER_CONT_ON_NAK; | |
db811ca0 CC |
594 | if (msg->flags & I2C_M_RD) |
595 | packet_header |= I2C_HEADER_READ; | |
596 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
597 | ||
598 | if (!(msg->flags & I2C_M_RD)) | |
599 | tegra_i2c_fill_tx_fifo(i2c_dev); | |
600 | ||
601 | int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; | |
2a2897ba LD |
602 | if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) |
603 | int_mask |= I2C_INT_PACKET_XFER_COMPLETE; | |
db811ca0 CC |
604 | if (msg->flags & I2C_M_RD) |
605 | int_mask |= I2C_INT_RX_FIFO_DATA_REQ; | |
606 | else if (i2c_dev->msg_buf_remaining) | |
607 | int_mask |= I2C_INT_TX_FIFO_DATA_REQ; | |
608 | tegra_i2c_unmask_irq(i2c_dev, int_mask); | |
609 | dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", | |
610 | i2c_readl(i2c_dev, I2C_INT_MASK)); | |
611 | ||
6973a39c NMG |
612 | time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, |
613 | TEGRA_I2C_TIMEOUT); | |
db811ca0 CC |
614 | tegra_i2c_mask_irq(i2c_dev, int_mask); |
615 | ||
6973a39c | 616 | if (time_left == 0) { |
db811ca0 CC |
617 | dev_err(i2c_dev->dev, "i2c transfer timed out\n"); |
618 | ||
619 | tegra_i2c_init(i2c_dev); | |
620 | return -ETIMEDOUT; | |
621 | } | |
622 | ||
6973a39c NMG |
623 | dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", |
624 | time_left, completion_done(&i2c_dev->msg_complete), | |
625 | i2c_dev->msg_err); | |
db811ca0 CC |
626 | |
627 | if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) | |
628 | return 0; | |
629 | ||
f70893d0 AC |
630 | /* |
631 | * NACK interrupt is generated before the I2C controller generates the | |
632 | * STOP condition on the bus. So wait for 2 clock periods before resetting | |
633 | * the controller so that STOP condition has been delivered properly. | |
634 | */ | |
635 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) | |
636 | udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); | |
637 | ||
db811ca0 CC |
638 | tegra_i2c_init(i2c_dev); |
639 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { | |
640 | if (msg->flags & I2C_M_IGNORE_NAK) | |
641 | return 0; | |
642 | return -EREMOTEIO; | |
643 | } | |
644 | ||
645 | return -EIO; | |
646 | } | |
647 | ||
648 | static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |
649 | int num) | |
650 | { | |
651 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); | |
652 | int i; | |
653 | int ret = 0; | |
654 | ||
655 | if (i2c_dev->is_suspended) | |
656 | return -EBUSY; | |
657 | ||
132c803f LD |
658 | ret = tegra_i2c_clock_enable(i2c_dev); |
659 | if (ret < 0) { | |
660 | dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret); | |
661 | return ret; | |
662 | } | |
663 | ||
db811ca0 | 664 | for (i = 0; i < num; i++) { |
c8f5af2f LD |
665 | enum msg_end_type end_type = MSG_END_STOP; |
666 | if (i < (num - 1)) { | |
667 | if (msgs[i + 1].flags & I2C_M_NOSTART) | |
668 | end_type = MSG_END_CONTINUE; | |
669 | else | |
670 | end_type = MSG_END_REPEAT_START; | |
671 | } | |
672 | ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); | |
db811ca0 CC |
673 | if (ret) |
674 | break; | |
675 | } | |
fd301cc4 | 676 | tegra_i2c_clock_disable(i2c_dev); |
db811ca0 CC |
677 | return ret ?: i; |
678 | } | |
679 | ||
680 | static u32 tegra_i2c_func(struct i2c_adapter *adap) | |
681 | { | |
6ad068ed | 682 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
4bb28e37 WS |
683 | u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
684 | I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; | |
6ad068ed LD |
685 | |
686 | if (i2c_dev->hw->has_continue_xfer_support) | |
687 | ret |= I2C_FUNC_NOSTART; | |
688 | return ret; | |
db811ca0 CC |
689 | } |
690 | ||
691 | static const struct i2c_algorithm tegra_i2c_algo = { | |
692 | .master_xfer = tegra_i2c_xfer, | |
693 | .functionality = tegra_i2c_func, | |
694 | }; | |
695 | ||
3aaa34b9 WS |
696 | /* payload size is only 12 bit */ |
697 | static struct i2c_adapter_quirks tegra_i2c_quirks = { | |
698 | .max_read_len = 4096, | |
699 | .max_write_len = 4096, | |
700 | }; | |
701 | ||
6ad068ed LD |
702 | static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { |
703 | .has_continue_xfer_support = false, | |
2a2897ba LD |
704 | .has_per_pkt_xfer_complete_irq = false, |
705 | .has_single_clk_source = false, | |
706 | .clk_divisor_hs_mode = 3, | |
707 | .clk_divisor_std_fast_mode = 0, | |
d57f5ded | 708 | .clk_divisor_fast_plus_mode = 0, |
6f4664b2 | 709 | .has_config_load_reg = false, |
6ad068ed LD |
710 | }; |
711 | ||
712 | static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { | |
713 | .has_continue_xfer_support = true, | |
2a2897ba LD |
714 | .has_per_pkt_xfer_complete_irq = false, |
715 | .has_single_clk_source = false, | |
716 | .clk_divisor_hs_mode = 3, | |
717 | .clk_divisor_std_fast_mode = 0, | |
d57f5ded | 718 | .clk_divisor_fast_plus_mode = 0, |
6f4664b2 | 719 | .has_config_load_reg = false, |
2a2897ba LD |
720 | }; |
721 | ||
722 | static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { | |
723 | .has_continue_xfer_support = true, | |
724 | .has_per_pkt_xfer_complete_irq = true, | |
725 | .has_single_clk_source = true, | |
726 | .clk_divisor_hs_mode = 1, | |
727 | .clk_divisor_std_fast_mode = 0x19, | |
d57f5ded | 728 | .clk_divisor_fast_plus_mode = 0x10, |
6f4664b2 LD |
729 | .has_config_load_reg = false, |
730 | }; | |
731 | ||
732 | static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { | |
733 | .has_continue_xfer_support = true, | |
734 | .has_per_pkt_xfer_complete_irq = true, | |
735 | .has_single_clk_source = true, | |
736 | .clk_divisor_hs_mode = 1, | |
737 | .clk_divisor_std_fast_mode = 0x19, | |
d57f5ded | 738 | .clk_divisor_fast_plus_mode = 0x10, |
6f4664b2 | 739 | .has_config_load_reg = true, |
6ad068ed LD |
740 | }; |
741 | ||
6ad068ed | 742 | /* Match table for of_platform binding */ |
0b255e92 | 743 | static const struct of_device_id tegra_i2c_of_match[] = { |
6f4664b2 | 744 | { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, |
2a2897ba | 745 | { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, |
6ad068ed LD |
746 | { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, |
747 | { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, | |
748 | { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, | |
749 | {}, | |
750 | }; | |
751 | MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); | |
6ad068ed | 752 | |
0b255e92 | 753 | static int tegra_i2c_probe(struct platform_device *pdev) |
db811ca0 CC |
754 | { |
755 | struct tegra_i2c_dev *i2c_dev; | |
db811ca0 | 756 | struct resource *res; |
14e92bd4 LD |
757 | struct clk *div_clk; |
758 | struct clk *fast_clk; | |
f533c61e | 759 | void __iomem *base; |
db811ca0 CC |
760 | int irq; |
761 | int ret = 0; | |
c9a9ef41 | 762 | int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; |
db811ca0 CC |
763 | |
764 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
84dbf809 TR |
765 | base = devm_ioremap_resource(&pdev->dev, res); |
766 | if (IS_ERR(base)) | |
767 | return PTR_ERR(base); | |
db811ca0 CC |
768 | |
769 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
770 | if (!res) { | |
771 | dev_err(&pdev->dev, "no irq resource\n"); | |
9cbb6b2b | 772 | return -EINVAL; |
db811ca0 CC |
773 | } |
774 | irq = res->start; | |
775 | ||
14e92bd4 LD |
776 | div_clk = devm_clk_get(&pdev->dev, "div-clk"); |
777 | if (IS_ERR(div_clk)) { | |
db811ca0 | 778 | dev_err(&pdev->dev, "missing controller clock"); |
14e92bd4 | 779 | return PTR_ERR(div_clk); |
db811ca0 CC |
780 | } |
781 | ||
9cbb6b2b | 782 | i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); |
46797a2a | 783 | if (!i2c_dev) |
9cbb6b2b | 784 | return -ENOMEM; |
db811ca0 CC |
785 | |
786 | i2c_dev->base = base; | |
14e92bd4 | 787 | i2c_dev->div_clk = div_clk; |
db811ca0 | 788 | i2c_dev->adapter.algo = &tegra_i2c_algo; |
3aaa34b9 | 789 | i2c_dev->adapter.quirks = &tegra_i2c_quirks; |
db811ca0 CC |
790 | i2c_dev->irq = irq; |
791 | i2c_dev->cont_id = pdev->id; | |
792 | i2c_dev->dev = &pdev->dev; | |
5c470f39 | 793 | |
dda9d6a8 SW |
794 | i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c"); |
795 | if (IS_ERR(i2c_dev->rst)) { | |
796 | dev_err(&pdev->dev, "missing controller reset"); | |
797 | return PTR_ERR(i2c_dev->rst); | |
798 | } | |
799 | ||
49a64ac5 SW |
800 | ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency", |
801 | &i2c_dev->bus_clk_rate); | |
802 | if (ret) | |
803 | i2c_dev->bus_clk_rate = 100000; /* default clock rate */ | |
db811ca0 | 804 | |
6ad068ed LD |
805 | i2c_dev->hw = &tegra20_i2c_hw; |
806 | ||
807 | if (pdev->dev.of_node) { | |
808 | const struct of_device_id *match; | |
49a64ac5 | 809 | match = of_match_device(tegra_i2c_of_match, &pdev->dev); |
6ad068ed | 810 | i2c_dev->hw = match->data; |
68fb6695 SW |
811 | i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, |
812 | "nvidia,tegra20-i2c-dvc"); | |
6ad068ed | 813 | } else if (pdev->id == 3) { |
db811ca0 | 814 | i2c_dev->is_dvc = 1; |
6ad068ed | 815 | } |
db811ca0 CC |
816 | init_completion(&i2c_dev->msg_complete); |
817 | ||
2a2897ba LD |
818 | if (!i2c_dev->hw->has_single_clk_source) { |
819 | fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); | |
820 | if (IS_ERR(fast_clk)) { | |
821 | dev_err(&pdev->dev, "missing fast clock"); | |
822 | return PTR_ERR(fast_clk); | |
823 | } | |
824 | i2c_dev->fast_clk = fast_clk; | |
825 | } | |
826 | ||
db811ca0 CC |
827 | platform_set_drvdata(pdev, i2c_dev); |
828 | ||
c9a9ef41 MP |
829 | if (!i2c_dev->hw->has_single_clk_source) { |
830 | ret = clk_prepare(i2c_dev->fast_clk); | |
831 | if (ret < 0) { | |
832 | dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); | |
833 | return ret; | |
834 | } | |
835 | } | |
836 | ||
d57f5ded LD |
837 | i2c_dev->clk_divisor_non_hs_mode = |
838 | i2c_dev->hw->clk_divisor_std_fast_mode; | |
839 | if (i2c_dev->hw->clk_divisor_fast_plus_mode && | |
840 | (i2c_dev->bus_clk_rate == 1000000)) | |
841 | i2c_dev->clk_divisor_non_hs_mode = | |
842 | i2c_dev->hw->clk_divisor_fast_plus_mode; | |
843 | ||
844 | clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); | |
c9a9ef41 MP |
845 | ret = clk_set_rate(i2c_dev->div_clk, |
846 | i2c_dev->bus_clk_rate * clk_multiplier); | |
847 | if (ret) { | |
848 | dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); | |
849 | goto unprepare_fast_clk; | |
850 | } | |
851 | ||
852 | ret = clk_prepare(i2c_dev->div_clk); | |
853 | if (ret < 0) { | |
854 | dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); | |
855 | goto unprepare_fast_clk; | |
856 | } | |
857 | ||
db811ca0 CC |
858 | ret = tegra_i2c_init(i2c_dev); |
859 | if (ret) { | |
860 | dev_err(&pdev->dev, "Failed to initialize i2c controller"); | |
c9a9ef41 | 861 | goto unprepare_div_clk; |
db811ca0 CC |
862 | } |
863 | ||
9cbb6b2b | 864 | ret = devm_request_irq(&pdev->dev, i2c_dev->irq, |
91b370a0 | 865 | tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); |
db811ca0 CC |
866 | if (ret) { |
867 | dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); | |
c9a9ef41 | 868 | goto unprepare_div_clk; |
db811ca0 CC |
869 | } |
870 | ||
db811ca0 CC |
871 | i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); |
872 | i2c_dev->adapter.owner = THIS_MODULE; | |
6025189a | 873 | i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; |
db811ca0 CC |
874 | strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", |
875 | sizeof(i2c_dev->adapter.name)); | |
db811ca0 CC |
876 | i2c_dev->adapter.dev.parent = &pdev->dev; |
877 | i2c_dev->adapter.nr = pdev->id; | |
5c470f39 | 878 | i2c_dev->adapter.dev.of_node = pdev->dev.of_node; |
db811ca0 CC |
879 | |
880 | ret = i2c_add_numbered_adapter(&i2c_dev->adapter); | |
881 | if (ret) { | |
882 | dev_err(&pdev->dev, "Failed to add I2C adapter\n"); | |
c9a9ef41 | 883 | goto unprepare_div_clk; |
db811ca0 CC |
884 | } |
885 | ||
886 | return 0; | |
c9a9ef41 MP |
887 | |
888 | unprepare_div_clk: | |
889 | clk_unprepare(i2c_dev->div_clk); | |
890 | ||
891 | unprepare_fast_clk: | |
892 | if (!i2c_dev->hw->has_single_clk_source) | |
893 | clk_unprepare(i2c_dev->fast_clk); | |
894 | ||
895 | return ret; | |
db811ca0 CC |
896 | } |
897 | ||
0b255e92 | 898 | static int tegra_i2c_remove(struct platform_device *pdev) |
db811ca0 CC |
899 | { |
900 | struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); | |
901 | i2c_del_adapter(&i2c_dev->adapter); | |
c9a9ef41 MP |
902 | |
903 | clk_unprepare(i2c_dev->div_clk); | |
904 | if (!i2c_dev->hw->has_single_clk_source) | |
905 | clk_unprepare(i2c_dev->fast_clk); | |
906 | ||
db811ca0 CC |
907 | return 0; |
908 | } | |
909 | ||
371e67c9 | 910 | #ifdef CONFIG_PM_SLEEP |
5db20c49 | 911 | static int tegra_i2c_suspend(struct device *dev) |
db811ca0 | 912 | { |
6a7b3c3c | 913 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
db811ca0 CC |
914 | |
915 | i2c_lock_adapter(&i2c_dev->adapter); | |
916 | i2c_dev->is_suspended = true; | |
917 | i2c_unlock_adapter(&i2c_dev->adapter); | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
5db20c49 | 922 | static int tegra_i2c_resume(struct device *dev) |
db811ca0 | 923 | { |
6a7b3c3c | 924 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
db811ca0 CC |
925 | int ret; |
926 | ||
927 | i2c_lock_adapter(&i2c_dev->adapter); | |
928 | ||
929 | ret = tegra_i2c_init(i2c_dev); | |
930 | ||
931 | if (ret) { | |
932 | i2c_unlock_adapter(&i2c_dev->adapter); | |
933 | return ret; | |
934 | } | |
935 | ||
936 | i2c_dev->is_suspended = false; | |
937 | ||
938 | i2c_unlock_adapter(&i2c_dev->adapter); | |
939 | ||
940 | return 0; | |
941 | } | |
6a7b3c3c | 942 | |
5db20c49 | 943 | static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume); |
6a7b3c3c RW |
944 | #define TEGRA_I2C_PM (&tegra_i2c_pm) |
945 | #else | |
946 | #define TEGRA_I2C_PM NULL | |
db811ca0 CC |
947 | #endif |
948 | ||
949 | static struct platform_driver tegra_i2c_driver = { | |
950 | .probe = tegra_i2c_probe, | |
0b255e92 | 951 | .remove = tegra_i2c_remove, |
db811ca0 CC |
952 | .driver = { |
953 | .name = "tegra-i2c", | |
49a64ac5 | 954 | .of_match_table = tegra_i2c_of_match, |
6a7b3c3c | 955 | .pm = TEGRA_I2C_PM, |
db811ca0 CC |
956 | }, |
957 | }; | |
958 | ||
959 | static int __init tegra_i2c_init_driver(void) | |
960 | { | |
961 | return platform_driver_register(&tegra_i2c_driver); | |
962 | } | |
963 | ||
964 | static void __exit tegra_i2c_exit_driver(void) | |
965 | { | |
966 | platform_driver_unregister(&tegra_i2c_driver); | |
967 | } | |
968 | ||
969 | subsys_initcall(tegra_i2c_init_driver); | |
970 | module_exit(tegra_i2c_exit_driver); | |
971 | ||
972 | MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); | |
973 | MODULE_AUTHOR("Colin Cross"); | |
974 | MODULE_LICENSE("GPL v2"); |