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i2c: muxes: rename first set of drivers to a standard pattern
[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-tegra.c
CommitLineData
db811ca0
CC		 1/*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/i2c-tegra.h>
5c470f39 29#include <linux/of_i2c.h>
93cf5d75 30#include <linux/module.h>
db811ca0
CC		 31
32#include <asm/unaligned.h>
33
34#include <mach/clk.h>
35
36#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
37#define BYTES_PER_FIFO_WORD 4
38
39#define I2C_CNFG 0x000
40abcf77 40#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
db811ca0
CC		 41#define I2C_CNFG_PACKET_MODE_EN (1<<10)
42#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
cb63c62d 43#define I2C_STATUS 0x01C
db811ca0 44#define I2C_SL_CNFG 0x020
5afa9d35 45#define I2C_SL_CNFG_NACK (1<<1)
db811ca0
CC		 46#define I2C_SL_CNFG_NEWSL (1<<2)
47#define I2C_SL_ADDR1 0x02c
5afa9d35 48#define I2C_SL_ADDR2 0x030
db811ca0
CC		 49#define I2C_TX_FIFO 0x050
50#define I2C_RX_FIFO 0x054
51#define I2C_PACKET_TRANSFER_STATUS 0x058
52#define I2C_FIFO_CONTROL 0x05c
53#define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
54#define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
55#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
56#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
57#define I2C_FIFO_STATUS 0x060
58#define I2C_FIFO_STATUS_TX_MASK 0xF0
59#define I2C_FIFO_STATUS_TX_SHIFT 4
60#define I2C_FIFO_STATUS_RX_MASK 0x0F
61#define I2C_FIFO_STATUS_RX_SHIFT 0
62#define I2C_INT_MASK 0x064
63#define I2C_INT_STATUS 0x068
64#define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
65#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
66#define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
67#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
68#define I2C_INT_NO_ACK (1<<3)
69#define I2C_INT_ARBITRATION_LOST (1<<2)
70#define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
71#define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
72#define I2C_CLK_DIVISOR 0x06c
73
74#define DVC_CTRL_REG1 0x000
75#define DVC_CTRL_REG1_INTR_EN (1<<10)
76#define DVC_CTRL_REG2 0x004
77#define DVC_CTRL_REG3 0x008
78#define DVC_CTRL_REG3_SW_PROG (1<<26)
79#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80#define DVC_STATUS 0x00c
81#define DVC_STATUS_I2C_DONE_INTR (1<<30)
82
83#define I2C_ERR_NONE 0x00
84#define I2C_ERR_NO_ACK 0x01
85#define I2C_ERR_ARBITRATION_LOST 0x02
cb63c62d 86#define I2C_ERR_UNKNOWN_INTERRUPT 0x04
db811ca0
CC		 87
88#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89#define PACKET_HEADER0_PACKET_ID_SHIFT 16
90#define PACKET_HEADER0_CONT_ID_SHIFT 12
91#define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
92
93#define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94#define I2C_HEADER_CONT_ON_NAK (1<<21)
95#define I2C_HEADER_SEND_START_BYTE (1<<20)
96#define I2C_HEADER_READ (1<<19)
97#define I2C_HEADER_10BIT_ADDR (1<<18)
98#define I2C_HEADER_IE_ENABLE (1<<17)
99#define I2C_HEADER_REPEAT_START (1<<16)
100#define I2C_HEADER_MASTER_ADDR_SHIFT 12
101#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
102
103/**
104 * struct tegra_i2c_dev - per device i2c context
105 * @dev: device reference for power management
106 * @adapter: core i2c layer adapter information
107 * @clk: clock reference for i2c controller
108 * @i2c_clk: clock reference for i2c bus
109 * @iomem: memory resource for registers
110 * @base: ioremapped registers cookie
111 * @cont_id: i2c controller id, used for for packet header
112 * @irq: irq number of transfer complete interrupt
113 * @is_dvc: identifies the DVC i2c controller, has a different register layout
114 * @msg_complete: transfer completion notifier
115 * @msg_err: error code for completed message
116 * @msg_buf: pointer to current message data
117 * @msg_buf_remaining: size of unsent data in the message buffer
118 * @msg_read: identifies read transfers
119 * @bus_clk_rate: current i2c bus clock rate
120 * @is_suspended: prevents i2c controller accesses after suspend is called
121 */
122struct tegra_i2c_dev {
123 struct device *dev;
124 struct i2c_adapter adapter;
125 struct clk *clk;
126 struct clk *i2c_clk;
127 struct resource *iomem;
128 void __iomem *base;
129 int cont_id;
130 int irq;
cb63c62d 131 bool irq_disabled;
db811ca0
CC		 132 int is_dvc;
133 struct completion msg_complete;
134 int msg_err;
135 u8 *msg_buf;
136 size_t msg_buf_remaining;
137 int msg_read;
138 unsigned long bus_clk_rate;
139 bool is_suspended;
140};
141
142static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
143{
144 writel(val, i2c_dev->base + reg);
145}
146
147static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
148{
149 return readl(i2c_dev->base + reg);
150}
151
152/*
153 * i2c_writel and i2c_readl will offset the register if necessary to talk
154 * to the I2C block inside the DVC block
155 */
156static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
157 unsigned long reg)
158{
159 if (i2c_dev->is_dvc)
160 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
161 return reg;
162}
163
164static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
165 unsigned long reg)
166{
167 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
168}
169
170static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
171{
172 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
173}
174
175static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
176 unsigned long reg, int len)
177{
178 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
179}
180
181static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
182 unsigned long reg, int len)
183{
184 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
185}
186
187static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
188{
189 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
190 int_mask &= ~mask;
191 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
192}
193
194static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
195{
196 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
197 int_mask |= mask;
198 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
199}
200
201static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
202{
203 unsigned long timeout = jiffies + HZ;
204 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
205 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
206 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
207
208 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
209 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
210 if (time_after(jiffies, timeout)) {
211 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
212 return -ETIMEDOUT;
213 }
214 msleep(1);
215 }
216 return 0;
217}
218
219static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
220{
221 u32 val;
222 int rx_fifo_avail;
223 u8 *buf = i2c_dev->msg_buf;
224 size_t buf_remaining = i2c_dev->msg_buf_remaining;
225 int words_to_transfer;
226
227 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
228 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
229 I2C_FIFO_STATUS_RX_SHIFT;
230
231 /* Rounds down to not include partial word at the end of buf */
232 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
233 if (words_to_transfer > rx_fifo_avail)
234 words_to_transfer = rx_fifo_avail;
235
236 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
237
238 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
239 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
240 rx_fifo_avail -= words_to_transfer;
241
242 /*
243 * If there is a partial word at the end of buf, handle it manually to
244 * prevent overwriting past the end of buf
245 */
246 if (rx_fifo_avail > 0 && buf_remaining > 0) {
247 BUG_ON(buf_remaining > 3);
248 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
249 memcpy(buf, &val, buf_remaining);
250 buf_remaining = 0;
251 rx_fifo_avail--;
252 }
253
254 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
255 i2c_dev->msg_buf_remaining = buf_remaining;
256 i2c_dev->msg_buf = buf;
257 return 0;
258}
259
260static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
261{
262 u32 val;
263 int tx_fifo_avail;
264 u8 *buf = i2c_dev->msg_buf;
265 size_t buf_remaining = i2c_dev->msg_buf_remaining;
266 int words_to_transfer;
267
268 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
269 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
270 I2C_FIFO_STATUS_TX_SHIFT;
271
272 /* Rounds down to not include partial word at the end of buf */
273 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
db811ca0 274
96219c3a
DA		 275 /* It's very common to have < 4 bytes, so optimize that case. */
276 if (words_to_transfer) {
277 if (words_to_transfer > tx_fifo_avail)
278 words_to_transfer = tx_fifo_avail;
279
280 /*
281 * Update state before writing to FIFO. If this casues us
282 * to finish writing all bytes (AKA buf_remaining goes to 0) we
283 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
284 * not maskable). We need to make sure that the isr sees
285 * buf_remaining as 0 and doesn't call us back re-entrantly.
286 */
287 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
288 tx_fifo_avail -= words_to_transfer;
289 i2c_dev->msg_buf_remaining = buf_remaining;
290 i2c_dev->msg_buf = buf +
291 words_to_transfer * BYTES_PER_FIFO_WORD;
292 barrier();
293
294 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
295
296 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
297 }
db811ca0
CC		 298
299 /*
300 * If there is a partial word at the end of buf, handle it manually to
301 * prevent reading past the end of buf, which could cross a page
302 * boundary and fault.
303 */
304 if (tx_fifo_avail > 0 && buf_remaining > 0) {
305 BUG_ON(buf_remaining > 3);
306 memcpy(&val, buf, buf_remaining);
96219c3a
DA		 307
308 /* Again update before writing to FIFO to make sure isr sees. */
309 i2c_dev->msg_buf_remaining = 0;
310 i2c_dev->msg_buf = NULL;
311 barrier();
312
db811ca0 313 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
db811ca0
CC		 314 }
315
db811ca0
CC		 316 return 0;
317}
318
319/*
320 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
321 * block. This block is identical to the rest of the I2C blocks, except that
322 * it only supports master mode, it has registers moved around, and it needs
323 * some extra init to get it into I2C mode. The register moves are handled
324 * by i2c_readl and i2c_writel
325 */
326static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
327{
328 u32 val = 0;
329 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
330 val |= DVC_CTRL_REG3_SW_PROG;
331 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
332 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
333
334 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
335 val |= DVC_CTRL_REG1_INTR_EN;
336 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
337}
338
339static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
340{
341 u32 val;
342 int err = 0;
343
344 clk_enable(i2c_dev->clk);
345
346 tegra_periph_reset_assert(i2c_dev->clk);
347 udelay(2);
348 tegra_periph_reset_deassert(i2c_dev->clk);
349
350 if (i2c_dev->is_dvc)
351 tegra_dvc_init(i2c_dev);
352
40abcf77
JC		 353 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
354 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
db811ca0
CC		 355 i2c_writel(i2c_dev, val, I2C_CNFG);
356 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
357 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
358
65a1a0ac
KW		 359 if (!i2c_dev->is_dvc) {
360 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
5afa9d35
SW		 361 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
362 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
363 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
364 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
365
65a1a0ac
KW		 366 }
367
db811ca0
CC		 368 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
369 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
370 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
371
372 if (tegra_i2c_flush_fifos(i2c_dev))
373 err = -ETIMEDOUT;
374
375 clk_disable(i2c_dev->clk);
cb63c62d
TP		 376
377 if (i2c_dev->irq_disabled) {
378 i2c_dev->irq_disabled = 0;
379 enable_irq(i2c_dev->irq);
380 }
381
db811ca0
CC		 382 return err;
383}
384
385static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
386{
387 u32 status;
388 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
389 struct tegra_i2c_dev *i2c_dev = dev_id;
390
391 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
392
393 if (status == 0) {
cb63c62d
TP		 394 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
395 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
396 i2c_readl(i2c_dev, I2C_STATUS),
397 i2c_readl(i2c_dev, I2C_CNFG));
398 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
399
400 if (!i2c_dev->irq_disabled) {
401 disable_irq_nosync(i2c_dev->irq);
402 i2c_dev->irq_disabled = 1;
403 }
404
405 complete(&i2c_dev->msg_complete);
406 goto err;
db811ca0
CC		 407 }
408
409 if (unlikely(status & status_err)) {
410 if (status & I2C_INT_NO_ACK)
411 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
412 if (status & I2C_INT_ARBITRATION_LOST)
413 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
414 complete(&i2c_dev->msg_complete);
415 goto err;
416 }
417
418 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
419 if (i2c_dev->msg_buf_remaining)
420 tegra_i2c_empty_rx_fifo(i2c_dev);
421 else
422 BUG();
423 }
424
425 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
426 if (i2c_dev->msg_buf_remaining)
427 tegra_i2c_fill_tx_fifo(i2c_dev);
428 else
429 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
430 }
431
96219c3a
DA		 432 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
433 BUG_ON(i2c_dev->msg_buf_remaining);
db811ca0 434 complete(&i2c_dev->msg_complete);
96219c3a 435 }
db811ca0
CC		 436
437 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
438 if (i2c_dev->is_dvc)
439 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
440 return IRQ_HANDLED;
441err:
25985edc 442 /* An error occurred, mask all interrupts */
db811ca0
CC		 443 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
444 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
445 I2C_INT_RX_FIFO_DATA_REQ);
446 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
cb63c62d
TP		 447 if (i2c_dev->is_dvc)
448 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
db811ca0
CC		 449 return IRQ_HANDLED;
450}
451
452static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
453 struct i2c_msg *msg, int stop)
454{
455 u32 packet_header;
456 u32 int_mask;
457 int ret;
458
459 tegra_i2c_flush_fifos(i2c_dev);
db811ca0
CC		 460
461 if (msg->len == 0)
462 return -EINVAL;
463
464 i2c_dev->msg_buf = msg->buf;
465 i2c_dev->msg_buf_remaining = msg->len;
466 i2c_dev->msg_err = I2C_ERR_NONE;
467 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
468 INIT_COMPLETION(i2c_dev->msg_complete);
469
470 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
471 PACKET_HEADER0_PROTOCOL_I2C |
472 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
473 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
474 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
475
476 packet_header = msg->len - 1;
477 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
478
479 packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
480 packet_header |= I2C_HEADER_IE_ENABLE;
2078cf3b
EG		 481 if (!stop)
482 packet_header |= I2C_HEADER_REPEAT_START;
db811ca0
CC		 483 if (msg->flags & I2C_M_TEN)
484 packet_header |= I2C_HEADER_10BIT_ADDR;
485 if (msg->flags & I2C_M_IGNORE_NAK)
486 packet_header |= I2C_HEADER_CONT_ON_NAK;
db811ca0
CC		 487 if (msg->flags & I2C_M_RD)
488 packet_header |= I2C_HEADER_READ;
489 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
490
491 if (!(msg->flags & I2C_M_RD))
492 tegra_i2c_fill_tx_fifo(i2c_dev);
493
494 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
495 if (msg->flags & I2C_M_RD)
496 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
497 else if (i2c_dev->msg_buf_remaining)
498 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
499 tegra_i2c_unmask_irq(i2c_dev, int_mask);
500 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
501 i2c_readl(i2c_dev, I2C_INT_MASK));
502
503 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
504 tegra_i2c_mask_irq(i2c_dev, int_mask);
505
506 if (WARN_ON(ret == 0)) {
507 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
508
509 tegra_i2c_init(i2c_dev);
510 return -ETIMEDOUT;
511 }
512
513 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
514 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
515
516 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
517 return 0;
518
f70893d0
AC		 519 /*
520 * NACK interrupt is generated before the I2C controller generates the
521 * STOP condition on the bus. So wait for 2 clock periods before resetting
522 * the controller so that STOP condition has been delivered properly.
523 */
524 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
525 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
526
db811ca0
CC		 527 tegra_i2c_init(i2c_dev);
528 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
529 if (msg->flags & I2C_M_IGNORE_NAK)
530 return 0;
531 return -EREMOTEIO;
532 }
533
534 return -EIO;
535}
536
537static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
538 int num)
539{
540 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
541 int i;
542 int ret = 0;
543
544 if (i2c_dev->is_suspended)
545 return -EBUSY;
546
547 clk_enable(i2c_dev->clk);
548 for (i = 0; i < num; i++) {
549 int stop = (i == (num - 1)) ? 1 : 0;
550 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
551 if (ret)
552 break;
553 }
554 clk_disable(i2c_dev->clk);
555 return ret ?: i;
556}
557
558static u32 tegra_i2c_func(struct i2c_adapter *adap)
559{
048e29cf 560 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
db811ca0
CC		 561}
562
563static const struct i2c_algorithm tegra_i2c_algo = {
564 .master_xfer = tegra_i2c_xfer,
565 .functionality = tegra_i2c_func,
566};
567
92891da1 568static int __devinit tegra_i2c_probe(struct platform_device *pdev)
db811ca0
CC		 569{
570 struct tegra_i2c_dev *i2c_dev;
571 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
572 struct resource *res;
573 struct resource *iomem;
574 struct clk *clk;
575 struct clk *i2c_clk;
5c470f39 576 const unsigned int *prop;
f533c61e 577 void __iomem *base;
db811ca0
CC		 578 int irq;
579 int ret = 0;
580
581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
582 if (!res) {
583 dev_err(&pdev->dev, "no mem resource\n");
584 return -EINVAL;
585 }
586 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
587 if (!iomem) {
588 dev_err(&pdev->dev, "I2C region already claimed\n");
589 return -EBUSY;
590 }
591
592 base = ioremap(iomem->start, resource_size(iomem));
593 if (!base) {
594 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
595 return -ENOMEM;
596 }
597
598 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
599 if (!res) {
600 dev_err(&pdev->dev, "no irq resource\n");
601 ret = -EINVAL;
602 goto err_iounmap;
603 }
604 irq = res->start;
605
606 clk = clk_get(&pdev->dev, NULL);
607 if (IS_ERR(clk)) {
608 dev_err(&pdev->dev, "missing controller clock");
609 ret = PTR_ERR(clk);
610 goto err_release_region;
611 }
612
613 i2c_clk = clk_get(&pdev->dev, "i2c");
614 if (IS_ERR(i2c_clk)) {
615 dev_err(&pdev->dev, "missing bus clock");
616 ret = PTR_ERR(i2c_clk);
617 goto err_clk_put;
618 }
619
620 i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
621 if (!i2c_dev) {
622 ret = -ENOMEM;
623 goto err_i2c_clk_put;
624 }
625
626 i2c_dev->base = base;
627 i2c_dev->clk = clk;
628 i2c_dev->i2c_clk = i2c_clk;
629 i2c_dev->iomem = iomem;
630 i2c_dev->adapter.algo = &tegra_i2c_algo;
631 i2c_dev->irq = irq;
632 i2c_dev->cont_id = pdev->id;
633 i2c_dev->dev = &pdev->dev;
5c470f39
JB		 634
635 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
636 if (pdata) {
637 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
638
639 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
640 prop = of_get_property(i2c_dev->dev->of_node,
641 "clock-frequency", NULL);
642 if (prop)
643 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
644 }
db811ca0 645
68fb6695
SW		 646 if (pdev->dev.of_node)
647 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
648 "nvidia,tegra20-i2c-dvc");
649 else if (pdev->id == 3)
db811ca0
CC		 650 i2c_dev->is_dvc = 1;
651 init_completion(&i2c_dev->msg_complete);
652
653 platform_set_drvdata(pdev, i2c_dev);
654
655 ret = tegra_i2c_init(i2c_dev);
656 if (ret) {
657 dev_err(&pdev->dev, "Failed to initialize i2c controller");
658 goto err_free;
659 }
660
661 ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
662 if (ret) {
663 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
664 goto err_free;
665 }
666
667 clk_enable(i2c_dev->i2c_clk);
668
669 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
670 i2c_dev->adapter.owner = THIS_MODULE;
671 i2c_dev->adapter.class = I2C_CLASS_HWMON;
672 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
673 sizeof(i2c_dev->adapter.name));
674 i2c_dev->adapter.algo = &tegra_i2c_algo;
675 i2c_dev->adapter.dev.parent = &pdev->dev;
676 i2c_dev->adapter.nr = pdev->id;
5c470f39 677 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
db811ca0
CC		 678
679 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
680 if (ret) {
681 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
682 goto err_free_irq;
683 }
684
5c470f39
JB		 685 of_i2c_register_devices(&i2c_dev->adapter);
686
db811ca0
CC		 687 return 0;
688err_free_irq:
689 free_irq(i2c_dev->irq, i2c_dev);
690err_free:
691 kfree(i2c_dev);
692err_i2c_clk_put:
693 clk_put(i2c_clk);
694err_clk_put:
695 clk_put(clk);
696err_release_region:
697 release_mem_region(iomem->start, resource_size(iomem));
698err_iounmap:
699 iounmap(base);
700 return ret;
701}
702
92891da1 703static int __devexit tegra_i2c_remove(struct platform_device *pdev)
db811ca0
CC		 704{
705 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
706 i2c_del_adapter(&i2c_dev->adapter);
707 free_irq(i2c_dev->irq, i2c_dev);
708 clk_put(i2c_dev->i2c_clk);
709 clk_put(i2c_dev->clk);
710 release_mem_region(i2c_dev->iomem->start,
711 resource_size(i2c_dev->iomem));
712 iounmap(i2c_dev->base);
713 kfree(i2c_dev);
714 return 0;
715}
716
717#ifdef CONFIG_PM
718static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
719{
720 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
721
722 i2c_lock_adapter(&i2c_dev->adapter);
723 i2c_dev->is_suspended = true;
724 i2c_unlock_adapter(&i2c_dev->adapter);
725
726 return 0;
727}
728
729static int tegra_i2c_resume(struct platform_device *pdev)
730{
731 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
732 int ret;
733
734 i2c_lock_adapter(&i2c_dev->adapter);
735
736 ret = tegra_i2c_init(i2c_dev);
737
738 if (ret) {
739 i2c_unlock_adapter(&i2c_dev->adapter);
740 return ret;
741 }
742
743 i2c_dev->is_suspended = false;
744
745 i2c_unlock_adapter(&i2c_dev->adapter);
746
747 return 0;
748}
749#endif
750
406bd18a
JB		 751#if defined(CONFIG_OF)
752/* Match table for of_platform binding */
753static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
754 { .compatible = "nvidia,tegra20-i2c", },
68fb6695 755 { .compatible = "nvidia,tegra20-i2c-dvc", },
406bd18a
JB		 756 {},
757};
758MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
759#else
760#define tegra_i2c_of_match NULL
761#endif
762
db811ca0
CC		 763static struct platform_driver tegra_i2c_driver = {
764 .probe = tegra_i2c_probe,
218d06d7 765 .remove = __devexit_p(tegra_i2c_remove),
db811ca0
CC		 766#ifdef CONFIG_PM
767 .suspend = tegra_i2c_suspend,
768 .resume = tegra_i2c_resume,
769#endif
770 .driver = {
771 .name = "tegra-i2c",
772 .owner = THIS_MODULE,
406bd18a 773 .of_match_table = tegra_i2c_of_match,
db811ca0
CC		 774 },
775};
776
777static int __init tegra_i2c_init_driver(void)
778{
779 return platform_driver_register(&tegra_i2c_driver);
780}
781
782static void __exit tegra_i2c_exit_driver(void)
783{
784 platform_driver_unregister(&tegra_i2c_driver);
785}
786
787subsys_initcall(tegra_i2c_init_driver);
788module_exit(tegra_i2c_exit_driver);
789
790MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
791MODULE_AUTHOR("Colin Cross");
792MODULE_LICENSE("GPL v2");
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