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db811ca0 CC |
1 | /* |
2 | * drivers/i2c/busses/i2c-tegra.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * Author: Colin Cross <ccross@android.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/i2c-tegra.h> | |
5c470f39 | 29 | #include <linux/of_i2c.h> |
6ad068ed | 30 | #include <linux/of_device.h> |
93cf5d75 | 31 | #include <linux/module.h> |
61fd290d | 32 | #include <linux/clk/tegra.h> |
db811ca0 CC |
33 | |
34 | #include <asm/unaligned.h> | |
35 | ||
db811ca0 CC |
36 | #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
37 | #define BYTES_PER_FIFO_WORD 4 | |
38 | ||
39 | #define I2C_CNFG 0x000 | |
40abcf77 | 40 | #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 |
db811ca0 CC |
41 | #define I2C_CNFG_PACKET_MODE_EN (1<<10) |
42 | #define I2C_CNFG_NEW_MASTER_FSM (1<<11) | |
cb63c62d | 43 | #define I2C_STATUS 0x01C |
db811ca0 | 44 | #define I2C_SL_CNFG 0x020 |
5afa9d35 | 45 | #define I2C_SL_CNFG_NACK (1<<1) |
db811ca0 CC |
46 | #define I2C_SL_CNFG_NEWSL (1<<2) |
47 | #define I2C_SL_ADDR1 0x02c | |
5afa9d35 | 48 | #define I2C_SL_ADDR2 0x030 |
db811ca0 CC |
49 | #define I2C_TX_FIFO 0x050 |
50 | #define I2C_RX_FIFO 0x054 | |
51 | #define I2C_PACKET_TRANSFER_STATUS 0x058 | |
52 | #define I2C_FIFO_CONTROL 0x05c | |
53 | #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) | |
54 | #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) | |
55 | #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 | |
56 | #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 | |
57 | #define I2C_FIFO_STATUS 0x060 | |
58 | #define I2C_FIFO_STATUS_TX_MASK 0xF0 | |
59 | #define I2C_FIFO_STATUS_TX_SHIFT 4 | |
60 | #define I2C_FIFO_STATUS_RX_MASK 0x0F | |
61 | #define I2C_FIFO_STATUS_RX_SHIFT 0 | |
62 | #define I2C_INT_MASK 0x064 | |
63 | #define I2C_INT_STATUS 0x068 | |
64 | #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) | |
65 | #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) | |
66 | #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) | |
67 | #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) | |
68 | #define I2C_INT_NO_ACK (1<<3) | |
69 | #define I2C_INT_ARBITRATION_LOST (1<<2) | |
70 | #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) | |
71 | #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) | |
72 | #define I2C_CLK_DIVISOR 0x06c | |
2a2897ba LD |
73 | #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 |
74 | #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 | |
db811ca0 CC |
75 | |
76 | #define DVC_CTRL_REG1 0x000 | |
77 | #define DVC_CTRL_REG1_INTR_EN (1<<10) | |
78 | #define DVC_CTRL_REG2 0x004 | |
79 | #define DVC_CTRL_REG3 0x008 | |
80 | #define DVC_CTRL_REG3_SW_PROG (1<<26) | |
81 | #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) | |
82 | #define DVC_STATUS 0x00c | |
83 | #define DVC_STATUS_I2C_DONE_INTR (1<<30) | |
84 | ||
85 | #define I2C_ERR_NONE 0x00 | |
86 | #define I2C_ERR_NO_ACK 0x01 | |
87 | #define I2C_ERR_ARBITRATION_LOST 0x02 | |
cb63c62d | 88 | #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 |
db811ca0 CC |
89 | |
90 | #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 | |
91 | #define PACKET_HEADER0_PACKET_ID_SHIFT 16 | |
92 | #define PACKET_HEADER0_CONT_ID_SHIFT 12 | |
93 | #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) | |
94 | ||
95 | #define I2C_HEADER_HIGHSPEED_MODE (1<<22) | |
96 | #define I2C_HEADER_CONT_ON_NAK (1<<21) | |
97 | #define I2C_HEADER_SEND_START_BYTE (1<<20) | |
98 | #define I2C_HEADER_READ (1<<19) | |
99 | #define I2C_HEADER_10BIT_ADDR (1<<18) | |
100 | #define I2C_HEADER_IE_ENABLE (1<<17) | |
101 | #define I2C_HEADER_REPEAT_START (1<<16) | |
c8f5af2f | 102 | #define I2C_HEADER_CONTINUE_XFER (1<<15) |
db811ca0 CC |
103 | #define I2C_HEADER_MASTER_ADDR_SHIFT 12 |
104 | #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 | |
c8f5af2f LD |
105 | /* |
106 | * msg_end_type: The bus control which need to be send at end of transfer. | |
107 | * @MSG_END_STOP: Send stop pulse at end of transfer. | |
108 | * @MSG_END_REPEAT_START: Send repeat start at end of transfer. | |
109 | * @MSG_END_CONTINUE: The following on message is coming and so do not send | |
110 | * stop or repeat start. | |
111 | */ | |
112 | enum msg_end_type { | |
113 | MSG_END_STOP, | |
114 | MSG_END_REPEAT_START, | |
115 | MSG_END_CONTINUE, | |
116 | }; | |
db811ca0 | 117 | |
6ad068ed LD |
118 | /** |
119 | * struct tegra_i2c_hw_feature : Different HW support on Tegra | |
120 | * @has_continue_xfer_support: Continue transfer supports. | |
2a2897ba LD |
121 | * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer |
122 | * complete interrupt per packet basis. | |
123 | * @has_single_clk_source: The i2c controller has single clock source. Tegra30 | |
124 | * and earlier Socs has two clock sources i.e. div-clk and | |
125 | * fast-clk. | |
126 | * @clk_divisor_hs_mode: Clock divisor in HS mode. | |
127 | * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is | |
128 | * applicable if there is no fast clock source i.e. single clock | |
129 | * source. | |
6ad068ed LD |
130 | */ |
131 | ||
132 | struct tegra_i2c_hw_feature { | |
133 | bool has_continue_xfer_support; | |
2a2897ba LD |
134 | bool has_per_pkt_xfer_complete_irq; |
135 | bool has_single_clk_source; | |
136 | int clk_divisor_hs_mode; | |
137 | int clk_divisor_std_fast_mode; | |
6ad068ed LD |
138 | }; |
139 | ||
db811ca0 CC |
140 | /** |
141 | * struct tegra_i2c_dev - per device i2c context | |
142 | * @dev: device reference for power management | |
6ad068ed | 143 | * @hw: Tegra i2c hw feature. |
db811ca0 | 144 | * @adapter: core i2c layer adapter information |
14e92bd4 LD |
145 | * @div_clk: clock reference for div clock of i2c controller. |
146 | * @fast_clk: clock reference for fast clock of i2c controller. | |
db811ca0 CC |
147 | * @base: ioremapped registers cookie |
148 | * @cont_id: i2c controller id, used for for packet header | |
149 | * @irq: irq number of transfer complete interrupt | |
150 | * @is_dvc: identifies the DVC i2c controller, has a different register layout | |
151 | * @msg_complete: transfer completion notifier | |
152 | * @msg_err: error code for completed message | |
153 | * @msg_buf: pointer to current message data | |
154 | * @msg_buf_remaining: size of unsent data in the message buffer | |
155 | * @msg_read: identifies read transfers | |
156 | * @bus_clk_rate: current i2c bus clock rate | |
157 | * @is_suspended: prevents i2c controller accesses after suspend is called | |
158 | */ | |
159 | struct tegra_i2c_dev { | |
160 | struct device *dev; | |
6ad068ed | 161 | const struct tegra_i2c_hw_feature *hw; |
db811ca0 | 162 | struct i2c_adapter adapter; |
14e92bd4 LD |
163 | struct clk *div_clk; |
164 | struct clk *fast_clk; | |
db811ca0 CC |
165 | void __iomem *base; |
166 | int cont_id; | |
167 | int irq; | |
cb63c62d | 168 | bool irq_disabled; |
db811ca0 CC |
169 | int is_dvc; |
170 | struct completion msg_complete; | |
171 | int msg_err; | |
172 | u8 *msg_buf; | |
173 | size_t msg_buf_remaining; | |
174 | int msg_read; | |
175 | unsigned long bus_clk_rate; | |
176 | bool is_suspended; | |
177 | }; | |
178 | ||
179 | static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) | |
180 | { | |
181 | writel(val, i2c_dev->base + reg); | |
182 | } | |
183 | ||
184 | static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |
185 | { | |
186 | return readl(i2c_dev->base + reg); | |
187 | } | |
188 | ||
189 | /* | |
190 | * i2c_writel and i2c_readl will offset the register if necessary to talk | |
191 | * to the I2C block inside the DVC block | |
192 | */ | |
193 | static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, | |
194 | unsigned long reg) | |
195 | { | |
196 | if (i2c_dev->is_dvc) | |
197 | reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; | |
198 | return reg; | |
199 | } | |
200 | ||
201 | static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, | |
202 | unsigned long reg) | |
203 | { | |
204 | writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
ec7aaca2 LD |
205 | |
206 | /* Read back register to make sure that register writes completed */ | |
207 | if (reg != I2C_TX_FIFO) | |
208 | readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
db811ca0 CC |
209 | } |
210 | ||
211 | static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |
212 | { | |
213 | return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
214 | } | |
215 | ||
216 | static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, | |
217 | unsigned long reg, int len) | |
218 | { | |
219 | writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | |
220 | } | |
221 | ||
222 | static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, | |
223 | unsigned long reg, int len) | |
224 | { | |
225 | readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | |
226 | } | |
227 | ||
228 | static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) | |
229 | { | |
230 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); | |
231 | int_mask &= ~mask; | |
232 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); | |
233 | } | |
234 | ||
235 | static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) | |
236 | { | |
237 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); | |
238 | int_mask |= mask; | |
239 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); | |
240 | } | |
241 | ||
242 | static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) | |
243 | { | |
244 | unsigned long timeout = jiffies + HZ; | |
245 | u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); | |
246 | val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; | |
247 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); | |
248 | ||
249 | while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & | |
250 | (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { | |
251 | if (time_after(jiffies, timeout)) { | |
252 | dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); | |
253 | return -ETIMEDOUT; | |
254 | } | |
255 | msleep(1); | |
256 | } | |
257 | return 0; | |
258 | } | |
259 | ||
260 | static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) | |
261 | { | |
262 | u32 val; | |
263 | int rx_fifo_avail; | |
264 | u8 *buf = i2c_dev->msg_buf; | |
265 | size_t buf_remaining = i2c_dev->msg_buf_remaining; | |
266 | int words_to_transfer; | |
267 | ||
268 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); | |
269 | rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> | |
270 | I2C_FIFO_STATUS_RX_SHIFT; | |
271 | ||
272 | /* Rounds down to not include partial word at the end of buf */ | |
273 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | |
274 | if (words_to_transfer > rx_fifo_avail) | |
275 | words_to_transfer = rx_fifo_avail; | |
276 | ||
277 | i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); | |
278 | ||
279 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | |
280 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | |
281 | rx_fifo_avail -= words_to_transfer; | |
282 | ||
283 | /* | |
284 | * If there is a partial word at the end of buf, handle it manually to | |
285 | * prevent overwriting past the end of buf | |
286 | */ | |
287 | if (rx_fifo_avail > 0 && buf_remaining > 0) { | |
288 | BUG_ON(buf_remaining > 3); | |
289 | val = i2c_readl(i2c_dev, I2C_RX_FIFO); | |
290 | memcpy(buf, &val, buf_remaining); | |
291 | buf_remaining = 0; | |
292 | rx_fifo_avail--; | |
293 | } | |
294 | ||
295 | BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); | |
296 | i2c_dev->msg_buf_remaining = buf_remaining; | |
297 | i2c_dev->msg_buf = buf; | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) | |
302 | { | |
303 | u32 val; | |
304 | int tx_fifo_avail; | |
305 | u8 *buf = i2c_dev->msg_buf; | |
306 | size_t buf_remaining = i2c_dev->msg_buf_remaining; | |
307 | int words_to_transfer; | |
308 | ||
309 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); | |
310 | tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> | |
311 | I2C_FIFO_STATUS_TX_SHIFT; | |
312 | ||
313 | /* Rounds down to not include partial word at the end of buf */ | |
314 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | |
db811ca0 | 315 | |
96219c3a DA |
316 | /* It's very common to have < 4 bytes, so optimize that case. */ |
317 | if (words_to_transfer) { | |
318 | if (words_to_transfer > tx_fifo_avail) | |
319 | words_to_transfer = tx_fifo_avail; | |
320 | ||
321 | /* | |
322 | * Update state before writing to FIFO. If this casues us | |
323 | * to finish writing all bytes (AKA buf_remaining goes to 0) we | |
324 | * have a potential for an interrupt (PACKET_XFER_COMPLETE is | |
325 | * not maskable). We need to make sure that the isr sees | |
326 | * buf_remaining as 0 and doesn't call us back re-entrantly. | |
327 | */ | |
328 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | |
329 | tx_fifo_avail -= words_to_transfer; | |
330 | i2c_dev->msg_buf_remaining = buf_remaining; | |
331 | i2c_dev->msg_buf = buf + | |
332 | words_to_transfer * BYTES_PER_FIFO_WORD; | |
333 | barrier(); | |
334 | ||
335 | i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); | |
336 | ||
337 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | |
338 | } | |
db811ca0 CC |
339 | |
340 | /* | |
341 | * If there is a partial word at the end of buf, handle it manually to | |
342 | * prevent reading past the end of buf, which could cross a page | |
343 | * boundary and fault. | |
344 | */ | |
345 | if (tx_fifo_avail > 0 && buf_remaining > 0) { | |
346 | BUG_ON(buf_remaining > 3); | |
347 | memcpy(&val, buf, buf_remaining); | |
96219c3a DA |
348 | |
349 | /* Again update before writing to FIFO to make sure isr sees. */ | |
350 | i2c_dev->msg_buf_remaining = 0; | |
351 | i2c_dev->msg_buf = NULL; | |
352 | barrier(); | |
353 | ||
db811ca0 | 354 | i2c_writel(i2c_dev, val, I2C_TX_FIFO); |
db811ca0 CC |
355 | } |
356 | ||
db811ca0 CC |
357 | return 0; |
358 | } | |
359 | ||
360 | /* | |
361 | * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) | |
362 | * block. This block is identical to the rest of the I2C blocks, except that | |
363 | * it only supports master mode, it has registers moved around, and it needs | |
364 | * some extra init to get it into I2C mode. The register moves are handled | |
365 | * by i2c_readl and i2c_writel | |
366 | */ | |
367 | static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) | |
368 | { | |
369 | u32 val = 0; | |
370 | val = dvc_readl(i2c_dev, DVC_CTRL_REG3); | |
371 | val |= DVC_CTRL_REG3_SW_PROG; | |
372 | val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; | |
373 | dvc_writel(i2c_dev, val, DVC_CTRL_REG3); | |
374 | ||
375 | val = dvc_readl(i2c_dev, DVC_CTRL_REG1); | |
376 | val |= DVC_CTRL_REG1_INTR_EN; | |
377 | dvc_writel(i2c_dev, val, DVC_CTRL_REG1); | |
378 | } | |
379 | ||
fd301cc4 LD |
380 | static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev) |
381 | { | |
382 | int ret; | |
2a2897ba LD |
383 | if (!i2c_dev->hw->has_single_clk_source) { |
384 | ret = clk_prepare_enable(i2c_dev->fast_clk); | |
385 | if (ret < 0) { | |
386 | dev_err(i2c_dev->dev, | |
387 | "Enabling fast clk failed, err %d\n", ret); | |
388 | return ret; | |
389 | } | |
fd301cc4 LD |
390 | } |
391 | ret = clk_prepare_enable(i2c_dev->div_clk); | |
392 | if (ret < 0) { | |
393 | dev_err(i2c_dev->dev, | |
394 | "Enabling div clk failed, err %d\n", ret); | |
395 | clk_disable_unprepare(i2c_dev->fast_clk); | |
396 | } | |
397 | return ret; | |
398 | } | |
399 | ||
400 | static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev) | |
401 | { | |
402 | clk_disable_unprepare(i2c_dev->div_clk); | |
2a2897ba LD |
403 | if (!i2c_dev->hw->has_single_clk_source) |
404 | clk_disable_unprepare(i2c_dev->fast_clk); | |
fd301cc4 LD |
405 | } |
406 | ||
db811ca0 CC |
407 | static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) |
408 | { | |
409 | u32 val; | |
410 | int err = 0; | |
2a2897ba LD |
411 | int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; |
412 | u32 clk_divisor; | |
db811ca0 | 413 | |
132c803f LD |
414 | err = tegra_i2c_clock_enable(i2c_dev); |
415 | if (err < 0) { | |
416 | dev_err(i2c_dev->dev, "Clock enable failed %d\n", err); | |
417 | return err; | |
418 | } | |
db811ca0 | 419 | |
14e92bd4 | 420 | tegra_periph_reset_assert(i2c_dev->div_clk); |
db811ca0 | 421 | udelay(2); |
14e92bd4 | 422 | tegra_periph_reset_deassert(i2c_dev->div_clk); |
db811ca0 CC |
423 | |
424 | if (i2c_dev->is_dvc) | |
425 | tegra_dvc_init(i2c_dev); | |
426 | ||
40abcf77 JC |
427 | val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | |
428 | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); | |
db811ca0 CC |
429 | i2c_writel(i2c_dev, val, I2C_CNFG); |
430 | i2c_writel(i2c_dev, 0, I2C_INT_MASK); | |
2a2897ba LD |
431 | |
432 | clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1); | |
433 | clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier); | |
434 | ||
435 | /* Make sure clock divisor programmed correctly */ | |
436 | clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; | |
437 | clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode << | |
438 | I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; | |
439 | i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); | |
db811ca0 | 440 | |
65a1a0ac KW |
441 | if (!i2c_dev->is_dvc) { |
442 | u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); | |
5afa9d35 SW |
443 | sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; |
444 | i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); | |
445 | i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); | |
446 | i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); | |
447 | ||
65a1a0ac KW |
448 | } |
449 | ||
db811ca0 CC |
450 | val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | |
451 | 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; | |
452 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); | |
453 | ||
454 | if (tegra_i2c_flush_fifos(i2c_dev)) | |
455 | err = -ETIMEDOUT; | |
456 | ||
fd301cc4 | 457 | tegra_i2c_clock_disable(i2c_dev); |
cb63c62d TP |
458 | |
459 | if (i2c_dev->irq_disabled) { | |
460 | i2c_dev->irq_disabled = 0; | |
461 | enable_irq(i2c_dev->irq); | |
462 | } | |
463 | ||
db811ca0 CC |
464 | return err; |
465 | } | |
466 | ||
467 | static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) | |
468 | { | |
469 | u32 status; | |
470 | const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; | |
471 | struct tegra_i2c_dev *i2c_dev = dev_id; | |
472 | ||
473 | status = i2c_readl(i2c_dev, I2C_INT_STATUS); | |
474 | ||
475 | if (status == 0) { | |
cb63c62d TP |
476 | dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", |
477 | i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), | |
478 | i2c_readl(i2c_dev, I2C_STATUS), | |
479 | i2c_readl(i2c_dev, I2C_CNFG)); | |
480 | i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; | |
481 | ||
482 | if (!i2c_dev->irq_disabled) { | |
483 | disable_irq_nosync(i2c_dev->irq); | |
484 | i2c_dev->irq_disabled = 1; | |
485 | } | |
cb63c62d | 486 | goto err; |
db811ca0 CC |
487 | } |
488 | ||
489 | if (unlikely(status & status_err)) { | |
490 | if (status & I2C_INT_NO_ACK) | |
491 | i2c_dev->msg_err |= I2C_ERR_NO_ACK; | |
492 | if (status & I2C_INT_ARBITRATION_LOST) | |
493 | i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; | |
db811ca0 CC |
494 | goto err; |
495 | } | |
496 | ||
497 | if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { | |
498 | if (i2c_dev->msg_buf_remaining) | |
499 | tegra_i2c_empty_rx_fifo(i2c_dev); | |
500 | else | |
501 | BUG(); | |
502 | } | |
503 | ||
504 | if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { | |
505 | if (i2c_dev->msg_buf_remaining) | |
506 | tegra_i2c_fill_tx_fifo(i2c_dev); | |
507 | else | |
508 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); | |
509 | } | |
510 | ||
c889e91d LD |
511 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); |
512 | if (i2c_dev->is_dvc) | |
513 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); | |
514 | ||
96219c3a DA |
515 | if (status & I2C_INT_PACKET_XFER_COMPLETE) { |
516 | BUG_ON(i2c_dev->msg_buf_remaining); | |
db811ca0 | 517 | complete(&i2c_dev->msg_complete); |
96219c3a | 518 | } |
db811ca0 CC |
519 | return IRQ_HANDLED; |
520 | err: | |
25985edc | 521 | /* An error occurred, mask all interrupts */ |
db811ca0 CC |
522 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | |
523 | I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | | |
524 | I2C_INT_RX_FIFO_DATA_REQ); | |
525 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); | |
cb63c62d TP |
526 | if (i2c_dev->is_dvc) |
527 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); | |
c889e91d LD |
528 | |
529 | complete(&i2c_dev->msg_complete); | |
db811ca0 CC |
530 | return IRQ_HANDLED; |
531 | } | |
532 | ||
533 | static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, | |
c8f5af2f | 534 | struct i2c_msg *msg, enum msg_end_type end_state) |
db811ca0 CC |
535 | { |
536 | u32 packet_header; | |
537 | u32 int_mask; | |
538 | int ret; | |
539 | ||
540 | tegra_i2c_flush_fifos(i2c_dev); | |
db811ca0 CC |
541 | |
542 | if (msg->len == 0) | |
543 | return -EINVAL; | |
544 | ||
545 | i2c_dev->msg_buf = msg->buf; | |
546 | i2c_dev->msg_buf_remaining = msg->len; | |
547 | i2c_dev->msg_err = I2C_ERR_NONE; | |
548 | i2c_dev->msg_read = (msg->flags & I2C_M_RD); | |
549 | INIT_COMPLETION(i2c_dev->msg_complete); | |
550 | ||
551 | packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | | |
552 | PACKET_HEADER0_PROTOCOL_I2C | | |
553 | (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | | |
554 | (1 << PACKET_HEADER0_PACKET_ID_SHIFT); | |
555 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
556 | ||
557 | packet_header = msg->len - 1; | |
558 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
559 | ||
353f56b5 | 560 | packet_header = I2C_HEADER_IE_ENABLE; |
c8f5af2f LD |
561 | if (end_state == MSG_END_CONTINUE) |
562 | packet_header |= I2C_HEADER_CONTINUE_XFER; | |
563 | else if (end_state == MSG_END_REPEAT_START) | |
2078cf3b | 564 | packet_header |= I2C_HEADER_REPEAT_START; |
353f56b5 LD |
565 | if (msg->flags & I2C_M_TEN) { |
566 | packet_header |= msg->addr; | |
db811ca0 | 567 | packet_header |= I2C_HEADER_10BIT_ADDR; |
353f56b5 LD |
568 | } else { |
569 | packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; | |
570 | } | |
db811ca0 CC |
571 | if (msg->flags & I2C_M_IGNORE_NAK) |
572 | packet_header |= I2C_HEADER_CONT_ON_NAK; | |
db811ca0 CC |
573 | if (msg->flags & I2C_M_RD) |
574 | packet_header |= I2C_HEADER_READ; | |
575 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
576 | ||
577 | if (!(msg->flags & I2C_M_RD)) | |
578 | tegra_i2c_fill_tx_fifo(i2c_dev); | |
579 | ||
580 | int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; | |
2a2897ba LD |
581 | if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) |
582 | int_mask |= I2C_INT_PACKET_XFER_COMPLETE; | |
db811ca0 CC |
583 | if (msg->flags & I2C_M_RD) |
584 | int_mask |= I2C_INT_RX_FIFO_DATA_REQ; | |
585 | else if (i2c_dev->msg_buf_remaining) | |
586 | int_mask |= I2C_INT_TX_FIFO_DATA_REQ; | |
587 | tegra_i2c_unmask_irq(i2c_dev, int_mask); | |
588 | dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", | |
589 | i2c_readl(i2c_dev, I2C_INT_MASK)); | |
590 | ||
591 | ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT); | |
592 | tegra_i2c_mask_irq(i2c_dev, int_mask); | |
593 | ||
58823c72 | 594 | if (ret == 0) { |
db811ca0 CC |
595 | dev_err(i2c_dev->dev, "i2c transfer timed out\n"); |
596 | ||
597 | tegra_i2c_init(i2c_dev); | |
598 | return -ETIMEDOUT; | |
599 | } | |
600 | ||
601 | dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n", | |
602 | ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err); | |
603 | ||
604 | if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) | |
605 | return 0; | |
606 | ||
f70893d0 AC |
607 | /* |
608 | * NACK interrupt is generated before the I2C controller generates the | |
609 | * STOP condition on the bus. So wait for 2 clock periods before resetting | |
610 | * the controller so that STOP condition has been delivered properly. | |
611 | */ | |
612 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) | |
613 | udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); | |
614 | ||
db811ca0 CC |
615 | tegra_i2c_init(i2c_dev); |
616 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { | |
617 | if (msg->flags & I2C_M_IGNORE_NAK) | |
618 | return 0; | |
619 | return -EREMOTEIO; | |
620 | } | |
621 | ||
622 | return -EIO; | |
623 | } | |
624 | ||
625 | static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |
626 | int num) | |
627 | { | |
628 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); | |
629 | int i; | |
630 | int ret = 0; | |
631 | ||
632 | if (i2c_dev->is_suspended) | |
633 | return -EBUSY; | |
634 | ||
132c803f LD |
635 | ret = tegra_i2c_clock_enable(i2c_dev); |
636 | if (ret < 0) { | |
637 | dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret); | |
638 | return ret; | |
639 | } | |
640 | ||
db811ca0 | 641 | for (i = 0; i < num; i++) { |
c8f5af2f LD |
642 | enum msg_end_type end_type = MSG_END_STOP; |
643 | if (i < (num - 1)) { | |
644 | if (msgs[i + 1].flags & I2C_M_NOSTART) | |
645 | end_type = MSG_END_CONTINUE; | |
646 | else | |
647 | end_type = MSG_END_REPEAT_START; | |
648 | } | |
649 | ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); | |
db811ca0 CC |
650 | if (ret) |
651 | break; | |
652 | } | |
fd301cc4 | 653 | tegra_i2c_clock_disable(i2c_dev); |
db811ca0 CC |
654 | return ret ?: i; |
655 | } | |
656 | ||
657 | static u32 tegra_i2c_func(struct i2c_adapter *adap) | |
658 | { | |
6ad068ed LD |
659 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
660 | u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | | |
661 | I2C_FUNC_PROTOCOL_MANGLING; | |
662 | ||
663 | if (i2c_dev->hw->has_continue_xfer_support) | |
664 | ret |= I2C_FUNC_NOSTART; | |
665 | return ret; | |
db811ca0 CC |
666 | } |
667 | ||
668 | static const struct i2c_algorithm tegra_i2c_algo = { | |
669 | .master_xfer = tegra_i2c_xfer, | |
670 | .functionality = tegra_i2c_func, | |
671 | }; | |
672 | ||
6ad068ed LD |
673 | static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { |
674 | .has_continue_xfer_support = false, | |
2a2897ba LD |
675 | .has_per_pkt_xfer_complete_irq = false, |
676 | .has_single_clk_source = false, | |
677 | .clk_divisor_hs_mode = 3, | |
678 | .clk_divisor_std_fast_mode = 0, | |
6ad068ed LD |
679 | }; |
680 | ||
681 | static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { | |
682 | .has_continue_xfer_support = true, | |
2a2897ba LD |
683 | .has_per_pkt_xfer_complete_irq = false, |
684 | .has_single_clk_source = false, | |
685 | .clk_divisor_hs_mode = 3, | |
686 | .clk_divisor_std_fast_mode = 0, | |
687 | }; | |
688 | ||
689 | static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { | |
690 | .has_continue_xfer_support = true, | |
691 | .has_per_pkt_xfer_complete_irq = true, | |
692 | .has_single_clk_source = true, | |
693 | .clk_divisor_hs_mode = 1, | |
694 | .clk_divisor_std_fast_mode = 0x19, | |
6ad068ed LD |
695 | }; |
696 | ||
697 | #if defined(CONFIG_OF) | |
698 | /* Match table for of_platform binding */ | |
0b255e92 | 699 | static const struct of_device_id tegra_i2c_of_match[] = { |
2a2897ba | 700 | { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, |
6ad068ed LD |
701 | { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, |
702 | { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, | |
703 | { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, | |
704 | {}, | |
705 | }; | |
706 | MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); | |
707 | #endif | |
708 | ||
0b255e92 | 709 | static int tegra_i2c_probe(struct platform_device *pdev) |
db811ca0 CC |
710 | { |
711 | struct tegra_i2c_dev *i2c_dev; | |
712 | struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data; | |
713 | struct resource *res; | |
14e92bd4 LD |
714 | struct clk *div_clk; |
715 | struct clk *fast_clk; | |
5c470f39 | 716 | const unsigned int *prop; |
f533c61e | 717 | void __iomem *base; |
db811ca0 CC |
718 | int irq; |
719 | int ret = 0; | |
720 | ||
721 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
722 | if (!res) { | |
723 | dev_err(&pdev->dev, "no mem resource\n"); | |
724 | return -EINVAL; | |
725 | } | |
db811ca0 | 726 | |
84dbf809 TR |
727 | base = devm_ioremap_resource(&pdev->dev, res); |
728 | if (IS_ERR(base)) | |
729 | return PTR_ERR(base); | |
db811ca0 CC |
730 | |
731 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
732 | if (!res) { | |
733 | dev_err(&pdev->dev, "no irq resource\n"); | |
9cbb6b2b | 734 | return -EINVAL; |
db811ca0 CC |
735 | } |
736 | irq = res->start; | |
737 | ||
14e92bd4 LD |
738 | div_clk = devm_clk_get(&pdev->dev, "div-clk"); |
739 | if (IS_ERR(div_clk)) { | |
db811ca0 | 740 | dev_err(&pdev->dev, "missing controller clock"); |
14e92bd4 | 741 | return PTR_ERR(div_clk); |
db811ca0 CC |
742 | } |
743 | ||
9cbb6b2b | 744 | i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); |
db811ca0 | 745 | if (!i2c_dev) { |
9cbb6b2b LD |
746 | dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev"); |
747 | return -ENOMEM; | |
db811ca0 CC |
748 | } |
749 | ||
750 | i2c_dev->base = base; | |
14e92bd4 | 751 | i2c_dev->div_clk = div_clk; |
db811ca0 CC |
752 | i2c_dev->adapter.algo = &tegra_i2c_algo; |
753 | i2c_dev->irq = irq; | |
754 | i2c_dev->cont_id = pdev->id; | |
755 | i2c_dev->dev = &pdev->dev; | |
5c470f39 JB |
756 | |
757 | i2c_dev->bus_clk_rate = 100000; /* default clock rate */ | |
758 | if (pdata) { | |
759 | i2c_dev->bus_clk_rate = pdata->bus_clk_rate; | |
760 | ||
761 | } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */ | |
762 | prop = of_get_property(i2c_dev->dev->of_node, | |
763 | "clock-frequency", NULL); | |
764 | if (prop) | |
765 | i2c_dev->bus_clk_rate = be32_to_cpup(prop); | |
766 | } | |
db811ca0 | 767 | |
6ad068ed LD |
768 | i2c_dev->hw = &tegra20_i2c_hw; |
769 | ||
770 | if (pdev->dev.of_node) { | |
771 | const struct of_device_id *match; | |
772 | match = of_match_device(of_match_ptr(tegra_i2c_of_match), | |
773 | &pdev->dev); | |
774 | i2c_dev->hw = match->data; | |
68fb6695 SW |
775 | i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, |
776 | "nvidia,tegra20-i2c-dvc"); | |
6ad068ed | 777 | } else if (pdev->id == 3) { |
db811ca0 | 778 | i2c_dev->is_dvc = 1; |
6ad068ed | 779 | } |
db811ca0 CC |
780 | init_completion(&i2c_dev->msg_complete); |
781 | ||
2a2897ba LD |
782 | if (!i2c_dev->hw->has_single_clk_source) { |
783 | fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); | |
784 | if (IS_ERR(fast_clk)) { | |
785 | dev_err(&pdev->dev, "missing fast clock"); | |
786 | return PTR_ERR(fast_clk); | |
787 | } | |
788 | i2c_dev->fast_clk = fast_clk; | |
789 | } | |
790 | ||
db811ca0 CC |
791 | platform_set_drvdata(pdev, i2c_dev); |
792 | ||
793 | ret = tegra_i2c_init(i2c_dev); | |
794 | if (ret) { | |
795 | dev_err(&pdev->dev, "Failed to initialize i2c controller"); | |
9cbb6b2b | 796 | return ret; |
db811ca0 CC |
797 | } |
798 | ||
9cbb6b2b | 799 | ret = devm_request_irq(&pdev->dev, i2c_dev->irq, |
91b370a0 | 800 | tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); |
db811ca0 CC |
801 | if (ret) { |
802 | dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); | |
9cbb6b2b | 803 | return ret; |
db811ca0 CC |
804 | } |
805 | ||
db811ca0 CC |
806 | i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); |
807 | i2c_dev->adapter.owner = THIS_MODULE; | |
808 | i2c_dev->adapter.class = I2C_CLASS_HWMON; | |
809 | strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", | |
810 | sizeof(i2c_dev->adapter.name)); | |
811 | i2c_dev->adapter.algo = &tegra_i2c_algo; | |
812 | i2c_dev->adapter.dev.parent = &pdev->dev; | |
813 | i2c_dev->adapter.nr = pdev->id; | |
5c470f39 | 814 | i2c_dev->adapter.dev.of_node = pdev->dev.of_node; |
db811ca0 CC |
815 | |
816 | ret = i2c_add_numbered_adapter(&i2c_dev->adapter); | |
817 | if (ret) { | |
818 | dev_err(&pdev->dev, "Failed to add I2C adapter\n"); | |
9cbb6b2b | 819 | return ret; |
db811ca0 CC |
820 | } |
821 | ||
5c470f39 JB |
822 | of_i2c_register_devices(&i2c_dev->adapter); |
823 | ||
db811ca0 | 824 | return 0; |
db811ca0 CC |
825 | } |
826 | ||
0b255e92 | 827 | static int tegra_i2c_remove(struct platform_device *pdev) |
db811ca0 CC |
828 | { |
829 | struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); | |
830 | i2c_del_adapter(&i2c_dev->adapter); | |
db811ca0 CC |
831 | return 0; |
832 | } | |
833 | ||
371e67c9 | 834 | #ifdef CONFIG_PM_SLEEP |
5db20c49 | 835 | static int tegra_i2c_suspend(struct device *dev) |
db811ca0 | 836 | { |
6a7b3c3c | 837 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
db811ca0 CC |
838 | |
839 | i2c_lock_adapter(&i2c_dev->adapter); | |
840 | i2c_dev->is_suspended = true; | |
841 | i2c_unlock_adapter(&i2c_dev->adapter); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
5db20c49 | 846 | static int tegra_i2c_resume(struct device *dev) |
db811ca0 | 847 | { |
6a7b3c3c | 848 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
db811ca0 CC |
849 | int ret; |
850 | ||
851 | i2c_lock_adapter(&i2c_dev->adapter); | |
852 | ||
853 | ret = tegra_i2c_init(i2c_dev); | |
854 | ||
855 | if (ret) { | |
856 | i2c_unlock_adapter(&i2c_dev->adapter); | |
857 | return ret; | |
858 | } | |
859 | ||
860 | i2c_dev->is_suspended = false; | |
861 | ||
862 | i2c_unlock_adapter(&i2c_dev->adapter); | |
863 | ||
864 | return 0; | |
865 | } | |
6a7b3c3c | 866 | |
5db20c49 | 867 | static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume); |
6a7b3c3c RW |
868 | #define TEGRA_I2C_PM (&tegra_i2c_pm) |
869 | #else | |
870 | #define TEGRA_I2C_PM NULL | |
db811ca0 CC |
871 | #endif |
872 | ||
873 | static struct platform_driver tegra_i2c_driver = { | |
874 | .probe = tegra_i2c_probe, | |
0b255e92 | 875 | .remove = tegra_i2c_remove, |
db811ca0 CC |
876 | .driver = { |
877 | .name = "tegra-i2c", | |
878 | .owner = THIS_MODULE, | |
02d8bf8d | 879 | .of_match_table = of_match_ptr(tegra_i2c_of_match), |
6a7b3c3c | 880 | .pm = TEGRA_I2C_PM, |
db811ca0 CC |
881 | }, |
882 | }; | |
883 | ||
884 | static int __init tegra_i2c_init_driver(void) | |
885 | { | |
886 | return platform_driver_register(&tegra_i2c_driver); | |
887 | } | |
888 | ||
889 | static void __exit tegra_i2c_exit_driver(void) | |
890 | { | |
891 | platform_driver_unregister(&tegra_i2c_driver); | |
892 | } | |
893 | ||
894 | subsys_initcall(tegra_i2c_init_driver); | |
895 | module_exit(tegra_i2c_exit_driver); | |
896 | ||
897 | MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); | |
898 | MODULE_AUTHOR("Colin Cross"); | |
899 | MODULE_LICENSE("GPL v2"); |