[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-xiic.c

/*
 * i2c-xiic.c
 * Copyright (c) 2002-2007 Xilinx Inc.
 * Copyright (c) 2009-2010 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 * This code was implemented by Mocean Laboratories AB when porting linux
 * to the automotive development board Russellville. The copyright holder
 * as seen in the header is Intel corporation.
 * Mocean Laboratories forked off the GNU/Linux platform work into a
 * separate company called Pelagicore AB, which committed the code to the
 * kernel.
 */

/* Supports:
 * Xilinx IIC
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-xiic.h>
#include <linux/io.h>
#include <linux/slab.h>

#define DRIVER_NAME "xiic-i2c"

enum xilinx_i2c_state {
	STATE_DONE,
	STATE_ERROR,
	STATE_START
};

/**
 * struct xiic_i2c - Internal representation of the XIIC I2C bus
 * @base:	Memory base of the HW registers
 * @wait:	Wait queue for callers
 * @adap:	Kernel adapter representation
 * @tx_msg:	Messages from above to be sent
 * @lock:	Mutual exclusion
 * @tx_pos:	Current pos in TX message
 * @nmsgs:	Number of messages in tx_msg
 * @state:	See STATE_
 * @rx_msg:	Current RX message
 * @rx_pos:	Position within current RX message
 */
struct xiic_i2c {
	void __iomem		*base;
	wait_queue_head_t	wait;
	struct i2c_adapter	adap;
	struct i2c_msg		*tx_msg;
	spinlock_t		lock;
	unsigned int 		tx_pos;
	unsigned int		nmsgs;
	enum xilinx_i2c_state	state;
	struct i2c_msg		*rx_msg;
	int			rx_pos;
};


#define XIIC_MSB_OFFSET 0
#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)

/*
 * Register offsets in bytes from RegisterBase. Three is added to the
 * base offset to access LSB (IBM style) of the word
 */
#define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET)	/* Control Register   */
#define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET)	/* Status Register    */
#define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)	/* Data Tx Register   */
#define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)	/* Data Rx Register   */
#define XIIC_ADR_REG_OFFSET  (0x10+XIIC_REG_OFFSET)	/* Address Register   */
#define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)	/* Tx FIFO Occupancy  */
#define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)	/* Rx FIFO Occupancy  */
#define XIIC_TBA_REG_OFFSET  (0x1C+XIIC_REG_OFFSET)	/* 10 Bit Address reg */
#define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)	/* Rx FIFO Depth reg  */
#define XIIC_GPO_REG_OFFSET  (0x24+XIIC_REG_OFFSET)	/* Output Register    */

/* Control Register masks */
#define XIIC_CR_ENABLE_DEVICE_MASK        0x01	/* Device enable = 1      */
#define XIIC_CR_TX_FIFO_RESET_MASK        0x02	/* Transmit FIFO reset=1  */
#define XIIC_CR_MSMS_MASK                 0x04	/* Master starts Txing=1  */
#define XIIC_CR_DIR_IS_TX_MASK            0x08	/* Dir of tx. Txing=1     */
#define XIIC_CR_NO_ACK_MASK               0x10	/* Tx Ack. NO ack = 1     */
#define XIIC_CR_REPEATED_START_MASK       0x20	/* Repeated start = 1     */
#define XIIC_CR_GENERAL_CALL_MASK         0x40	/* Gen Call enabled = 1   */

/* Status Register masks */
#define XIIC_SR_GEN_CALL_MASK             0x01	/* 1=a mstr issued a GC   */
#define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02	/* 1=when addr as slave   */
#define XIIC_SR_BUS_BUSY_MASK             0x04	/* 1 = bus is busy        */
#define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08	/* 1=Dir: mstr <-- slave  */
#define XIIC_SR_TX_FIFO_FULL_MASK         0x10	/* 1 = Tx FIFO full       */
#define XIIC_SR_RX_FIFO_FULL_MASK         0x20	/* 1 = Rx FIFO full       */
#define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40	/* 1 = Rx FIFO empty      */
#define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80	/* 1 = Tx FIFO empty      */

/* Interrupt Status Register masks    Interrupt occurs when...       */
#define XIIC_INTR_ARB_LOST_MASK           0x01	/* 1 = arbitration lost   */
#define XIIC_INTR_TX_ERROR_MASK           0x02	/* 1=Tx error/msg complete */
#define XIIC_INTR_TX_EMPTY_MASK           0x04	/* 1 = Tx FIFO/reg empty  */
#define XIIC_INTR_RX_FULL_MASK            0x08	/* 1=Rx FIFO/reg=OCY level */
#define XIIC_INTR_BNB_MASK                0x10	/* 1 = Bus not busy       */
#define XIIC_INTR_AAS_MASK                0x20	/* 1 = when addr as slave */
#define XIIC_INTR_NAAS_MASK               0x40	/* 1 = not addr as slave  */
#define XIIC_INTR_TX_HALF_MASK            0x80	/* 1 = TX FIFO half empty */

/* The following constants specify the depth of the FIFOs */
#define IIC_RX_FIFO_DEPTH         16	/* Rx fifo capacity               */
#define IIC_TX_FIFO_DEPTH         16	/* Tx fifo capacity               */

/* The following constants specify groups of interrupts that are typically
 * enabled or disables at the same time
 */
#define XIIC_TX_INTERRUPTS                           \
(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)

#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)

/* The following constants are used with the following macros to specify the
 * operation, a read or write operation.
 */
#define XIIC_READ_OPERATION  1
#define XIIC_WRITE_OPERATION 0

/*
 * Tx Fifo upper bit masks.
 */
#define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
#define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */

/*
 * The following constants define the register offsets for the Interrupt
 * registers. There are some holes in the memory map for reserved addresses
 * to allow other registers to be added and still match the memory map of the
 * interrupt controller registers
 */
#define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
#define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
#define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
#define XIIC_RESETR_OFFSET   0x40 /* Reset Register */

#define XIIC_RESET_MASK             0xAUL

/*
 * The following constant is used for the device global interrupt enable
 * register, to enable all interrupts for the device, this is the only bit
 * in the register
 */
#define XIIC_GINTR_ENABLE_MASK      0x80000000UL

#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)

static void xiic_start_xfer(struct xiic_i2c *i2c);
static void __xiic_start_xfer(struct xiic_i2c *i2c);

static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
{
	iowrite8(value, i2c->base + reg);
}

static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
{
	return ioread8(i2c->base + reg);
}

static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
{
	iowrite16(value, i2c->base + reg);
}

static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
{
	iowrite32(value, i2c->base + reg);
}

static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
{
	return ioread32(i2c->base + reg);
}

static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
{
	u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
	xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
}

static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
{
	u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
	xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
}

static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
{
	u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
	xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
}

static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
{
	xiic_irq_clr(i2c, mask);
	xiic_irq_en(i2c, mask);
}

static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
{
	u8 sr;
	for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
		!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
		sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
		xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
}

static void xiic_reinit(struct xiic_i2c *i2c)
{
	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);

	/* Set receive Fifo depth to maximum (zero based). */
	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);

	/* Reset Tx Fifo. */
	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);

	/* Enable IIC Device, remove Tx Fifo reset & disable general call. */
	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);

	/* make sure RX fifo is empty */
	xiic_clear_rx_fifo(i2c);

	/* Enable interrupts */
	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);

	xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
}

static void xiic_deinit(struct xiic_i2c *i2c)
{
	u8 cr;

	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);

	/* Disable IIC Device. */
	cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
}

static void xiic_read_rx(struct xiic_i2c *i2c)
{
	u8 bytes_in_fifo;
	int i;

	bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;

	dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
		", SR: 0x%x, CR: 0x%x\n",
		__func__, bytes_in_fifo, xiic_rx_space(i2c),
		xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
		xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));

	if (bytes_in_fifo > xiic_rx_space(i2c))
		bytes_in_fifo = xiic_rx_space(i2c);

	for (i = 0; i < bytes_in_fifo; i++)
		i2c->rx_msg->buf[i2c->rx_pos++] =
			xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);

	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
		(xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
		IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);
}

static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
{
	/* return the actual space left in the FIFO */
	return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
}

static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
{
	u8 fifo_space = xiic_tx_fifo_space(i2c);
	int len = xiic_tx_space(i2c);

	len = (len > fifo_space) ? fifo_space : len;

	dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
		__func__, len, fifo_space);

	while (len--) {
		u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
		if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
			/* last message in transfer -> STOP */
			data |= XIIC_TX_DYN_STOP_MASK;
			dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);

			xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
		} else
			xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data);
	}
}

static void xiic_wakeup(struct xiic_i2c *i2c, int code)
{
	i2c->tx_msg = NULL;
	i2c->rx_msg = NULL;
	i2c->nmsgs = 0;
	i2c->state = code;
	wake_up(&i2c->wait);
}

static void xiic_process(struct xiic_i2c *i2c)
{
	u32 pend, isr, ier;
	u32 clr = 0;

	/* Get the interrupt Status from the IPIF. There is no clearing of
	 * interrupts in the IPIF. Interrupts must be cleared at the source.
	 * To find which interrupts are pending; AND interrupts pending with
	 * interrupts masked.
	 */
	isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
	ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
	pend = isr & ier;

	dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
		"pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
		__func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
		i2c->tx_msg, i2c->nmsgs);

	/* Do not processes a devices interrupts if the device has no
	 * interrupts pending
	 */
	if (!pend)
		return;

	/* Service requesting interrupt */
	if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
		((pend & XIIC_INTR_TX_ERROR_MASK) &&
		!(pend & XIIC_INTR_RX_FULL_MASK))) {
		/* bus arbritration lost, or...
		 * Transmit error _OR_ RX completed
		 * if this happens when RX_FULL is not set
		 * this is probably a TX error
		 */

		dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);

		/* dynamic mode seem to suffer from problems if we just flushes
		 * fifos and the next message is a TX with len 0 (only addr)
		 * reset the IP instead of just flush fifos
		 */
		xiic_reinit(i2c);

		if (i2c->tx_msg)
			xiic_wakeup(i2c, STATE_ERROR);

	} else if (pend & XIIC_INTR_RX_FULL_MASK) {
		/* Receive register/FIFO is full */

		clr = XIIC_INTR_RX_FULL_MASK;
		if (!i2c->rx_msg) {
			dev_dbg(i2c->adap.dev.parent,
				"%s unexpexted RX IRQ\n", __func__);
			xiic_clear_rx_fifo(i2c);
			goto out;
		}

		xiic_read_rx(i2c);
		if (xiic_rx_space(i2c) == 0) {
			/* this is the last part of the message */
			i2c->rx_msg = NULL;

			/* also clear TX error if there (RX complete) */
			clr |= (isr & XIIC_INTR_TX_ERROR_MASK);

			dev_dbg(i2c->adap.dev.parent,
				"%s end of message, nmsgs: %d\n",
				__func__, i2c->nmsgs);

			/* send next message if this wasn't the last,
			 * otherwise the transfer will be finialise when
			 * receiving the bus not busy interrupt
			 */
			if (i2c->nmsgs > 1) {
				i2c->nmsgs--;
				i2c->tx_msg++;
				dev_dbg(i2c->adap.dev.parent,
					"%s will start next...\n", __func__);

				__xiic_start_xfer(i2c);
			}
		}
	} else if (pend & XIIC_INTR_BNB_MASK) {
		/* IIC bus has transitioned to not busy */
		clr = XIIC_INTR_BNB_MASK;

		/* The bus is not busy, disable BusNotBusy interrupt */
		xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);

		if (!i2c->tx_msg)
			goto out;

		if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
			xiic_tx_space(i2c) == 0)
			xiic_wakeup(i2c, STATE_DONE);
		else
			xiic_wakeup(i2c, STATE_ERROR);

	} else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
Commit	Line	Data
e1d5b659 RR	1	/*
	2	* i2c-xiic.c
	3	* Copyright (c) 2002-2007 Xilinx Inc.
	4	* Copyright (c) 2009-2010 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*
	19	*
	20	* This code was implemented by Mocean Laboratories AB when porting linux
	21	* to the automotive development board Russellville. The copyright holder
	22	* as seen in the header is Intel corporation.
	23	* Mocean Laboratories forked off the GNU/Linux platform work into a
25985edc	24	* separate company called Pelagicore AB, which committed the code to the
e1d5b659 RR	25	* kernel.
	26	*/
	27
	28	/* Supports:
	29	* Xilinx IIC
	30	*/
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
	33	#include <linux/init.h>
	34	#include <linux/errno.h>
02ca6c40	35	#include <linux/delay.h>
e1d5b659	36	#include <linux/platform_device.h>
e46dccff	37	#include <linux/mfd/core.h>
e1d5b659 RR	38	#include <linux/i2c.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/wait.h>
	41	#include <linux/i2c-xiic.h>
	42	#include <linux/io.h>
5a0e3ad6	43	#include <linux/slab.h>
e1d5b659 RR	44
	45	#define DRIVER_NAME "xiic-i2c"
	46
	47	enum xilinx_i2c_state {
	48	STATE_DONE,
	49	STATE_ERROR,
	50	STATE_START
	51	};
	52
	53	/**
	54	* struct xiic_i2c - Internal representation of the XIIC I2C bus
	55	* @base: Memory base of the HW registers
	56	* @wait: Wait queue for callers
	57	* @adap: Kernel adapter representation
	58	* @tx_msg: Messages from above to be sent
	59	* @lock: Mutual exclusion
	60	* @tx_pos: Current pos in TX message
	61	* @nmsgs: Number of messages in tx_msg
	62	* @state: See STATE_
	63	* @rx_msg: Current RX message
	64	* @rx_pos: Position within current RX message
	65	*/
	66	struct xiic_i2c {
	67	void __iomem *base;
	68	wait_queue_head_t wait;
	69	struct i2c_adapter adap;
	70	struct i2c_msg *tx_msg;
	71	spinlock_t lock;
	72	unsigned int tx_pos;
	73	unsigned int nmsgs;
	74	enum xilinx_i2c_state state;
	75	struct i2c_msg *rx_msg;
	76	int rx_pos;
	77	};
	78
	79
	80	#define XIIC_MSB_OFFSET 0
	81	#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
	82
	83	/*
	84	* Register offsets in bytes from RegisterBase. Three is added to the
	85	* base offset to access LSB (IBM style) of the word
	86	*/
	87	#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
	88	#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
	89	#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
	90	#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
	91	#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
	92	#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
	93	#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
	94	#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
	95	#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
	96	#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
	97
	98	/* Control Register masks */
	99	#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
	100	#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
	101	#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
	102	#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
	103	#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
	104	#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
	105	#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
	106
	107	/* Status Register masks */
108	#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
109	#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
110	#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
111	#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
112	#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
113	#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
114	#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
115	#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
116
117	/* Interrupt Status Register masks Interrupt occurs when... */
118	#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
119	#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
120	#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
121	#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
122	#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
123	#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
124	#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
125	#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
126
127	/* The following constants specify the depth of the FIFOs */
128	#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
129	#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
130
131	/* The following constants specify groups of interrupts that are typically
132	* enabled or disables at the same time
133	*/
134	#define XIIC_TX_INTERRUPTS \
135	(XIIC_INTR_TX_ERROR_MASK \| XIIC_INTR_TX_EMPTY_MASK \| XIIC_INTR_TX_HALF_MASK)
136
137	#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK \| XIIC_TX_INTERRUPTS)
138
139	/* The following constants are used with the following macros to specify the
140	* operation, a read or write operation.
141	*/
142	#define XIIC_READ_OPERATION 1
143	#define XIIC_WRITE_OPERATION 0
144
145	/*
146	* Tx Fifo upper bit masks.
147	*/
148	#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
149	#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
150
151	/*
152	* The following constants define the register offsets for the Interrupt
153	* registers. There are some holes in the memory map for reserved addresses
154	* to allow other registers to be added and still match the memory map of the
155	* interrupt controller registers
156	*/
157	#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
158	#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
159	#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
160	#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
161
162	#define XIIC_RESET_MASK 0xAUL
163
164	/*
165	* The following constant is used for the device global interrupt enable
166	* register, to enable all interrupts for the device, this is the only bit
167	* in the register
168	*/
169	#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
170
171	#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
172	#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
173
174	static void xiic_start_xfer(struct xiic_i2c *i2c);
175	static void __xiic_start_xfer(struct xiic_i2c *i2c);
176
177	static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
178	{
179	iowrite8(value, i2c->base + reg);
180	}
181
182	static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
183	{
184	return ioread8(i2c->base + reg);
185	}
186
187	static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
188	{
189	iowrite16(value, i2c->base + reg);
190	}
191
192	static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
193	{
194	iowrite32(value, i2c->base + reg);
195	}
196
197	static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
198	{
199	return ioread32(i2c->base + reg);
200	}
201
202	static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
203	{
204	u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
205	xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
206	}
207
208	static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
209	{
210	u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
211	xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier \| mask);
212	}
213
214	static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
215	{
216	u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
217	xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
218	}
219
220	static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
221	{
222	xiic_irq_clr(i2c, mask);
223	xiic_irq_en(i2c, mask);
224	}
225
226	static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
227	{
228	u8 sr;
229	for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
230	!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
231	sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
232	xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
233	}
234
235	static void xiic_reinit(struct xiic_i2c *i2c)
236	{
237	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
238
239	/* Set receive Fifo depth to maximum (zero based). */
240	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
241
242	/* Reset Tx Fifo. */
243	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
244
245	/* Enable IIC Device, remove Tx Fifo reset & disable general call. */
246	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
247
248	/* make sure RX fifo is empty */
249	xiic_clear_rx_fifo(i2c);
250
251	/* Enable interrupts */
252	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
253
254	xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK \| XIIC_INTR_ARB_LOST_MASK);
255	}
256
257	static void xiic_deinit(struct xiic_i2c *i2c)
258	{
259	u8 cr;
260
261	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
262
263	/* Disable IIC Device. */
264	cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
265	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
266	}
267
268	static void xiic_read_rx(struct xiic_i2c *i2c)
269	{
270	u8 bytes_in_fifo;
271	int i;
272
273	bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
274
275	dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
276	", SR: 0x%x, CR: 0x%x\n",
277	__func__, bytes_in_fifo, xiic_rx_space(i2c),
278	xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
279	xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
280
281	if (bytes_in_fifo > xiic_rx_space(i2c))
282	bytes_in_fifo = xiic_rx_space(i2c);
283
284	for (i = 0; i < bytes_in_fifo; i++)
285	i2c->rx_msg->buf[i2c->rx_pos++] =
286	xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
287
288	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
289	(xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
290	IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
291	}
292
293	static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
294	{
295	/* return the actual space left in the FIFO */
296	return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
297	}
298
299	static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
300	{
301	u8 fifo_space = xiic_tx_fifo_space(i2c);
302	int len = xiic_tx_space(i2c);
303
304	len = (len > fifo_space) ? fifo_space : len;
305
306	dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
307	__func__, len, fifo_space);
308
309	while (len--) {
310	u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
311	if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
312	/* last message in transfer -> STOP */
313	data \|= XIIC_TX_DYN_STOP_MASK;
314	dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
315
316	xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
317	} else
318	xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data);
319	}
320	}
321
322	static void xiic_wakeup(struct xiic_i2c *i2c, int code)
323	{
324	i2c->tx_msg = NULL;
325	i2c->rx_msg = NULL;
326	i2c->nmsgs = 0;
327	i2c->state = code;
328	wake_up(&i2c->wait);
329	}
330
331	static void xiic_process(struct xiic_i2c *i2c)
332	{
333	u32 pend, isr, ier;
334	u32 clr = 0;
335
336	/* Get the interrupt Status from the IPIF. There is no clearing of
337	* interrupts in the IPIF. Interrupts must be cleared at the source.
338	* To find which interrupts are pending; AND interrupts pending with
339	* interrupts masked.
340	*/
341	isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
342	ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
343	pend = isr & ier;
344
345	dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
346	"pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
347	__func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
348	i2c->tx_msg, i2c->nmsgs);
349
350	/* Do not processes a devices interrupts if the device has no
351	* interrupts pending
352	*/
353	if (!pend)
354	return;
355
356	/* Service requesting interrupt */
357	if ((pend & XIIC_INTR_ARB_LOST_MASK) \|\|
358	((pend & XIIC_INTR_TX_ERROR_MASK) &&
359	!(pend & XIIC_INTR_RX_FULL_MASK))) {
360	/* bus arbritration lost, or...
361	* Transmit error _OR_ RX completed
362	* if this happens when RX_FULL is not set
363	* this is probably a TX error
364	*/
365
366	dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
367
368	/* dynamic mode seem to suffer from problems if we just flushes
369	* fifos and the next message is a TX with len 0 (only addr)
370	* reset the IP instead of just flush fifos
371	*/
372	xiic_reinit(i2c);
373
374	if (i2c->tx_msg)
375	xiic_wakeup(i2c, STATE_ERROR);
376
377	} else if (pend & XIIC_INTR_RX_FULL_MASK) {
378	/* Receive register/FIFO is full */
379
380	clr = XIIC_INTR_RX_FULL_MASK;
381	if (!i2c->rx_msg) {
382	dev_dbg(i2c->adap.dev.parent,
383	"%s unexpexted RX IRQ\n", __func__);
384	xiic_clear_rx_fifo(i2c);
385	goto out;
386	}
387
388	xiic_read_rx(i2c);
389	if (xiic_rx_space(i2c) == 0) {
390	/* this is the last part of the message */
391	i2c->rx_msg = NULL;
392
393	/* also clear TX error if there (RX complete) */
394	clr \|= (isr & XIIC_INTR_TX_ERROR_MASK);
395
396	dev_dbg(i2c->adap.dev.parent,
397	"%s end of message, nmsgs: %d\n",
398	__func__, i2c->nmsgs);
399
400	/* send next message if this wasn't the last,
401	* otherwise the transfer will be finialise when
402	* receiving the bus not busy interrupt
403	*/
404	if (i2c->nmsgs > 1) {
405	i2c->nmsgs--;
406	i2c->tx_msg++;
407	dev_dbg(i2c->adap.dev.parent,
408	"%s will start next...\n", __func__);
409
410	__xiic_start_xfer(i2c);
411	}
412	}
413	} else if (pend & XIIC_INTR_BNB_MASK) {
414	/* IIC bus has transitioned to not busy */
415	clr = XIIC_INTR_BNB_MASK;
416
417	/* The bus is not busy, disable BusNotBusy interrupt */
418	xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
419
420	if (!i2c->tx_msg)
421	goto out;
422
423	if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
424	xiic_tx_space(i2c) == 0)
425	xiic_wakeup(i2c, STATE_DONE);
426	else
427	xiic_wakeup(i2c, STATE_ERROR);
428
429	} else if (pend & (XIIC_INTR_TX_EMPTY_MASK \| XIIC_INTR_TX_HALF_MASK)) {
430