[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-xlp9xx.c

/*
 * Copyright (c) 2003-2015 Broadcom Corporation
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/i2c.h>
#include <linux/i2c-smbus.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>

#define XLP9XX_I2C_DIV			0x0
#define XLP9XX_I2C_CTRL			0x1
#define XLP9XX_I2C_CMD			0x2
#define XLP9XX_I2C_STATUS		0x3
#define XLP9XX_I2C_MTXFIFO		0x4
#define XLP9XX_I2C_MRXFIFO		0x5
#define XLP9XX_I2C_MFIFOCTRL		0x6
#define XLP9XX_I2C_STXFIFO		0x7
#define XLP9XX_I2C_SRXFIFO		0x8
#define XLP9XX_I2C_SFIFOCTRL		0x9
#define XLP9XX_I2C_SLAVEADDR		0xA
#define XLP9XX_I2C_OWNADDR		0xB
#define XLP9XX_I2C_FIFOWCNT		0xC
#define XLP9XX_I2C_INTEN		0xD
#define XLP9XX_I2C_INTST		0xE
#define XLP9XX_I2C_WAITCNT		0xF
#define XLP9XX_I2C_TIMEOUT		0X10
#define XLP9XX_I2C_GENCALLADDR		0x11

#define XLP9XX_I2C_STATUS_BUSY		BIT(0)

#define XLP9XX_I2C_CMD_START		BIT(7)
#define XLP9XX_I2C_CMD_STOP		BIT(6)
#define XLP9XX_I2C_CMD_READ		BIT(5)
#define XLP9XX_I2C_CMD_WRITE		BIT(4)
#define XLP9XX_I2C_CMD_ACK		BIT(3)

#define XLP9XX_I2C_CTRL_MCTLEN_SHIFT	16
#define XLP9XX_I2C_CTRL_MCTLEN_MASK	0xffff0000
#define XLP9XX_I2C_CTRL_RST		BIT(8)
#define XLP9XX_I2C_CTRL_EN		BIT(6)
#define XLP9XX_I2C_CTRL_MASTER		BIT(4)
#define XLP9XX_I2C_CTRL_FIFORD		BIT(1)
#define XLP9XX_I2C_CTRL_ADDMODE		BIT(0)

#define XLP9XX_I2C_INTEN_NACKADDR	BIT(25)
#define XLP9XX_I2C_INTEN_SADDR		BIT(13)
#define XLP9XX_I2C_INTEN_DATADONE	BIT(12)
#define XLP9XX_I2C_INTEN_ARLOST		BIT(11)
#define XLP9XX_I2C_INTEN_MFIFOFULL	BIT(4)
#define XLP9XX_I2C_INTEN_MFIFOEMTY	BIT(3)
#define XLP9XX_I2C_INTEN_MFIFOHI	BIT(2)
#define XLP9XX_I2C_INTEN_BUSERR		BIT(0)

#define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT		8
#define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT		0
#define XLP9XX_I2C_MFIFOCTRL_RST		BIT(16)

#define XLP9XX_I2C_SLAVEADDR_RW			BIT(0)
#define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT		1

#define XLP9XX_I2C_IP_CLK_FREQ		133000000UL
#define XLP9XX_I2C_DEFAULT_FREQ		100000
#define XLP9XX_I2C_HIGH_FREQ		400000
#define XLP9XX_I2C_FIFO_SIZE		0x80U
#define XLP9XX_I2C_TIMEOUT_MS		1000
#define XLP9XX_I2C_BUSY_TIMEOUT		50

#define XLP9XX_I2C_FIFO_WCNT_MASK	0xff
#define XLP9XX_I2C_STATUS_ERRMASK	(XLP9XX_I2C_INTEN_ARLOST | \
			XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)

struct xlp9xx_i2c_dev {
	struct device *dev;
	struct i2c_adapter adapter;
	struct completion msg_complete;
	struct i2c_smbus_alert_setup alert_data;
	struct i2c_client *ara;
	int irq;
	bool msg_read;
	bool len_recv;
	bool client_pec;
	u32 __iomem *base;
	u32 msg_buf_remaining;
	u32 msg_len;
	u32 ip_clk_hz;
	u32 clk_hz;
	u32 msg_err;
	u8 *msg_buf;
};

static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
					unsigned long reg, u32 val)
{
	writel(val, priv->base + reg);
}

static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
				      unsigned long reg)
{
	return readl(priv->base + reg);
}

static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
{
	u32 inten;

	inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
}

static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
{
	u32 inten;

	inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
}

static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
{
	u32 thres;

	if (priv->len_recv)
		/* interrupt after the first read to examine
		 * the length byte before proceeding further
		 */
		thres = 1;
	else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE)
		thres = XLP9XX_I2C_FIFO_SIZE;
	else
		thres = priv->msg_buf_remaining;

	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
			     thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
}

static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
{
	u32 len, i;
	u8 *buf = priv->msg_buf;

	len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
	for (i = 0; i < len; i++)
		xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
	priv->msg_buf_remaining -= len;
	priv->msg_buf += len;
}

static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv)
{
	u32 val, len;

	/*
	 * Update receive length. Re-read len to get the latest value,
	 * and then add 4 to have a minimum value that can be safely
	 * written. This is to account for the byte read above, the
	 * transfer in progress and any delays in the register I/O
	 */
	val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
	len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
				  XLP9XX_I2C_FIFO_WCNT_MASK;
	len = max_t(u32, priv->msg_len, len + 4);
	if (len >= I2C_SMBUS_BLOCK_MAX + 2)
		return;
	val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
			(len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
}

static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
{
	u32 len, i;
	u8 rlen, *buf = priv->msg_buf;

	len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
				  XLP9XX_I2C_FIFO_WCNT_MASK;
	if (!len)
		return;
	if (priv->len_recv) {
		/* read length byte */
		rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);

		/*
		 * We expect at least 2 interrupts for I2C_M_RECV_LEN
		 * transactions. The length is updated during the first
		 * interrupt, and the buffer contents are only copied
		 * during subsequent interrupts. If in case the interrupts
		 * get merged we would complete the transaction without
		 * copying out the bytes from RX fifo. To avoid this now we
		 * drain the fifo as and when data is available.
		 * We drained the rlen byte already, decrement total length
		 * by one.
		 */

		len--;
		if (rlen > I2C_SMBUS_BLOCK_MAX || rlen == 0) {
			rlen = 0;	/*abort transfer */
			priv->msg_buf_remaining = 0;
			priv->msg_len = 0;
			xlp9xx_i2c_update_rlen(priv);
			return;
		}

		*buf++ = rlen;
		if (priv->client_pec)
			++rlen; /* account for error check byte */
		/* update remaining bytes and message length */
		priv->msg_buf_remaining = rlen;
		priv->msg_len = rlen + 1;
		xlp9xx_i2c_update_rlen(priv);
		priv->len_recv = false;
	}

	len = min(priv->msg_buf_remaining, len);
	for (i = 0; i < len; i++, buf++)
		*buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);

	priv->msg_buf_remaining -= len;
	priv->msg_buf = buf;

	if (priv->msg_buf_remaining)
		xlp9xx_i2c_update_rx_fifo_thres(priv);
}

static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
{
	struct xlp9xx_i2c_dev *priv = dev_id;
	u32 status;

	status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
	if (status == 0)
		return IRQ_NONE;

	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
	if (status & XLP9XX_I2C_STATUS_ERRMASK) {
		priv->msg_err = status;
		goto xfer_done;
	}

	/* SADDR ACK for SMBUS_QUICK */
	if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
		goto xfer_done;

	if (!priv->msg_read) {
		if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
			/* TX FIFO got empty, fill it up again */
			if (priv->msg_buf_remaining)
				xlp9xx_i2c_fill_tx_fifo(priv);
			else
				xlp9xx_i2c_mask_irq(priv,
						    XLP9XX_I2C_INTEN_MFIFOEMTY);
		}
	} else {
		if (status & (XLP9XX_I2C_INTEN_DATADONE |
			      XLP9XX_I2C_INTEN_MFIFOHI)) {
			/* data is in FIFO, read it */
			if (priv->msg_buf_remaining)
				xlp9xx_i2c_drain_rx_fifo(priv);
		}
	}

	/* Transfer complete */
	if (status & XLP9XX_I2C_INTEN_DATADONE)
		goto xfer_done;

	return IRQ_HANDLED;

xfer_done:
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
	complete(&priv->msg_complete);
	return IRQ_HANDLED;
}

static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv)
{
	u32 status;
	u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT;

	while (busy_timeout) {
		status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS);
		if ((status & XLP9XX_I2C_STATUS_BUSY) == 0)
			break;

		busy_timeout--;
		usleep_range(1000, 1100);
	}

	if (!busy_timeout)
		return -EIO;

	return 0;
}

static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
{
	u32 prescale;

	/*
	 * The controller uses 5 * SCL clock internally.
	 * So prescale value should be divided by 5.
	 */
	prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
	prescale = ((prescale - 8) / 5) - 1;
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
			     XLP9XX_I2C_CTRL_MASTER);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);

	return 0;
}

static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
			       int last_msg)
{
	unsigned long timeleft;
	u32 intr_mask, cmd, val, len;

	priv->msg_buf = msg->buf;
	priv->msg_buf_remaining = priv->msg_len = msg->len;
	priv->msg_err = 0;
	priv->msg_read = (msg->flags & I2C_M_RD);
	reinit_completion(&priv->msg_complete);

	/* Reset FIFO */
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
			     XLP9XX_I2C_MFIFOCTRL_RST);

	/* set slave addr */
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
			     (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
			     (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));

	/* Build control word for transfer */
	val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
	if (!priv->msg_read)
		val &= ~XLP9XX_I2C_CTRL_FIFORD;
	else
		val |= XLP9XX_I2C_CTRL_FIFORD;	/* read */

	if (msg->flags & I2C_M_TEN)
		val |= XLP9XX_I2C_CTRL_ADDMODE;	/* 10-bit address mode*/
	else
		val &= ~XLP9XX_I2C_CTRL_ADDMODE;

	priv->len_recv = msg->flags & I2C_M_RECV_LEN;
	len = priv->len_recv ? I2C_SMBUS_BLOCK_MAX + 2 : msg->len;
	priv->client_pec = msg->flags & I2C_CLIENT_PEC;

	/* set FIFO threshold if reading */
	if (priv->msg_read)
		xlp9xx_i2c_update_rx_fifo_thres(priv);

	/* set data length to be transferred */
	val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
	      (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);

	/* fill fifo during tx */
	if (!priv->msg_read)
		xlp9xx_i2c_fill_tx_fifo(priv);

	/* set interrupt mask */
	intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
		     XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);

	if (priv->msg_read) {
		intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
		if (msg->len == 0)
			intr_mask |= XLP9XX_I2C_INTEN_SADDR;
	} else {
		if (msg->len == 0)
			intr_mask |= XLP9XX_I2C_INTEN_SADDR;
		else
			intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
	}
	xlp9xx_i2c_unmask_irq(priv, intr_mask);

	/* set cmd reg */
	cmd = XLP9XX_I2C_CMD_START;
	if (msg->len)
		cmd |= (priv->msg_read ?
			XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
	if (last_msg)
		cmd |= XLP9XX_I2C_CMD_STOP;

	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);

	timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
	timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);

	if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) {
		dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
		xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP);
		return -EIO;
	} else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) {
		return -ENXIO;
	}

	if (timeleft == 0) {
		dev_dbg(priv->dev, "i2c transfer timed out!\n");
		xlp9xx_i2c_init(priv);
		return -ETIMEDOUT;
	}

	/* update msg->len with actual received length */
	if (msg->flags & I2C_M_RECV_LEN) {
		if (!priv->msg_len)
			return -EPROTO;
		msg->len = priv->msg_len;
	}
	return 0;
}

static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
			   int num)
{
	int i, ret;
	struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);

	ret = xlp9xx_i2c_check_bus_status(priv);
	if (ret) {
		xlp9xx_i2c_init(priv);
		ret = xlp9xx_i2c_check_bus_status(priv);
		if (ret)
			return ret;
	}

	for (i = 0; i < num; i++) {
		ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
		if (ret != 0)
			return ret;
	}

	return num;
}

static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA |
			I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
}

static const struct i2c_algorithm xlp9xx_i2c_algo = {
	.master_xfer = xlp9xx_i2c_xfer,
	.functionality = xlp9xx_i2c_functionality,
};

static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
				    struct xlp9xx_i2c_dev *priv)
{
	struct clk *clk;
	u32 freq;
	int err;

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
		dev_dbg(&pdev->dev, "using default input frequency %u\n",
			priv->ip_clk_hz);
	} else {
		priv->ip_clk_hz = clk_get_rate(clk);
	}

	err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
	if (err) {
		freq = XLP9XX_I2C_DEFAULT_FREQ;
		dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
	} else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) {
		dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
			 freq);
		freq = XLP9XX_I2C_DEFAULT_FREQ;
	}
	priv->clk_hz = freq;

	return 0;
}

static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv,
				  struct platform_device *pdev)
{
	if (!priv->alert_data.irq)
		return -EINVAL;

	priv->ara = i2c_setup_smbus_alert(&priv->adapter, &priv->alert_data);
	if (!priv->ara)
		return -ENODEV;

	return 0;
}

static int xlp9xx_i2c_probe(struct platform_device *pdev)
{
	struct xlp9xx_i2c_dev *priv;
	struct resource *res;
	int err = 0;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->irq = platform_get_irq(pdev, 0);
	if (priv->irq <= 0) {
		dev_err(&pdev->dev, "invalid irq!\n");
		return priv->irq;
	}
	/* SMBAlert irq */
	priv->alert_data.irq = platform_get_irq(pdev, 1);
	if (priv->alert_data.irq <= 0)
		priv->alert_data.irq = 0;

	xlp9xx_i2c_get_frequency(pdev, priv);
	xlp9xx_i2c_init(priv);

	err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
			       pdev->name, priv);
	if (err) {
		dev_err(&pdev->dev, "IRQ request failed!\n");
		return err;
	}

	init_completion(&priv->msg_complete);
	priv->adapter.dev.parent = &pdev->dev;
	priv->adapter.algo = &xlp9xx_i2c_algo;
	priv->adapter.class = I2C_CLASS_HWMON;
	ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
	priv->adapter.dev.of_node = pdev->dev.of_node;
	priv->dev = &pdev->dev;

	snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
	i2c_set_adapdata(&priv->adapter, priv);

	err = i2c_add_adapter(&priv->adapter);
	if (err)
		return err;

	err = xlp9xx_i2c_smbus_setup(priv, pdev);
	if (err)
		dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err);

	platform_set_drvdata(pdev, priv);
	dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);

	return 0;
}

static int xlp9xx_i2c_remove(struct platform_device *pdev)
{
	struct xlp9xx_i2c_dev *priv;

	priv = platform_get_drvdata(pdev);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
	synchronize_irq(priv->irq);
	i2c_del_adapter(&priv->adapter);
	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);

	return 0;
}

static const struct of_device_id xlp9xx_i2c_of_match[] = {
	{ .compatible = "netlogic,xlp980-i2c", },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match);

#ifdef CONFIG_ACPI
static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = {
	{"BRCM9007", 0},
	{"CAV9007",  0},
	{}
};
MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids);
#endif

static struct platform_driver xlp9xx_i2c_driver = {
	.probe = xlp9xx_i2c_probe,
	.remove = xlp9xx_i2c_remove,
	.driver = {
		.name = "xlp9xx-i2c",
		.of_match_table = xlp9xx_i2c_of_match,
		.acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids),
	},
};

module_platform_driver(xlp9xx_i2c_driver);

MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2bbd681b SSB	1	/*
	2	* Copyright (c) 2003-2015 Broadcom Corporation
	3	*
	4	* This file is licensed under the terms of the GNU General Public
	5	* License version 2. This program is licensed "as is" without any
	6	* warranty of any kind, whether express or implied.
	7	*/
	8
748c0bbb	9	#include <linux/acpi.h>
c347b8fc	10	#include <linux/clk.h>
2bbd681b SSB	11	#include <linux/completion.h>
2bbd681b SSB	12	#include <linux/i2c.h>
43bcfcc8	13	#include <linux/i2c-smbus.h>
2bbd681b SSB	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
2fbdba2b	20	#include <linux/delay.h>
2bbd681b SSB	21
	22	#define XLP9XX_I2C_DIV 0x0
	23	#define XLP9XX_I2C_CTRL 0x1
	24	#define XLP9XX_I2C_CMD 0x2
	25	#define XLP9XX_I2C_STATUS 0x3
	26	#define XLP9XX_I2C_MTXFIFO 0x4
	27	#define XLP9XX_I2C_MRXFIFO 0x5
	28	#define XLP9XX_I2C_MFIFOCTRL 0x6
	29	#define XLP9XX_I2C_STXFIFO 0x7
	30	#define XLP9XX_I2C_SRXFIFO 0x8
	31	#define XLP9XX_I2C_SFIFOCTRL 0x9
	32	#define XLP9XX_I2C_SLAVEADDR 0xA
	33	#define XLP9XX_I2C_OWNADDR 0xB
	34	#define XLP9XX_I2C_FIFOWCNT 0xC
	35	#define XLP9XX_I2C_INTEN 0xD
	36	#define XLP9XX_I2C_INTST 0xE
	37	#define XLP9XX_I2C_WAITCNT 0xF
	38	#define XLP9XX_I2C_TIMEOUT 0X10
	39	#define XLP9XX_I2C_GENCALLADDR 0x11
	40
2fbdba2b GC	41	#define XLP9XX_I2C_STATUS_BUSY BIT(0)
2fbdba2b GC	42
2bbd681b SSB	43	#define XLP9XX_I2C_CMD_START BIT(7)
	44	#define XLP9XX_I2C_CMD_STOP BIT(6)
	45	#define XLP9XX_I2C_CMD_READ BIT(5)
	46	#define XLP9XX_I2C_CMD_WRITE BIT(4)
	47	#define XLP9XX_I2C_CMD_ACK BIT(3)
	48
	49	#define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16
	50	#define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000
	51	#define XLP9XX_I2C_CTRL_RST BIT(8)
	52	#define XLP9XX_I2C_CTRL_EN BIT(6)
	53	#define XLP9XX_I2C_CTRL_MASTER BIT(4)
	54	#define XLP9XX_I2C_CTRL_FIFORD BIT(1)
	55	#define XLP9XX_I2C_CTRL_ADDMODE BIT(0)
	56
	57	#define XLP9XX_I2C_INTEN_NACKADDR BIT(25)
	58	#define XLP9XX_I2C_INTEN_SADDR BIT(13)
	59	#define XLP9XX_I2C_INTEN_DATADONE BIT(12)
	60	#define XLP9XX_I2C_INTEN_ARLOST BIT(11)
	61	#define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4)
	62	#define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3)
	63	#define XLP9XX_I2C_INTEN_MFIFOHI BIT(2)
	64	#define XLP9XX_I2C_INTEN_BUSERR BIT(0)
	65
	66	#define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8
	67	#define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0
	68	#define XLP9XX_I2C_MFIFOCTRL_RST BIT(16)
	69
	70	#define XLP9XX_I2C_SLAVEADDR_RW BIT(0)
	71	#define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1
	72
	73	#define XLP9XX_I2C_IP_CLK_FREQ 133000000UL
	74	#define XLP9XX_I2C_DEFAULT_FREQ 100000
	75	#define XLP9XX_I2C_HIGH_FREQ 400000
	76	#define XLP9XX_I2C_FIFO_SIZE 0x80U
	77	#define XLP9XX_I2C_TIMEOUT_MS 1000
2fbdba2b	78	#define XLP9XX_I2C_BUSY_TIMEOUT 50
2bbd681b SSB	79
	80	#define XLP9XX_I2C_FIFO_WCNT_MASK 0xff
	81	#define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST \| \
	82	XLP9XX_I2C_INTEN_NACKADDR \| XLP9XX_I2C_INTEN_BUSERR)
	83
	84	struct xlp9xx_i2c_dev {
	85	struct device *dev;
	86	struct i2c_adapter adapter;
	87	struct completion msg_complete;
43bcfcc8 GC	88	struct i2c_smbus_alert_setup alert_data;
43bcfcc8 GC	89	struct i2c_client *ara;
2bbd681b SSB	90	int irq;
2bbd681b SSB	91	bool msg_read;
5515ae11 KP	92	bool len_recv;
5515ae11 KP	93	bool client_pec;
2bbd681b SSB	94	u32 __iomem *base;
	95	u32 msg_buf_remaining;
	96	u32 msg_len;
c347b8fc	97	u32 ip_clk_hz;
2bbd681b SSB	98	u32 clk_hz;
	99	u32 msg_err;
	100	u8 *msg_buf;
	101	};
	102
	103	static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
	104	unsigned long reg, u32 val)
	105	{
	106	writel(val, priv->base + reg);
	107	}
	108
	109	static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
	110	unsigned long reg)
	111	{
	112	return readl(priv->base + reg);
	113	}
	114
	115	static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
	116	{
	117	u32 inten;
	118
	119	inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
	120	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
	121	}
	122
	123	static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
	124	{
	125	u32 inten;
	126
	127	inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) \| mask;
	128	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
	129	}
	130
	131	static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
	132	{
	133	u32 thres;
	134
323879c8 GC	135	if (priv->len_recv)
	136	/* interrupt after the first read to examine
	137	* the length byte before proceeding further
	138	*/
	139	thres = 1;
	140	else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE)
	141	thres = XLP9XX_I2C_FIFO_SIZE;
	142	else
	143	thres = priv->msg_buf_remaining;
	144
2bbd681b SSB	145	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
	146	thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
	147	}
	148
	149	static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
	150	{
	151	u32 len, i;
	152	u8 *buf = priv->msg_buf;
	153
	154	len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
	155	for (i = 0; i < len; i++)
	156	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
	157	priv->msg_buf_remaining -= len;
	158	priv->msg_buf += len;
	159	}
	160
3af5f693 GC	161	static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv)
	162	{
	163	u32 val, len;
	164
	165	/*
	166	* Update receive length. Re-read len to get the latest value,
	167	* and then add 4 to have a minimum value that can be safely
	168	* written. This is to account for the byte read above, the
	169	* transfer in progress and any delays in the register I/O
	170	*/
	171	val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
	172	len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
	173	XLP9XX_I2C_FIFO_WCNT_MASK;
	174	len = max_t(u32, priv->msg_len, len + 4);
dae2b99a GC	175	if (len >= I2C_SMBUS_BLOCK_MAX + 2)
dae2b99a GC	176	return;
3af5f693 GC	177	val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) \|
	178	(len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
	179	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
	180	}
	181
2bbd681b SSB	182	static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
2bbd681b SSB	183	{
3af5f693	184	u32 len, i;
5515ae11	185	u8 rlen, *buf = priv->msg_buf;
2bbd681b SSB	186
	187	len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
	188	XLP9XX_I2C_FIFO_WCNT_MASK;
5515ae11 KP	189	if (!len)
	190	return;
	191	if (priv->len_recv) {
	192	/* read length byte */
	193	rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
73f8ca7e GC	194
	195	/*
	196	* We expect at least 2 interrupts for I2C_M_RECV_LEN
	197	* transactions. The length is updated during the first
	198	* interrupt, and the buffer contents are only copied
	199	* during subsequent interrupts. If in case the interrupts
	200	* get merged we would complete the transaction without
	201	* copying out the bytes from RX fifo. To avoid this now we
	202	* drain the fifo as and when data is available.
	203	* We drained the rlen byte already, decrement total length
	204	* by one.
	205	*/
	206
	207	len--;
dae2b99a GC	208	if (rlen > I2C_SMBUS_BLOCK_MAX \|\| rlen == 0) {
	209	rlen = 0; /abort transfer /
	210	priv->msg_buf_remaining = 0;
	211	priv->msg_len = 0;
73f8ca7e GC	212	xlp9xx_i2c_update_rlen(priv);
73f8ca7e GC	213	return;
dae2b99a	214	}
73f8ca7e GC	215
	216	*buf++ = rlen;
	217	if (priv->client_pec)
	218	++rlen; /* account for error check byte */
	219	/* update remaining bytes and message length */
	220	priv->msg_buf_remaining = rlen;
	221	priv->msg_len = rlen + 1;
3af5f693	222	xlp9xx_i2c_update_rlen(priv);
dae2b99a	223	priv->len_recv = false;
323879c8	224	}
2bbd681b	225
73f8ca7e GC	226	len = min(priv->msg_buf_remaining, len);
	227	for (i = 0; i < len; i++, buf++)
	228	*buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
	229
	230	priv->msg_buf_remaining -= len;
2bbd681b SSB	231	priv->msg_buf = buf;
	232
	233	if (priv->msg_buf_remaining)
	234	xlp9xx_i2c_update_rx_fifo_thres(priv);
	235	}
	236
	237	static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
	238	{
	239	struct xlp9xx_i2c_dev *priv = dev_id;
	240	u32 status;
	241
	242	status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
	243	if (status == 0)
	244	return IRQ_NONE;
	245
	246	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
	247	if (status & XLP9XX_I2C_STATUS_ERRMASK) {
	248	priv->msg_err = status;
	249	goto xfer_done;
	250	}
	251
	252	/* SADDR ACK for SMBUS_QUICK */
	253	if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
	254	goto xfer_done;
	255
	256	if (!priv->msg_read) {
	257	if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
	258	/* TX FIFO got empty, fill it up again */
	259	if (priv->msg_buf_remaining)
	260	xlp9xx_i2c_fill_tx_fifo(priv);
	261	else
	262	xlp9xx_i2c_mask_irq(priv,
	263	XLP9XX_I2C_INTEN_MFIFOEMTY);
	264	}
	265	} else {
	266	if (status & (XLP9XX_I2C_INTEN_DATADONE \|
	267	XLP9XX_I2C_INTEN_MFIFOHI)) {
	268	/* data is in FIFO, read it */
	269	if (priv->msg_buf_remaining)
	270	xlp9xx_i2c_drain_rx_fifo(priv);
	271	}
	272	}
	273
	274	/* Transfer complete */
	275	if (status & XLP9XX_I2C_INTEN_DATADONE)
	276	goto xfer_done;
	277
	278	return IRQ_HANDLED;
	279
	280	xfer_done:
	281	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
	282	complete(&priv->msg_complete);
	283	return IRQ_HANDLED;
	284	}
	285
2fbdba2b GC	286	static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv)
	287	{
	288	u32 status;
	289	u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT;
	290
	291	while (busy_timeout) {
	292	status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS);
	293	if ((status & XLP9XX_I2C_STATUS_BUSY) == 0)
	294	break;
	295
	296	busy_timeout--;
	297	usleep_range(1000, 1100);
	298	}
	299
	300	if (!busy_timeout)
	301	return -EIO;
	302
	303	return 0;
	304	}
	305
2bbd681b SSB	306	static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
	307	{
	308	u32 prescale;
	309
	310	/*
	311	* The controller uses 5 * SCL clock internally.
	312	* So prescale value should be divided by 5.
	313	*/
c347b8fc	314	prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
2bbd681b SSB	315	prescale = ((prescale - 8) / 5) - 1;
	316	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
	317	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN \|
	318	XLP9XX_I2C_CTRL_MASTER);
	319	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
	320	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
	321
	322	return 0;
	323	}
	324
	325	static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev priv, struct i2c_msg msg,
	326	int last_msg)
	327	{
	328	unsigned long timeleft;
5515ae11	329	u32 intr_mask, cmd, val, len;
2bbd681b SSB	330
	331	priv->msg_buf = msg->buf;
	332	priv->msg_buf_remaining = priv->msg_len = msg->len;
	333	priv->msg_err = 0;
	334	priv->msg_read = (msg->flags & I2C_M_RD);
	335	reinit_completion(&priv->msg_complete);
	336
	337	/* Reset FIFO */
	338	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
	339	XLP9XX_I2C_MFIFOCTRL_RST);
	340
2bbd681b SSB	341	/* set slave addr */
	342	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
	343	(msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) \|
	344	(priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
	345
	346	/* Build control word for transfer */
	347	val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
	348	if (!priv->msg_read)
	349	val &= ~XLP9XX_I2C_CTRL_FIFORD;
	350	else
	351	val \|= XLP9XX_I2C_CTRL_FIFORD; /* read */
	352
	353	if (msg->flags & I2C_M_TEN)
	354	val \|= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
	355	else
	356	val &= ~XLP9XX_I2C_CTRL_ADDMODE;
	357
5515ae11	358	priv->len_recv = msg->flags & I2C_M_RECV_LEN;
dae2b99a	359	len = priv->len_recv ? I2C_SMBUS_BLOCK_MAX + 2 : msg->len;
5515ae11 KP	360	priv->client_pec = msg->flags & I2C_CLIENT_PEC;
5515ae11 KP	361
dae2b99a GC	362	/* set FIFO threshold if reading */
	363	if (priv->msg_read)
	364	xlp9xx_i2c_update_rx_fifo_thres(priv);
	365
2bbd681b SSB	366	/* set data length to be transferred */
2bbd681b SSB	367	val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) \|
5515ae11	368	(len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
2bbd681b SSB	369	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
	370
	371	/* fill fifo during tx */
	372	if (!priv->msg_read)
	373	xlp9xx_i2c_fill_tx_fifo(priv);
	374
	375	/* set interrupt mask */
	376	intr_mask = (XLP9XX_I2C_INTEN_ARLOST \| XLP9XX_I2C_INTEN_BUSERR \|
	377	XLP9XX_I2C_INTEN_NACKADDR \| XLP9XX_I2C_INTEN_DATADONE);
	378
	379	if (priv->msg_read) {
	380	intr_mask \|= XLP9XX_I2C_INTEN_MFIFOHI;
	381	if (msg->len == 0)
	382	intr_mask \|= XLP9XX_I2C_INTEN_SADDR;
	383	} else {
	384	if (msg->len == 0)
	385	intr_mask \|= XLP9XX_I2C_INTEN_SADDR;
	386	else
	387	intr_mask \|= XLP9XX_I2C_INTEN_MFIFOEMTY;
	388	}
	389	xlp9xx_i2c_unmask_irq(priv, intr_mask);
	390
	391	/* set cmd reg */
	392	cmd = XLP9XX_I2C_CMD_START;
a12cb271 GC	393	if (msg->len)
	394	cmd \|= (priv->msg_read ?
	395	XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
2bbd681b SSB	396	if (last_msg)
	397	cmd \|= XLP9XX_I2C_CMD_STOP;
	398
	399	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
	400
	401	timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
	402	timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
	403
a12cb271	404	if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) {
2bbd681b	405	dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
a12cb271 GC	406	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP);
	407	return -EIO;
	408	} else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) {
	409	return -ENXIO;
2bbd681b SSB	410	}
	411
	412	if (timeleft == 0) {
	413	dev_dbg(priv->dev, "i2c transfer timed out!\n");
	414	xlp9xx_i2c_init(priv);
	415	return -ETIMEDOUT;
	416	}
	417
5515ae11	418	/* update msg->len with actual received length */
dae2b99a GC	419	if (msg->flags & I2C_M_RECV_LEN) {
	420	if (!priv->msg_len)
	421	return -EPROTO;
5515ae11	422	msg->len = priv->msg_len;
dae2b99a	423	}
2bbd681b SSB	424	return 0;
	425	}
	426
	427	static int xlp9xx_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
	428	int num)
	429	{
	430	int i, ret;
	431	struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
	432
2fbdba2b GC	433	ret = xlp9xx_i2c_check_bus_status(priv);
	434	if (ret) {
	435	xlp9xx_i2c_init(priv);
	436	ret = xlp9xx_i2c_check_bus_status(priv);
	437	if (ret)
	438	return ret;
	439	}
	440
2bbd681b SSB	441	for (i = 0; i < num; i++) {
	442	ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
	443	if (ret != 0)
	444	return ret;
	445	}
	446
	447	return num;
	448	}
	449
	450	static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
	451	{
323879c8 GC	452	return I2C_FUNC_SMBUS_EMUL \| I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
323879c8 GC	453	I2C_FUNC_I2C \| I2C_FUNC_10BIT_ADDR;
2bbd681b SSB	454	}
2bbd681b SSB	455
92d9d0df	456	static const struct i2c_algorithm xlp9xx_i2c_algo = {
2bbd681b SSB	457	.master_xfer = xlp9xx_i2c_xfer,
	458	.functionality = xlp9xx_i2c_functionality,
	459	};
	460
	461	static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
	462	struct xlp9xx_i2c_dev *priv)
	463	{
c347b8fc	464	struct clk *clk;
2bbd681b SSB	465	u32 freq;
	466	int err;
	467
c347b8fc J	468	clk = devm_clk_get(&pdev->dev, NULL);
	469	if (IS_ERR(clk)) {
	470	priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
	471	dev_dbg(&pdev->dev, "using default input frequency %u\n",
	472	priv->ip_clk_hz);
	473	} else {
	474	priv->ip_clk_hz = clk_get_rate(clk);
	475	}
	476
748c0bbb	477	err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
2bbd681b SSB	478	if (err) {
	479	freq = XLP9XX_I2C_DEFAULT_FREQ;
	480	dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
	481	} else if (freq == 0 \|\| freq > XLP9XX_I2C_HIGH_FREQ) {
	482	dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
	483	freq);
	484	freq = XLP9XX_I2C_DEFAULT_FREQ;
	485	}
	486	priv->clk_hz = freq;
	487
	488	return 0;
	489	}
	490
43bcfcc8 GC	491	static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv,
	492	struct platform_device *pdev)
	493	{
	494	if (!priv->alert_data.irq)
	495	return -EINVAL;
	496
	497	priv->ara = i2c_setup_smbus_alert(&priv->adapter, &priv->alert_data);
	498	if (!priv->ara)
	499	return -ENODEV;
	500
	501	return 0;
	502	}
	503
2bbd681b SSB	504	static int xlp9xx_i2c_probe(struct platform_device *pdev)
	505	{
	506	struct xlp9xx_i2c_dev *priv;
	507	struct resource *res;
	508	int err = 0;
	509
	510	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	511	if (!priv)
	512	return -ENOMEM;
	513
	514	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	515	priv->base = devm_ioremap_resource(&pdev->dev, res);
	516	if (IS_ERR(priv->base))
	517	return PTR_ERR(priv->base);
	518
	519	priv->irq = platform_get_irq(pdev, 0);
	520	if (priv->irq <= 0) {
	521	dev_err(&pdev->dev, "invalid irq!\n");
	522	return priv->irq;
	523	}
43bcfcc8 GC	524	/* SMBAlert irq */
	525	priv->alert_data.irq = platform_get_irq(pdev, 1);
	526	if (priv->alert_data.irq <= 0)
	527	priv->alert_data.irq = 0;
2bbd681b SSB	528
	529	xlp9xx_i2c_get_frequency(pdev, priv);
	530	xlp9xx_i2c_init(priv);
	531
	532	err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
	533	pdev->name, priv);
	534	if (err) {
	535	dev_err(&pdev->dev, "IRQ request failed!\n");
	536	return err;
	537	}
	538
	539	init_completion(&priv->msg_complete);
	540	priv->adapter.dev.parent = &pdev->dev;
	541	priv->adapter.algo = &xlp9xx_i2c_algo;
227855b9	542	priv->adapter.class = I2C_CLASS_HWMON;
254df038	543	ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
2bbd681b SSB	544	priv->adapter.dev.of_node = pdev->dev.of_node;
	545	priv->dev = &pdev->dev;
	546
	547	snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
	548	i2c_set_adapdata(&priv->adapter, priv);
	549
	550	err = i2c_add_adapter(&priv->adapter);
ea734404	551	if (err)
2bbd681b	552	return err;
2bbd681b	553
43bcfcc8 GC	554	err = xlp9xx_i2c_smbus_setup(priv, pdev);
	555	if (err)
	556	dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err);
	557
2bbd681b SSB	558	platform_set_drvdata(pdev, priv);
	559	dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
	560
	561	return 0;
	562	}
	563
	564	static int xlp9xx_i2c_remove(struct platform_device *pdev)
	565	{
	566	struct xlp9xx_i2c_dev *priv;
	567
	568	priv = platform_get_drvdata(pdev);
	569	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
	570	synchronize_irq(priv->irq);
	571	i2c_del_adapter(&priv->adapter);
	572	xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
	573
	574	return 0;
	575	}
	576
	577	static const struct of_device_id xlp9xx_i2c_of_match[] = {
	578	{ .compatible = "netlogic,xlp980-i2c", },
	579	{ /* sentinel */ },
	580	};
06e7b10a	581	MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match);
2bbd681b	582
748c0bbb TJ	583	#ifdef CONFIG_ACPI
	584	static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = {
	585	{"BRCM9007", 0},
4165bd4b	586	{"CAV9007", 0},
748c0bbb TJ	587	{}
	588	};
	589	MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids);
	590	#endif
	591
2bbd681b SSB	592	static struct platform_driver xlp9xx_i2c_driver = {
	593	.probe = xlp9xx_i2c_probe,
	594	.remove = xlp9xx_i2c_remove,
	595	.driver = {
	596	.name = "xlp9xx-i2c",
	597	.of_match_table = xlp9xx_i2c_of_match,
748c0bbb	598	.acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids),
2bbd681b SSB	599	},
	600	};
	601
	602	module_platform_driver(xlp9xx_i2c_driver);
	603
	604	MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
	605	MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
	606	MODULE_LICENSE("GPL v2");