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9615a01f BX |
1 | /* |
2 | * Copyright (C) 2017 Sanechips Technology Co., Ltd. | |
3 | * Copyright 2017 Linaro Ltd. | |
4 | * | |
5 | * Author: Baoyou Xie <baoyou.xie@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/i2c.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
18 | ||
19 | #define REG_CMD 0x04 | |
20 | #define REG_DEVADDR_H 0x0C | |
21 | #define REG_DEVADDR_L 0x10 | |
22 | #define REG_CLK_DIV_FS 0x14 | |
23 | #define REG_CLK_DIV_HS 0x18 | |
24 | #define REG_WRCONF 0x1C | |
25 | #define REG_RDCONF 0x20 | |
26 | #define REG_DATA 0x24 | |
27 | #define REG_STAT 0x28 | |
28 | ||
29 | #define I2C_STOP 0 | |
30 | #define I2C_MASTER BIT(0) | |
31 | #define I2C_ADDR_MODE_TEN BIT(1) | |
32 | #define I2C_IRQ_MSK_ENABLE BIT(3) | |
33 | #define I2C_RW_READ BIT(4) | |
34 | #define I2C_CMB_RW_EN BIT(5) | |
35 | #define I2C_START BIT(6) | |
36 | ||
37 | #define I2C_ADDR_LOW_MASK GENMASK(6, 0) | |
38 | #define I2C_ADDR_LOW_SHIFT 0 | |
39 | #define I2C_ADDR_HI_MASK GENMASK(2, 0) | |
40 | #define I2C_ADDR_HI_SHIFT 7 | |
41 | ||
42 | #define I2C_WFIFO_RESET BIT(7) | |
43 | #define I2C_RFIFO_RESET BIT(7) | |
44 | ||
45 | #define I2C_IRQ_ACK_CLEAR BIT(7) | |
46 | #define I2C_INT_MASK GENMASK(6, 0) | |
47 | ||
48 | #define I2C_TRANS_DONE BIT(0) | |
49 | #define I2C_SR_EDEVICE BIT(1) | |
50 | #define I2C_SR_EDATA BIT(2) | |
51 | ||
52 | #define I2C_FIFO_MAX 16 | |
53 | ||
54 | #define I2C_TIMEOUT msecs_to_jiffies(1000) | |
55 | ||
56 | #define DEV(i2c) (&i2c->adap.dev) | |
57 | ||
58 | struct zx2967_i2c { | |
59 | struct i2c_adapter adap; | |
60 | struct clk *clk; | |
61 | struct completion complete; | |
62 | u32 clk_freq; | |
63 | void __iomem *reg_base; | |
64 | size_t residue; | |
65 | int irq; | |
66 | int msg_rd; | |
67 | u8 *cur_trans; | |
68 | u8 access_cnt; | |
69 | bool is_suspended; | |
70 | int error; | |
71 | }; | |
72 | ||
73 | static void zx2967_i2c_writel(struct zx2967_i2c *i2c, | |
74 | u32 val, unsigned long reg) | |
75 | { | |
76 | writel_relaxed(val, i2c->reg_base + reg); | |
77 | } | |
78 | ||
79 | static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg) | |
80 | { | |
81 | return readl_relaxed(i2c->reg_base + reg); | |
82 | } | |
83 | ||
84 | static void zx2967_i2c_writesb(struct zx2967_i2c *i2c, | |
85 | void *data, unsigned long reg, int len) | |
86 | { | |
87 | writesb(i2c->reg_base + reg, data, len); | |
88 | } | |
89 | ||
90 | static void zx2967_i2c_readsb(struct zx2967_i2c *i2c, | |
91 | void *data, unsigned long reg, int len) | |
92 | { | |
93 | readsb(i2c->reg_base + reg, data, len); | |
94 | } | |
95 | ||
96 | static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c) | |
97 | { | |
98 | u32 status; | |
99 | u32 ctl; | |
100 | ||
101 | status = zx2967_i2c_readl(i2c, REG_STAT); | |
102 | status |= I2C_IRQ_ACK_CLEAR; | |
103 | zx2967_i2c_writel(i2c, status, REG_STAT); | |
104 | ||
105 | ctl = zx2967_i2c_readl(i2c, REG_CMD); | |
106 | if (i2c->msg_rd) | |
107 | ctl |= I2C_RW_READ; | |
108 | else | |
109 | ctl &= ~I2C_RW_READ; | |
110 | ctl &= ~I2C_CMB_RW_EN; | |
111 | ctl |= I2C_START; | |
112 | zx2967_i2c_writel(i2c, ctl, REG_CMD); | |
113 | } | |
114 | ||
115 | static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c) | |
116 | { | |
117 | u32 offset; | |
118 | u32 val; | |
119 | ||
120 | if (i2c->msg_rd) { | |
121 | offset = REG_RDCONF; | |
122 | val = I2C_RFIFO_RESET; | |
123 | } else { | |
124 | offset = REG_WRCONF; | |
125 | val = I2C_WFIFO_RESET; | |
126 | } | |
127 | ||
128 | val |= zx2967_i2c_readl(i2c, offset); | |
129 | zx2967_i2c_writel(i2c, val, offset); | |
130 | } | |
131 | ||
132 | static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size) | |
133 | { | |
134 | u8 val[I2C_FIFO_MAX] = {0}; | |
135 | int i; | |
136 | ||
137 | if (size > I2C_FIFO_MAX) { | |
138 | dev_err(DEV(i2c), "fifo size %d over the max value %d\n", | |
139 | size, I2C_FIFO_MAX); | |
140 | return -EINVAL; | |
141 | } | |
142 | ||
143 | zx2967_i2c_readsb(i2c, val, REG_DATA, size); | |
144 | for (i = 0; i < size; i++) { | |
145 | *i2c->cur_trans++ = val[i]; | |
146 | i2c->residue--; | |
147 | } | |
148 | ||
149 | barrier(); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c) | |
155 | { | |
156 | size_t residue = i2c->residue; | |
157 | u8 *buf = i2c->cur_trans; | |
158 | ||
159 | if (residue == 0) { | |
160 | dev_err(DEV(i2c), "residue is %d\n", (int)residue); | |
161 | return -EINVAL; | |
162 | } | |
163 | ||
164 | if (residue <= I2C_FIFO_MAX) { | |
165 | zx2967_i2c_writesb(i2c, buf, REG_DATA, residue); | |
166 | ||
167 | /* Again update before writing to FIFO to make sure isr sees. */ | |
168 | i2c->residue = 0; | |
169 | i2c->cur_trans = NULL; | |
170 | } else { | |
171 | zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX); | |
172 | i2c->residue -= I2C_FIFO_MAX; | |
173 | i2c->cur_trans += I2C_FIFO_MAX; | |
174 | } | |
175 | ||
176 | barrier(); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c) | |
182 | { | |
183 | u32 val; | |
184 | u32 clk_div; | |
185 | ||
186 | val = I2C_MASTER | I2C_IRQ_MSK_ENABLE; | |
187 | zx2967_i2c_writel(i2c, val, REG_CMD); | |
188 | ||
189 | clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1; | |
190 | zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS); | |
191 | zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS); | |
192 | ||
193 | zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF); | |
194 | zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF); | |
195 | zx2967_i2c_writel(i2c, 1, REG_RDCONF); | |
196 | ||
197 | zx2967_i2c_flush_fifos(i2c); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c) | |
203 | { | |
204 | u32 status; | |
205 | ||
206 | status = zx2967_i2c_readl(i2c, REG_STAT); | |
207 | status |= I2C_IRQ_ACK_CLEAR; | |
208 | zx2967_i2c_writel(i2c, status, REG_STAT); | |
209 | } | |
210 | ||
211 | static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id) | |
212 | { | |
213 | u32 status; | |
214 | struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id; | |
215 | ||
216 | status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK; | |
217 | zx2967_i2c_isr_clr(i2c); | |
218 | ||
219 | if (status & I2C_SR_EDEVICE) | |
220 | i2c->error = -ENXIO; | |
221 | else if (status & I2C_SR_EDATA) | |
222 | i2c->error = -EIO; | |
223 | else if (status & I2C_TRANS_DONE) | |
224 | i2c->error = 0; | |
225 | else | |
226 | goto done; | |
227 | ||
228 | complete(&i2c->complete); | |
229 | done: | |
230 | return IRQ_HANDLED; | |
231 | } | |
232 | ||
233 | static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr) | |
234 | { | |
235 | u16 val; | |
236 | ||
237 | val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK; | |
238 | zx2967_i2c_writel(i2c, val, REG_DEVADDR_L); | |
239 | ||
240 | val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK; | |
241 | zx2967_i2c_writel(i2c, val, REG_DEVADDR_H); | |
242 | if (val) | |
243 | val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN; | |
244 | else | |
245 | val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN; | |
246 | zx2967_i2c_writel(i2c, val, REG_CMD); | |
247 | } | |
248 | ||
249 | static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes) | |
250 | { | |
251 | unsigned long time_left; | |
252 | int rd = i2c->msg_rd; | |
253 | int ret; | |
254 | ||
255 | reinit_completion(&i2c->complete); | |
256 | ||
257 | if (rd) { | |
258 | zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF); | |
259 | } else { | |
260 | ret = zx2967_i2c_fill_tx_fifo(i2c); | |
261 | if (ret) | |
262 | return ret; | |
263 | } | |
264 | ||
265 | zx2967_i2c_start_ctrl(i2c); | |
266 | ||
267 | time_left = wait_for_completion_timeout(&i2c->complete, | |
268 | I2C_TIMEOUT); | |
269 | if (time_left == 0) | |
270 | return -ETIMEDOUT; | |
271 | ||
272 | if (i2c->error) | |
273 | return i2c->error; | |
274 | ||
275 | return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0; | |
276 | } | |
277 | ||
278 | static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c, | |
279 | struct i2c_msg *msg) | |
280 | { | |
281 | int ret; | |
282 | int i; | |
283 | ||
284 | if (msg->len == 0) | |
285 | return -EINVAL; | |
286 | ||
287 | zx2967_i2c_flush_fifos(i2c); | |
288 | ||
289 | i2c->cur_trans = msg->buf; | |
290 | i2c->residue = msg->len; | |
291 | i2c->access_cnt = msg->len / I2C_FIFO_MAX; | |
292 | i2c->msg_rd = msg->flags & I2C_M_RD; | |
293 | ||
294 | for (i = 0; i < i2c->access_cnt; i++) { | |
295 | ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX); | |
296 | if (ret) | |
297 | return ret; | |
298 | } | |
299 | ||
300 | if (i2c->residue > 0) { | |
301 | ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue); | |
302 | if (ret) | |
303 | return ret; | |
304 | } | |
305 | ||
306 | i2c->residue = 0; | |
307 | i2c->access_cnt = 0; | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int zx2967_i2c_xfer(struct i2c_adapter *adap, | |
313 | struct i2c_msg *msgs, int num) | |
314 | { | |
315 | struct zx2967_i2c *i2c = i2c_get_adapdata(adap); | |
316 | int ret; | |
317 | int i; | |
318 | ||
319 | if (i2c->is_suspended) | |
320 | return -EBUSY; | |
321 | ||
322 | zx2967_set_addr(i2c, msgs->addr); | |
323 | ||
324 | for (i = 0; i < num; i++) { | |
325 | ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]); | |
326 | if (ret) | |
327 | return ret; | |
328 | } | |
329 | ||
330 | return num; | |
331 | } | |
332 | ||
333 | static void | |
334 | zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr, | |
335 | char read_write, u8 command, int size, | |
336 | union i2c_smbus_data *data) | |
337 | { | |
338 | u32 val; | |
339 | ||
340 | val = zx2967_i2c_readl(i2c, REG_RDCONF); | |
341 | val |= I2C_RFIFO_RESET; | |
342 | zx2967_i2c_writel(i2c, val, REG_RDCONF); | |
343 | zx2967_set_addr(i2c, addr); | |
344 | val = zx2967_i2c_readl(i2c, REG_CMD); | |
345 | val &= ~I2C_RW_READ; | |
346 | zx2967_i2c_writel(i2c, val, REG_CMD); | |
347 | ||
348 | switch (size) { | |
349 | case I2C_SMBUS_BYTE: | |
350 | zx2967_i2c_writel(i2c, command, REG_DATA); | |
351 | break; | |
352 | case I2C_SMBUS_BYTE_DATA: | |
353 | zx2967_i2c_writel(i2c, command, REG_DATA); | |
354 | if (read_write == I2C_SMBUS_WRITE) | |
355 | zx2967_i2c_writel(i2c, data->byte, REG_DATA); | |
356 | break; | |
357 | case I2C_SMBUS_WORD_DATA: | |
358 | zx2967_i2c_writel(i2c, command, REG_DATA); | |
359 | if (read_write == I2C_SMBUS_WRITE) { | |
360 | zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA); | |
361 | zx2967_i2c_writel(i2c, (data->word & 0xff), | |
362 | REG_DATA); | |
363 | } | |
364 | break; | |
365 | } | |
366 | } | |
367 | ||
368 | static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size, | |
369 | union i2c_smbus_data *data) | |
370 | { | |
371 | unsigned long time_left; | |
372 | u8 buf[2]; | |
373 | u32 val; | |
374 | ||
375 | reinit_completion(&i2c->complete); | |
376 | ||
377 | val = zx2967_i2c_readl(i2c, REG_CMD); | |
378 | val |= I2C_CMB_RW_EN; | |
379 | zx2967_i2c_writel(i2c, val, REG_CMD); | |
380 | ||
381 | val = zx2967_i2c_readl(i2c, REG_CMD); | |
382 | val |= I2C_START; | |
383 | zx2967_i2c_writel(i2c, val, REG_CMD); | |
384 | ||
385 | time_left = wait_for_completion_timeout(&i2c->complete, | |
386 | I2C_TIMEOUT); | |
387 | if (time_left == 0) | |
388 | return -ETIMEDOUT; | |
389 | ||
390 | if (i2c->error) | |
391 | return i2c->error; | |
392 | ||
393 | switch (size) { | |
394 | case I2C_SMBUS_BYTE: | |
395 | case I2C_SMBUS_BYTE_DATA: | |
396 | val = zx2967_i2c_readl(i2c, REG_DATA); | |
397 | data->byte = val; | |
398 | break; | |
399 | case I2C_SMBUS_WORD_DATA: | |
400 | case I2C_SMBUS_PROC_CALL: | |
401 | buf[0] = zx2967_i2c_readl(i2c, REG_DATA); | |
402 | buf[1] = zx2967_i2c_readl(i2c, REG_DATA); | |
403 | data->word = (buf[0] << 8) | buf[1]; | |
404 | break; | |
405 | default: | |
406 | return -EOPNOTSUPP; | |
407 | } | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
412 | static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c) | |
413 | { | |
414 | unsigned long time_left; | |
415 | u32 val; | |
416 | ||
417 | reinit_completion(&i2c->complete); | |
418 | val = zx2967_i2c_readl(i2c, REG_CMD); | |
419 | val |= I2C_START; | |
420 | zx2967_i2c_writel(i2c, val, REG_CMD); | |
421 | ||
422 | time_left = wait_for_completion_timeout(&i2c->complete, | |
423 | I2C_TIMEOUT); | |
424 | if (time_left == 0) | |
425 | return -ETIMEDOUT; | |
426 | ||
427 | if (i2c->error) | |
428 | return i2c->error; | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr, | |
434 | unsigned short flags, char read_write, | |
435 | u8 command, int size, union i2c_smbus_data *data) | |
436 | { | |
437 | struct zx2967_i2c *i2c = i2c_get_adapdata(adap); | |
438 | ||
439 | if (size == I2C_SMBUS_QUICK) | |
440 | read_write = I2C_SMBUS_WRITE; | |
441 | ||
442 | switch (size) { | |
443 | case I2C_SMBUS_QUICK: | |
444 | case I2C_SMBUS_BYTE: | |
445 | case I2C_SMBUS_BYTE_DATA: | |
446 | case I2C_SMBUS_WORD_DATA: | |
447 | zx2967_smbus_xfer_prepare(i2c, addr, read_write, | |
448 | command, size, data); | |
449 | break; | |
450 | default: | |
451 | return -EOPNOTSUPP; | |
452 | } | |
453 | ||
454 | if (read_write == I2C_SMBUS_READ) | |
455 | return zx2967_smbus_xfer_read(i2c, size, data); | |
456 | ||
457 | return zx2967_smbus_xfer_write(i2c); | |
458 | } | |
459 | ||
460 | static u32 zx2967_i2c_func(struct i2c_adapter *adap) | |
461 | { | |
462 | return I2C_FUNC_I2C | | |
463 | I2C_FUNC_SMBUS_QUICK | | |
464 | I2C_FUNC_SMBUS_BYTE | | |
465 | I2C_FUNC_SMBUS_BYTE_DATA | | |
466 | I2C_FUNC_SMBUS_WORD_DATA | | |
467 | I2C_FUNC_SMBUS_BLOCK_DATA | | |
468 | I2C_FUNC_SMBUS_PROC_CALL | | |
469 | I2C_FUNC_SMBUS_I2C_BLOCK; | |
470 | } | |
471 | ||
472 | static int __maybe_unused zx2967_i2c_suspend(struct device *dev) | |
473 | { | |
474 | struct zx2967_i2c *i2c = dev_get_drvdata(dev); | |
475 | ||
476 | i2c->is_suspended = true; | |
477 | clk_disable_unprepare(i2c->clk); | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | static int __maybe_unused zx2967_i2c_resume(struct device *dev) | |
483 | { | |
484 | struct zx2967_i2c *i2c = dev_get_drvdata(dev); | |
485 | ||
486 | i2c->is_suspended = false; | |
487 | clk_prepare_enable(i2c->clk); | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops, | |
493 | zx2967_i2c_suspend, zx2967_i2c_resume); | |
494 | ||
495 | static const struct i2c_algorithm zx2967_i2c_algo = { | |
496 | .master_xfer = zx2967_i2c_xfer, | |
497 | .smbus_xfer = zx2967_smbus_xfer, | |
498 | .functionality = zx2967_i2c_func, | |
499 | }; | |
500 | ||
501 | static const struct of_device_id zx2967_i2c_of_match[] = { | |
502 | { .compatible = "zte,zx296718-i2c", }, | |
503 | { }, | |
504 | }; | |
505 | MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match); | |
506 | ||
507 | static int zx2967_i2c_probe(struct platform_device *pdev) | |
508 | { | |
509 | struct zx2967_i2c *i2c; | |
510 | void __iomem *reg_base; | |
511 | struct resource *res; | |
512 | struct clk *clk; | |
513 | int ret; | |
514 | ||
515 | i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); | |
516 | if (!i2c) | |
517 | return -ENOMEM; | |
518 | ||
519 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
520 | reg_base = devm_ioremap_resource(&pdev->dev, res); | |
521 | if (IS_ERR(reg_base)) | |
522 | return PTR_ERR(reg_base); | |
523 | ||
524 | clk = devm_clk_get(&pdev->dev, NULL); | |
525 | if (IS_ERR(clk)) { | |
526 | dev_err(&pdev->dev, "missing controller clock"); | |
527 | return PTR_ERR(clk); | |
528 | } | |
529 | ||
530 | ret = clk_prepare_enable(clk); | |
531 | if (ret) { | |
532 | dev_err(&pdev->dev, "failed to enable i2c_clk\n"); | |
533 | return ret; | |
534 | } | |
535 | ||
536 | ret = device_property_read_u32(&pdev->dev, "clock-frequency", | |
537 | &i2c->clk_freq); | |
538 | if (ret) { | |
539 | dev_err(&pdev->dev, "missing clock-frequency"); | |
540 | return ret; | |
541 | } | |
542 | ||
543 | ret = platform_get_irq(pdev, 0); | |
544 | if (ret < 0) | |
545 | return ret; | |
546 | ||
547 | i2c->irq = ret; | |
548 | i2c->reg_base = reg_base; | |
549 | i2c->clk = clk; | |
550 | ||
551 | init_completion(&i2c->complete); | |
552 | platform_set_drvdata(pdev, i2c); | |
553 | ||
554 | ret = zx2967_i2c_reset_hardware(i2c); | |
555 | if (ret) { | |
556 | dev_err(&pdev->dev, "failed to initialize i2c controller\n"); | |
557 | goto err_clk_unprepare; | |
558 | } | |
559 | ||
560 | ret = devm_request_irq(&pdev->dev, i2c->irq, | |
561 | zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c); | |
562 | if (ret) { | |
563 | dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq); | |
564 | goto err_clk_unprepare; | |
565 | } | |
566 | ||
567 | i2c_set_adapdata(&i2c->adap, i2c); | |
568 | strlcpy(i2c->adap.name, "zx2967 i2c adapter", | |
569 | sizeof(i2c->adap.name)); | |
570 | i2c->adap.algo = &zx2967_i2c_algo; | |
571 | i2c->adap.nr = pdev->id; | |
572 | i2c->adap.dev.parent = &pdev->dev; | |
573 | i2c->adap.dev.of_node = pdev->dev.of_node; | |
574 | ||
575 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
576 | if (ret) | |
577 | goto err_clk_unprepare; | |
578 | ||
579 | return 0; | |
580 | ||
581 | err_clk_unprepare: | |
582 | clk_disable_unprepare(i2c->clk); | |
583 | return ret; | |
584 | } | |
585 | ||
586 | static int zx2967_i2c_remove(struct platform_device *pdev) | |
587 | { | |
588 | struct zx2967_i2c *i2c = platform_get_drvdata(pdev); | |
589 | ||
590 | i2c_del_adapter(&i2c->adap); | |
591 | clk_disable_unprepare(i2c->clk); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static struct platform_driver zx2967_i2c_driver = { | |
597 | .probe = zx2967_i2c_probe, | |
598 | .remove = zx2967_i2c_remove, | |
599 | .driver = { | |
600 | .name = "zx2967_i2c", | |
601 | .of_match_table = zx2967_i2c_of_match, | |
602 | .pm = &zx2967_i2c_dev_pm_ops, | |
603 | }, | |
604 | }; | |
605 | module_platform_driver(zx2967_i2c_driver); | |
606 | ||
607 | MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>"); | |
608 | MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver"); | |
609 | MODULE_LICENSE("GPL v2"); |