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99c3adb4 1/*
1da177e4
LT
2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
3
4 National Semiconductor SCx200 ACCESS.bus support
16ffc5c9 5 Also supports the AMD CS5535 and AMD CS5536
99c3adb4 6
1da177e4
LT
7 Based on i2c-keywest.c which is:
8 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
99c3adb4 10
1da177e4
LT
11 This program is free software; you can redistribute it and/or
12 modify it under the terms of the GNU General Public License as
13 published by the Free Software Foundation; either version 2 of the
14 License, or (at your option) any later version.
99c3adb4 15
1da177e4
LT
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 General Public License for more details.
99c3adb4 20
1da177e4
LT
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
1da177e4
LT
24*/
25
1da177e4
LT
26#include <linux/module.h>
27#include <linux/errno.h>
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <linux/i2c.h>
31#include <linux/smp_lock.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
3fb9a655 34#include <linux/mutex.h>
1da177e4
LT
35#include <asm/io.h>
36
37#include <linux/scx200.h>
38
39#define NAME "scx200_acb"
40
41MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
42MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
43MODULE_LICENSE("GPL");
44
45#define MAX_DEVICES 4
46static int base[MAX_DEVICES] = { 0x820, 0x840 };
47module_param_array(base, int, NULL, 0);
48MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
49
f933ff50 50#define POLL_TIMEOUT (HZ/5)
1da177e4
LT
51
52enum scx200_acb_state {
53 state_idle,
54 state_address,
55 state_command,
56 state_repeat_start,
57 state_quick,
58 state_read,
59 state_write,
60};
61
62static const char *scx200_acb_state_name[] = {
63 "idle",
64 "address",
65 "command",
66 "repeat_start",
67 "quick",
68 "read",
69 "write",
70};
71
72/* Physical interface */
99c3adb4 73struct scx200_acb_iface {
1da177e4
LT
74 struct scx200_acb_iface *next;
75 struct i2c_adapter adapter;
76 unsigned base;
3fb9a655 77 struct mutex mutex;
1da177e4
LT
78
79 /* State machine data */
80 enum scx200_acb_state state;
81 int result;
82 u8 address_byte;
83 u8 command;
84 u8 *ptr;
85 char needs_reset;
86 unsigned len;
80cd3a87
JC
87
88 /* PCI device info */
89 struct pci_dev *pdev;
90 int bar;
1da177e4
LT
91};
92
93/* Register Definitions */
94#define ACBSDA (iface->base + 0)
95#define ACBST (iface->base + 1)
96#define ACBST_SDAST 0x40 /* SDA Status */
99c3adb4 97#define ACBST_BER 0x20
1da177e4
LT
98#define ACBST_NEGACK 0x10 /* Negative Acknowledge */
99#define ACBST_STASTR 0x08 /* Stall After Start */
100#define ACBST_MASTER 0x02
101#define ACBCST (iface->base + 2)
102#define ACBCST_BB 0x02
103#define ACBCTL1 (iface->base + 3)
104#define ACBCTL1_STASTRE 0x80
105#define ACBCTL1_NMINTE 0x40
99c3adb4
BG
106#define ACBCTL1_ACK 0x10
107#define ACBCTL1_STOP 0x02
108#define ACBCTL1_START 0x01
1da177e4
LT
109#define ACBADDR (iface->base + 4)
110#define ACBCTL2 (iface->base + 5)
111#define ACBCTL2_ENABLE 0x01
112
113/************************************************************************/
114
115static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
116{
117 const char *errmsg;
118
ef4d9275
BG
119 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
120 scx200_acb_state_name[iface->state], status);
1da177e4
LT
121
122 if (status & ACBST_BER) {
123 errmsg = "bus error";
124 goto error;
125 }
126 if (!(status & ACBST_MASTER)) {
127 errmsg = "not master";
128 goto error;
129 }
9b7b6d3b
BG
130 if (status & ACBST_NEGACK) {
131 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
132 scx200_acb_state_name[iface->state]);
133
134 iface->state = state_idle;
135 iface->result = -ENXIO;
136
137 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
138 outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
95563d34
JC
139
140 /* Reset the status register */
141 outb(0, ACBST);
9b7b6d3b
BG
142 return;
143 }
1da177e4
LT
144
145 switch (iface->state) {
146 case state_idle:
147 dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
148 break;
149
150 case state_address:
151 /* Do a pointer write first */
152 outb(iface->address_byte & ~1, ACBSDA);
153
154 iface->state = state_command;
155 break;
156
157 case state_command:
158 outb(iface->command, ACBSDA);
159
160 if (iface->address_byte & 1)
161 iface->state = state_repeat_start;
162 else
163 iface->state = state_write;
164 break;
165
166 case state_repeat_start:
167 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
168 /* fallthrough */
99c3adb4 169
1da177e4
LT
170 case state_quick:
171 if (iface->address_byte & 1) {
99c3adb4 172 if (iface->len == 1)
1da177e4
LT
173 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
174 else
175 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
176 outb(iface->address_byte, ACBSDA);
177
178 iface->state = state_read;
179 } else {
180 outb(iface->address_byte, ACBSDA);
181
182 iface->state = state_write;
183 }
184 break;
185
186 case state_read:
fd627a01
TA
187 /* Set ACK if _next_ byte will be the last one */
188 if (iface->len == 2)
1da177e4
LT
189 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
190 else
191 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
192
fd627a01 193 if (iface->len == 1) {
1da177e4
LT
194 iface->result = 0;
195 iface->state = state_idle;
196 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
197 }
198
fd627a01
TA
199 *iface->ptr++ = inb(ACBSDA);
200 --iface->len;
201
1da177e4
LT
202 break;
203
204 case state_write:
205 if (iface->len == 0) {
206 iface->result = 0;
207 iface->state = state_idle;
208 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
209 break;
210 }
99c3adb4 211
1da177e4
LT
212 outb(*iface->ptr++, ACBSDA);
213 --iface->len;
99c3adb4 214
1da177e4
LT
215 break;
216 }
217
218 return;
219
1da177e4
LT
220 error:
221 dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
222 scx200_acb_state_name[iface->state]);
223
224 iface->state = state_idle;
225 iface->result = -EIO;
226 iface->needs_reset = 1;
227}
228
1da177e4
LT
229static void scx200_acb_poll(struct scx200_acb_iface *iface)
230{
9b7b6d3b 231 u8 status;
1da177e4
LT
232 unsigned long timeout;
233
234 timeout = jiffies + POLL_TIMEOUT;
235 while (time_before(jiffies, timeout)) {
236 status = inb(ACBST);
95563d34
JC
237
238 /* Reset the status register to avoid the hang */
239 outb(0, ACBST);
240
1da177e4
LT
241 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
242 scx200_acb_machine(iface, status);
243 return;
244 }
f933ff50 245 yield();
1da177e4
LT
246 }
247
9b7b6d3b
BG
248 dev_err(&iface->adapter.dev, "timeout in state %s\n",
249 scx200_acb_state_name[iface->state]);
250
251 iface->state = state_idle;
252 iface->result = -EIO;
253 iface->needs_reset = 1;
1da177e4 254}
1da177e4
LT
255
256static void scx200_acb_reset(struct scx200_acb_iface *iface)
257{
258 /* Disable the ACCESS.bus device and Configure the SCL
99c3adb4 259 frequency: 16 clock cycles */
1da177e4
LT
260 outb(0x70, ACBCTL2);
261 /* Polling mode */
262 outb(0, ACBCTL1);
263 /* Disable slave address */
264 outb(0, ACBADDR);
265 /* Enable the ACCESS.bus device */
266 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
267 /* Free STALL after START */
268 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
269 /* Send a STOP */
270 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
271 /* Clear BER, NEGACK and STASTR bits */
272 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
273 /* Clear BB bit */
274 outb(inb(ACBCST) | ACBCST_BB, ACBCST);
275}
276
277static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
99c3adb4
BG
278 u16 address, unsigned short flags,
279 char rw, u8 command, int size,
280 union i2c_smbus_data *data)
1da177e4
LT
281{
282 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
283 int len;
284 u8 *buffer;
285 u16 cur_word;
286 int rc;
287
288 switch (size) {
289 case I2C_SMBUS_QUICK:
99c3adb4
BG
290 len = 0;
291 buffer = NULL;
292 break;
293
1da177e4 294 case I2C_SMBUS_BYTE:
9b7b6d3b
BG
295 len = 1;
296 buffer = rw ? &data->byte : &command;
99c3adb4
BG
297 break;
298
1da177e4 299 case I2C_SMBUS_BYTE_DATA:
99c3adb4
BG
300 len = 1;
301 buffer = &data->byte;
302 break;
303
1da177e4
LT
304 case I2C_SMBUS_WORD_DATA:
305 len = 2;
99c3adb4
BG
306 cur_word = cpu_to_le16(data->word);
307 buffer = (u8 *)&cur_word;
1da177e4 308 break;
99c3adb4 309
c3efacaa
JD
310 case I2C_SMBUS_I2C_BLOCK_DATA:
311 if (rw == I2C_SMBUS_READ)
312 data->block[0] = I2C_SMBUS_BLOCK_MAX; /* For now */
99c3adb4 313 len = data->block[0];
c3efacaa
JD
314 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
315 return -EINVAL;
99c3adb4 316 buffer = &data->block[1];
1da177e4 317 break;
99c3adb4 318
1da177e4 319 default:
99c3adb4 320 return -EINVAL;
1da177e4
LT
321 }
322
ef4d9275
BG
323 dev_dbg(&adapter->dev,
324 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
325 size, address, command, len, rw);
1da177e4
LT
326
327 if (!len && rw == I2C_SMBUS_READ) {
ef4d9275 328 dev_dbg(&adapter->dev, "zero length read\n");
1da177e4
LT
329 return -EINVAL;
330 }
331
3fb9a655 332 mutex_lock(&iface->mutex);
1da177e4 333
9b7b6d3b 334 iface->address_byte = (address << 1) | rw;
1da177e4
LT
335 iface->command = command;
336 iface->ptr = buffer;
337 iface->len = len;
338 iface->result = -EINVAL;
339 iface->needs_reset = 0;
340
341 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
342
343 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
344 iface->state = state_quick;
345 else
346 iface->state = state_address;
347
1da177e4
LT
348 while (iface->state != state_idle)
349 scx200_acb_poll(iface);
1da177e4
LT
350
351 if (iface->needs_reset)
352 scx200_acb_reset(iface);
353
354 rc = iface->result;
355
3fb9a655 356 mutex_unlock(&iface->mutex);
1da177e4
LT
357
358 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
99c3adb4 359 data->word = le16_to_cpu(cur_word);
1da177e4
LT
360
361#ifdef DEBUG
ef4d9275 362 dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
1da177e4
LT
363 if (buffer) {
364 int i;
365 printk(" data:");
366 for (i = 0; i < len; ++i)
367 printk(" %02x", buffer[i]);
368 }
369 printk("\n");
370#endif
371
372 return rc;
373}
374
375static u32 scx200_acb_func(struct i2c_adapter *adapter)
376{
377 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
378 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
c3efacaa 379 I2C_FUNC_SMBUS_I2C_BLOCK;
1da177e4
LT
380}
381
382/* For now, we only handle combined mode (smbus) */
383static struct i2c_algorithm scx200_acb_algorithm = {
1da177e4
LT
384 .smbus_xfer = scx200_acb_smbus_xfer,
385 .functionality = scx200_acb_func,
386};
387
388static struct scx200_acb_iface *scx200_acb_list;
8a05940d 389static DECLARE_MUTEX(scx200_acb_list_mutex);
1da177e4 390
99173926 391static __init int scx200_acb_probe(struct scx200_acb_iface *iface)
1da177e4
LT
392{
393 u8 val;
394
395 /* Disable the ACCESS.bus device and Configure the SCL
99c3adb4 396 frequency: 16 clock cycles */
1da177e4
LT
397 outb(0x70, ACBCTL2);
398
399 if (inb(ACBCTL2) != 0x70) {
ef4d9275 400 pr_debug(NAME ": ACBCTL2 readback failed\n");
1da177e4
LT
401 return -ENXIO;
402 }
403
404 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
405
406 val = inb(ACBCTL1);
407 if (val) {
ef4d9275
BG
408 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
409 val);
1da177e4
LT
410 return -ENXIO;
411 }
412
413 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
414
415 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
416
417 val = inb(ACBCTL1);
418 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
ef4d9275
BG
419 pr_debug(NAME ": enabled, but NMINTE won't be set, "
420 "ACBCTL1=0x%02x\n", val);
1da177e4
LT
421 return -ENXIO;
422 }
423
424 return 0;
425}
426
80cd3a87
JC
427static __init struct scx200_acb_iface *scx200_create_iface(const char *text,
428 int index)
1da177e4
LT
429{
430 struct scx200_acb_iface *iface;
431 struct i2c_adapter *adapter;
1da177e4 432
5263ebb5 433 iface = kzalloc(sizeof(*iface), GFP_KERNEL);
1da177e4
LT
434 if (!iface) {
435 printk(KERN_ERR NAME ": can't allocate memory\n");
80cd3a87 436 return NULL;
1da177e4
LT
437 }
438
1da177e4
LT
439 adapter = &iface->adapter;
440 i2c_set_adapdata(adapter, iface);
16ffc5c9 441 snprintf(adapter->name, I2C_NAME_SIZE, "%s ACB%d", text, index);
1da177e4 442 adapter->owner = THIS_MODULE;
1684a984 443 adapter->id = I2C_HW_SMBUS_SCX200;
1da177e4
LT
444 adapter->algo = &scx200_acb_algorithm;
445 adapter->class = I2C_CLASS_HWMON;
446
3fb9a655 447 mutex_init(&iface->mutex);
1da177e4 448
80cd3a87
JC
449 return iface;
450}
451
452static int __init scx200_acb_create(struct scx200_acb_iface *iface)
453{
454 struct i2c_adapter *adapter;
455 int rc;
456
457 adapter = &iface->adapter;
1da177e4
LT
458
459 rc = scx200_acb_probe(iface);
460 if (rc) {
ef4d9275 461 printk(KERN_WARNING NAME ": probe failed\n");
80cd3a87 462 return rc;
1da177e4
LT
463 }
464
465 scx200_acb_reset(iface);
466
467 if (i2c_add_adapter(adapter) < 0) {
ef4d9275 468 printk(KERN_ERR NAME ": failed to register\n");
80cd3a87 469 return -ENODEV;
1da177e4
LT
470 }
471
8a05940d 472 down(&scx200_acb_list_mutex);
1da177e4
LT
473 iface->next = scx200_acb_list;
474 scx200_acb_list = iface;
8a05940d 475 up(&scx200_acb_list_mutex);
1da177e4
LT
476
477 return 0;
80cd3a87 478}
1da177e4 479
80cd3a87
JC
480static __init int scx200_create_pci(const char *text, struct pci_dev *pdev,
481 int bar)
482{
483 struct scx200_acb_iface *iface;
484 int rc;
485
486 iface = scx200_create_iface(text, 0);
487
488 if (iface == NULL)
489 return -ENOMEM;
490
491 iface->pdev = pdev;
492 iface->bar = bar;
493
494 pci_enable_device_bars(iface->pdev, 1 << iface->bar);
495
496 rc = pci_request_region(iface->pdev, iface->bar, iface->adapter.name);
497
498 if (rc != 0) {
499 printk(KERN_ERR NAME ": can't allocate PCI BAR %d\n",
500 iface->bar);
501 goto errout_free;
502 }
503
504 iface->base = pci_resource_start(iface->pdev, iface->bar);
505 rc = scx200_acb_create(iface);
506
507 if (rc == 0)
508 return 0;
509
510 pci_release_region(iface->pdev, iface->bar);
511 pci_dev_put(iface->pdev);
9b7b6d3b
BG
512 errout_free:
513 kfree(iface);
1da177e4
LT
514 return rc;
515}
516
80cd3a87
JC
517static int __init scx200_create_isa(const char *text, unsigned long base,
518 int index)
519{
520 struct scx200_acb_iface *iface;
521 int rc;
522
523 iface = scx200_create_iface(text, index);
524
525 if (iface == NULL)
526 return -ENOMEM;
527
528 if (request_region(base, 8, iface->adapter.name) == 0) {
529 printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n",
530 base, base + 8 - 1);
531 rc = -EBUSY;
532 goto errout_free;
533 }
534
535 iface->base = base;
536 rc = scx200_acb_create(iface);
537
538 if (rc == 0)
539 return 0;
1da177e4 540
80cd3a87
JC
541 release_region(base, 8);
542 errout_free:
543 kfree(iface);
544 return rc;
545}
546
547/* Driver data is an index into the scx200_data array that indicates
548 * the name and the BAR where the I/O address resource is located. ISA
549 * devices are flagged with a bar value of -1 */
550
551static struct pci_device_id scx200_pci[] = {
552 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE),
553 .driver_data = 0 },
554 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE),
555 .driver_data = 0 },
556 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA),
557 .driver_data = 1 },
558 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA),
559 .driver_data = 2 }
16ffc5c9
BG
560};
561
80cd3a87
JC
562static struct {
563 const char *name;
564 int bar;
565} scx200_data[] = {
566 { "SCx200", -1 },
567 { "CS5535", 0 },
568 { "CS5536", 0 }
569};
16ffc5c9 570
80cd3a87 571static __init int scx200_scan_pci(void)
16ffc5c9 572{
80cd3a87
JC
573 int data, dev;
574 int rc = -ENODEV;
575 struct pci_dev *pdev;
576
577 for(dev = 0; dev < ARRAY_SIZE(scx200_pci); dev++) {
578 pdev = pci_get_device(scx200_pci[dev].vendor,
579 scx200_pci[dev].device, NULL);
580
581 if (pdev == NULL)
582 continue;
583
584 data = scx200_pci[dev].driver_data;
585
586 /* if .bar is greater or equal to zero, this is a
587 * PCI device - otherwise, we assume
588 that the ports are ISA based
589 */
590
591 if (scx200_data[data].bar >= 0)
592 rc = scx200_create_pci(scx200_data[data].name, pdev,
593 scx200_data[data].bar);
594 else {
595 int i;
596
597 for (i = 0; i < MAX_DEVICES; ++i) {
598 if (base[i] == 0)
599 continue;
600
601 rc = scx200_create_isa(scx200_data[data].name,
602 base[i],
603 i);
604 }
605 }
16ffc5c9 606
80cd3a87 607 break;
16ffc5c9
BG
608 }
609
80cd3a87 610 return rc;
16ffc5c9
BG
611}
612
1da177e4
LT
613static int __init scx200_acb_init(void)
614{
80cd3a87 615 int rc;
1da177e4
LT
616
617 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
618
80cd3a87 619 rc = scx200_scan_pci();
1da177e4 620
6f9c2963
JD
621 /* If at least one bus was created, init must succeed */
622 if (scx200_acb_list)
623 return 0;
1da177e4
LT
624 return rc;
625}
626
627static void __exit scx200_acb_cleanup(void)
628{
629 struct scx200_acb_iface *iface;
99c3adb4 630
8a05940d 631 down(&scx200_acb_list_mutex);
1da177e4
LT
632 while ((iface = scx200_acb_list) != NULL) {
633 scx200_acb_list = iface->next;
8a05940d 634 up(&scx200_acb_list_mutex);
1da177e4
LT
635
636 i2c_del_adapter(&iface->adapter);
80cd3a87
JC
637
638 if (iface->pdev) {
639 pci_release_region(iface->pdev, iface->bar);
640 pci_dev_put(iface->pdev);
641 }
642 else
643 release_region(iface->base, 8);
644
1da177e4 645 kfree(iface);
8a05940d 646 down(&scx200_acb_list_mutex);
1da177e4 647 }
8a05940d 648 up(&scx200_acb_list_mutex);
1da177e4
LT
649}
650
651module_init(scx200_acb_init);
652module_exit(scx200_acb_cleanup);