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alim15x3: fix PIO timings calculations
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1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
4 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
5 *
6 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
7 * May be copied or modified under the terms of the GNU General Public License
ccd32e22 8 * Copyright (C) 2002 Alan Cox
1da177e4 9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
21b82477 10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
3c8cc8df 11 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4
LT
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
1da177e4
LT
30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/kernel.h>
33#include <linux/pci.h>
1da177e4
LT
34#include <linux/ide.h>
35#include <linux/init.h>
95ba8c17 36#include <linux/dmi.h>
1da177e4
LT
37
38#include <asm/io.h>
39
ced3ec8a
BZ
40#define DRV_NAME "alim15x3"
41
1da177e4
LT
42/*
43 * ALi devices are not plug in. Otherwise these static values would
44 * need to go. They ought to go away anyway
45 */
46
47static u8 m5229_revision;
48static u8 chip_is_1543c_e;
49static struct pci_dev *isa_dev;
50
1da177e4 51/**
88b2b32b 52 * ali_set_pio_mode - set host controller for PIO mode
26bcb879
BZ
53 * @drive: drive
54 * @pio: PIO mode number
21b82477 55 *
26bcb879 56 * Program the controller for the given PIO mode.
1da177e4 57 */
26bcb879 58
88b2b32b 59static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 60{
898ec223 61 ide_hwif_t *hwif = drive->hwif;
36501650 62 struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 63 unsigned long flags;
30e5ee4d 64 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
3c8cc8df 65 unsigned long T = 1000000 / bus_speed; /* PCI clock based */
1da177e4
LT
66 int port = hwif->channel ? 0x5c : 0x58;
67 int portFIFO = hwif->channel ? 0x55 : 0x54;
123995b9 68 u8 cd_dma_fifo = 0, unit = drive->dn & 1;
3c8cc8df 69 struct ide_timing t;
1da177e4 70
3c8cc8df
BZ
71 ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1);
72
73 t.setup = clamp_val(t.setup, 1, 8) & 7;
74 t.active = clamp_val(t.active, 1, 8) & 7;
75 t.recover = clamp_val(t.recover, 1, 16) & 15;
1da177e4 76
1da177e4 77 local_irq_save(flags);
3c8cc8df 78
1da177e4
LT
79 /*
80 * PIO mode => ATA FIFO on, ATAPI FIFO off
81 */
82 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
83 if (drive->media==ide_disk) {
84 if (unit) {
85 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
86 } else {
87 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
88 }
89 } else {
90 if (unit) {
91 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
92 } else {
93 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
94 }
95 }
3c8cc8df
BZ
96
97 pci_write_config_byte(dev, port, t.setup);
98 pci_write_config_byte(dev, port + unit + 2,
99 (t.active << 4) | t.recover);
100
1da177e4 101 local_irq_restore(flags);
21b82477
SS
102}
103
1da177e4 104/**
2d5eaa6d
BZ
105 * ali_udma_filter - compute UDMA mask
106 * @drive: IDE device
1da177e4 107 *
2d5eaa6d
BZ
108 * Return available UDMA modes.
109 *
110 * The actual rules for the ALi are:
1da177e4
LT
111 * No UDMA on revisions <= 0x20
112 * Disk only for revisions < 0xC2
63b1623e 113 * Not WDC drives on M1543C-E (?)
1da177e4 114 */
1da177e4 115
2d5eaa6d 116static u8 ali_udma_filter(ide_drive_t *drive)
1da177e4 117{
2d5eaa6d
BZ
118 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
119 if (drive->media != ide_disk)
120 return 0;
2db3dae5 121 if (chip_is_1543c_e &&
4dde4492 122 strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
2d5eaa6d 123 return 0;
1da177e4
LT
124 }
125
2d5eaa6d 126 return drive->hwif->ultra_mask;
1da177e4
LT
127}
128
129/**
88b2b32b
BZ
130 * ali_set_dma_mode - set host controller for DMA mode
131 * @drive: drive
132 * @speed: DMA mode
1da177e4
LT
133 *
134 * Configure the hardware for the desired IDE transfer mode.
1da177e4 135 */
f212ff28 136
88b2b32b 137static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 138{
898ec223 139 ide_hwif_t *hwif = drive->hwif;
36501650 140 struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 141 u8 speed1 = speed;
123995b9 142 u8 unit = drive->dn & 1;
1da177e4
LT
143 u8 tmpbyte = 0x00;
144 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
145
146 if (speed == XFER_UDMA_6)
147 speed1 = 0x47;
148
149 if (speed < XFER_UDMA_0) {
150 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
151 /*
152 * clear "ultra enable" bit
153 */
154 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
155 tmpbyte &= ultra_enable;
156 pci_write_config_byte(dev, m5229_udma, tmpbyte);
157
a6fe837e
BZ
158 /*
159 * FIXME: Oh, my... DMA timings are never set.
160 */
1da177e4
LT
161 } else {
162 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
163 tmpbyte &= (0x0f << ((1-unit) << 2));
164 /*
165 * enable ultra dma and set timing
166 */
167 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
168 pci_write_config_byte(dev, m5229_udma, tmpbyte);
169 if (speed >= XFER_UDMA_3) {
170 pci_read_config_byte(dev, 0x4b, &tmpbyte);
171 tmpbyte |= 1;
172 pci_write_config_byte(dev, 0x4b, tmpbyte);
173 }
174 }
1da177e4
LT
175}
176
1da177e4 177/**
8a4a5738 178 * ali_dma_check - DMA check
1da177e4 179 * @drive: target device
22981694 180 * @cmd: command
1da177e4
LT
181 *
182 * Returns 1 if the DMA cannot be performed, zero on success.
183 */
184
8a4a5738 185static int ali_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
1da177e4
LT
186{
187 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
22981694 188 if (cmd->tf_flags & IDE_TFLAG_WRITE)
1da177e4
LT
189 return 1; /* try PIO instead of DMA */
190 }
8a4a5738 191 return 0;
1da177e4
LT
192}
193
194/**
195 * init_chipset_ali15x3 - Initialise an ALi IDE controller
196 * @dev: PCI device
1da177e4
LT
197 *
198 * This function initializes the ALI IDE controller and where
199 * appropriate also sets up the 1533 southbridge.
200 */
a326b02b 201
2ed0ef54 202static int init_chipset_ali15x3(struct pci_dev *dev)
1da177e4
LT
203{
204 unsigned long flags;
205 u8 tmpbyte;
b1489009 206 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
1da177e4 207
44c10138 208 m5229_revision = dev->revision;
1da177e4 209
b1489009 210 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
1da177e4 211
1da177e4
LT
212 local_irq_save(flags);
213
214 if (m5229_revision < 0xC2) {
215 /*
216 * revision 0x20 (1543-E, 1543-F)
217 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
218 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
219 */
220 pci_read_config_byte(dev, 0x4b, &tmpbyte);
221 /*
222 * clear bit 7
223 */
224 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
cad221aa
BZ
225 /*
226 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
227 */
228 if (m5229_revision >= 0x20 && isa_dev) {
229 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
230 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
231 }
b1489009 232 goto out;
1da177e4
LT
233 }
234
235 /*
236 * 1543C-B?, 1535, 1535D, 1553
237 * Note 1: not all "motherboard" support this detection
238 * Note 2: if no udma 66 device, the detection may "error".
239 * but in this case, we will not set the device to
240 * ultra 66, the detection result is not important
241 */
242
243 /*
244 * enable "Cable Detection", m5229, 0x4b, bit3
245 */
246 pci_read_config_byte(dev, 0x4b, &tmpbyte);
247 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
248
249 /*
250 * We should only tune the 1533 enable if we are using an ALi
251 * North bridge. We might have no north found on some zany
252 * box without a device at 0:0.0. The ALi bridge will be at
253 * 0:0.0 so if we didn't find one we know what is cooking.
254 */
b1489009
AC
255 if (north && north->vendor != PCI_VENDOR_ID_AL)
256 goto out;
1da177e4
LT
257
258 if (m5229_revision < 0xC5 && isa_dev)
259 {
260 /*
261 * set south-bridge's enable bit, m1533, 0x79
262 */
263
264 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
265 if (m5229_revision == 0xC2) {
266 /*
267 * 1543C-B0 (m1533, 0x79, bit 2)
268 */
269 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
270 } else if (m5229_revision >= 0xC3) {
271 /*
272 * 1553/1535 (m1533, 0x79, bit 1)
273 */
274 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
275 }
276 }
cad221aa 277
b1489009 278out:
cad221aa
BZ
279 /*
280 * CD_ROM DMA on (m5229, 0x53, bit0)
281 * Enable this bit even if we want to use PIO.
282 * PIO FIFO off (m5229, 0x53, bit1)
283 * The hardware will use 0x54h and 0x55h to control PIO FIFO.
284 * (Not on later devices it seems)
285 *
286 * 0x53 changes meaning on later revs - we must no touch
287 * bit 1 on them. Need to check if 0x20 is the right break.
288 */
289 if (m5229_revision >= 0x20) {
290 pci_read_config_byte(dev, 0x53, &tmpbyte);
291
292 if (m5229_revision <= 0x20)
293 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
294 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
295 tmpbyte |= 0x03;
296 else
297 tmpbyte |= 0x01;
298
299 pci_write_config_byte(dev, 0x53, tmpbyte);
300 }
b1489009
AC
301 pci_dev_put(north);
302 pci_dev_put(isa_dev);
1da177e4
LT
303 local_irq_restore(flags);
304 return 0;
305}
306
95ba8c17
BZ
307/*
308 * Cable special cases
309 */
310
1855256c 311static const struct dmi_system_id cable_dmi_table[] = {
95ba8c17
BZ
312 {
313 .ident = "HP Pavilion N5430",
314 .matches = {
315 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
8663fd6d 316 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
95ba8c17
BZ
317 },
318 },
03e6f489
DE
319 {
320 .ident = "Toshiba Satellite S1800-814",
321 .matches = {
322 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
323 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
324 },
325 },
95ba8c17
BZ
326 { }
327};
328
329static int ali_cable_override(struct pci_dev *pdev)
330{
331 /* Fujitsu P2000 */
332 if (pdev->subsystem_vendor == 0x10CF &&
333 pdev->subsystem_device == 0x10AF)
334 return 1;
335
d151456a
BZ
336 /* Mitac 8317 (Winbook-A) and relatives */
337 if (pdev->subsystem_vendor == 0x1071 &&
338 pdev->subsystem_device == 0x8317)
339 return 1;
340
95ba8c17
BZ
341 /* Systems by DMI */
342 if (dmi_check_system(cable_dmi_table))
343 return 1;
344
345 return 0;
346}
347
1da177e4 348/**
ac95beed 349 * ali_cable_detect - cable detection
1da177e4
LT
350 * @hwif: IDE interface
351 *
352 * This checks if the controller and the cable are capable
353 * of UDMA66 transfers. It doesn't check the drives.
354 * But see note 2 below!
355 *
356 * FIXME: frobs bits that are not defined on newer ALi devicea
357 */
358
f454cbe8 359static u8 ali_cable_detect(ide_hwif_t *hwif)
1da177e4 360{
36501650 361 struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 362 unsigned long flags;
95ba8c17 363 u8 cbl = ATA_CBL_PATA40, tmpbyte;
1da177e4
LT
364
365 local_irq_save(flags);
366
367 if (m5229_revision >= 0xC2) {
368 /*
95ba8c17
BZ
369 * m5229 80-pin cable detection (from Host View)
370 *
371 * 0x4a bit0 is 0 => primary channel has 80-pin
372 * 0x4a bit1 is 0 => secondary channel has 80-pin
373 *
374 * Certain laptops use short but suitable cables
375 * and don't implement the detect logic.
1da177e4 376 */
95ba8c17
BZ
377 if (ali_cable_override(dev))
378 cbl = ATA_CBL_PATA40_SHORT;
379 else {
380 pci_read_config_byte(dev, 0x4a, &tmpbyte);
381 if ((tmpbyte & (1 << hwif->channel)) == 0)
382 cbl = ATA_CBL_PATA80;
383 }
1da177e4
LT
384 }
385
1da177e4
LT
386 local_irq_restore(flags);
387
95ba8c17 388 return cbl;
1da177e4
LT
389}
390
03682411 391#ifndef CONFIG_SPARC64
1da177e4
LT
392/**
393 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
394 * @hwif: interface to configure
395 *
396 * Obtain the IRQ tables for an ALi based IDE solution on the PC
397 * class platforms. This part of the code isn't applicable to the
03682411 398 * Sparc systems.
1da177e4
LT
399 */
400
c2f12589 401static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
1da177e4
LT
402{
403 u8 ideic, inmir;
404 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
405 1, 11, 0, 12, 0, 14, 0, 15 };
406 int irq = -1;
407
1da177e4
LT
408 if (isa_dev) {
409 /*
410 * read IDE interface control
411 */
412 pci_read_config_byte(isa_dev, 0x58, &ideic);
413
414 /* bit0, bit1 */
415 ideic = ideic & 0x03;
416
417 /* get IRQ for IDE Controller */
418 if ((hwif->channel && ideic == 0x03) ||
419 (!hwif->channel && !ideic)) {
420 /*
421 * get SIRQ1 routing table
422 */
423 pci_read_config_byte(isa_dev, 0x44, &inmir);
424 inmir = inmir & 0x0f;
425 irq = irq_routing_table[inmir];
426 } else if (hwif->channel && !(ideic & 0x01)) {
427 /*
428 * get SIRQ2 routing table
429 */
430 pci_read_config_byte(isa_dev, 0x75, &inmir);
431 inmir = inmir & 0x0f;
432 irq = irq_routing_table[inmir];
433 }
434 if(irq >= 0)
435 hwif->irq = irq;
436 }
1da177e4 437}
6d1cee44
AV
438#else
439#define init_hwif_ali15x3 NULL
03682411 440#endif /* CONFIG_SPARC64 */
1da177e4
LT
441
442/**
443 * init_dma_ali15x3 - set up DMA on ALi15x3
444 * @hwif: IDE interface
b123f56e 445 * @d: IDE port info
1da177e4 446 *
b123f56e 447 * Set up the DMA functionality on the ALi 15x3.
1da177e4
LT
448 */
449
b123f56e
BZ
450static int __devinit init_dma_ali15x3(ide_hwif_t *hwif,
451 const struct ide_port_info *d)
1da177e4 452{
b123f56e
BZ
453 struct pci_dev *dev = to_pci_dev(hwif->dev);
454 unsigned long base = ide_pci_dma_base(hwif, d);
455
ebb00fb5
BZ
456 if (base == 0)
457 return -1;
458
459 hwif->dma_base = base;
460
461 if (ide_pci_check_simplex(hwif, d) < 0)
462 return -1;
463
464 if (ide_pci_set_master(dev, d->name) < 0)
b123f56e
BZ
465 return -1;
466
0ecdca26 467 if (!hwif->channel)
b123f56e
BZ
468 outb(inb(base + 2) & 0x60, base + 2);
469
470 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
471 hwif->name, base, base + 7);
472
473 if (ide_allocate_dma_engine(hwif))
474 return -1;
475
b123f56e 476 return 0;
1da177e4
LT
477}
478
ac95beed
BZ
479static const struct ide_port_ops ali_port_ops = {
480 .set_pio_mode = ali_set_pio_mode,
481 .set_dma_mode = ali_set_dma_mode,
482 .udma_filter = ali_udma_filter,
483 .cable_detect = ali_cable_detect,
484};
485
f37afdac
BZ
486static const struct ide_dma_ops ali_dma_ops = {
487 .dma_host_set = ide_dma_host_set,
8a4a5738 488 .dma_setup = ide_dma_setup,
f37afdac 489 .dma_start = ide_dma_start,
653bcf52 490 .dma_end = ide_dma_end,
f37afdac
BZ
491 .dma_test_irq = ide_dma_test_irq,
492 .dma_lost_irq = ide_dma_lost_irq,
8a4a5738 493 .dma_check = ali_dma_check,
22117d6e 494 .dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315 495 .dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0
BZ
496};
497
85620436 498static const struct ide_port_info ali15x3_chipset __devinitdata = {
ced3ec8a 499 .name = DRV_NAME,
1da177e4
LT
500 .init_chipset = init_chipset_ali15x3,
501 .init_hwif = init_hwif_ali15x3,
502 .init_dma = init_dma_ali15x3,
ac95beed 503 .port_ops = &ali_port_ops,
3f023b01 504 .dma_ops = &sff_dma_ops,
4099d143 505 .pio_mask = ATA_PIO5,
5f8b6c34
BZ
506 .swdma_mask = ATA_SWDMA2,
507 .mwdma_mask = ATA_MWDMA2,
1da177e4
LT
508};
509
510/**
511 * alim15x3_init_one - set up an ALi15x3 IDE controller
512 * @dev: PCI device to set up
513 *
514 * Perform the actual set up for an ALi15x3 that has been found by the
515 * hot plug layer.
516 */
517
518static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
519{
039788e1 520 struct ide_port_info d = ali15x3_chipset;
8ac2b42a 521 u8 rev = dev->revision, idx = id->driver_data;
1da177e4 522
28328307
BZ
523 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
524 if (rev <= 0xC4)
525 d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
526
527 if (rev >= 0x20) {
528 if (rev == 0x20)
529 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
530
531 if (rev < 0xC2)
532 d.udma_mask = ATA_UDMA2;
533 else if (rev == 0xC2 || rev == 0xC3)
534 d.udma_mask = ATA_UDMA4;
535 else if (rev == 0xC4)
536 d.udma_mask = ATA_UDMA5;
537 else
538 d.udma_mask = ATA_UDMA6;
5e37bdc0
BZ
539
540 d.dma_ops = &ali_dma_ops;
6d36b95f
BZ
541 } else {
542 d.host_flags |= IDE_HFLAG_NO_DMA;
543
544 d.mwdma_mask = d.swdma_mask = 0;
28328307
BZ
545 }
546
8ac2b42a
BZ
547 if (idx == 0)
548 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
549
6cdf6eb3 550 return ide_pci_init_one(dev, &d, NULL);
1da177e4
LT
551}
552
553
9cbcc5e3
BZ
554static const struct pci_device_id alim15x3_pci_tbl[] = {
555 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
8ac2b42a 556 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
1da177e4
LT
557 { 0, },
558};
559MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
560
a9ab09e2 561static struct pci_driver alim15x3_pci_driver = {
1da177e4
LT
562 .name = "ALI15x3_IDE",
563 .id_table = alim15x3_pci_tbl,
564 .probe = alim15x3_init_one,
8ee3f3b6 565 .remove = ide_pci_remove,
feb22b7f
BZ
566 .suspend = ide_pci_suspend,
567 .resume = ide_pci_resume,
1da177e4
LT
568};
569
82ab1eec 570static int __init ali15x3_ide_init(void)
1da177e4 571{
a9ab09e2 572 return ide_pci_register_driver(&alim15x3_pci_driver);
1da177e4
LT
573}
574
8ee3f3b6
BZ
575static void __exit ali15x3_ide_exit(void)
576{
95964018 577 pci_unregister_driver(&alim15x3_pci_driver);
8ee3f3b6
BZ
578}
579
1da177e4 580module_init(ali15x3_ide_init);
8ee3f3b6 581module_exit(ali15x3_ide_exit);
1da177e4 582
3c8cc8df 583MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz");
1da177e4
LT
584MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
585MODULE_LICENSE("GPL");