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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/arm/icside.c | |
3 | * | |
4 | * Copyright (c) 1996-2004 Russell King. | |
5 | * | |
6 | * Please note that this platform does not support 32-bit IDE IO. | |
7 | */ | |
8 | ||
1da177e4 LT |
9 | #include <linux/string.h> |
10 | #include <linux/module.h> | |
11 | #include <linux/ioport.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/blkdev.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/hdreg.h> | |
16 | #include <linux/ide.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/scatterlist.h> | |
21 | ||
22 | #include <asm/dma.h> | |
23 | #include <asm/ecard.h> | |
24 | #include <asm/io.h> | |
25 | ||
26 | #define ICS_IDENT_OFFSET 0x2280 | |
27 | ||
28 | #define ICS_ARCIN_V5_INTRSTAT 0x0000 | |
29 | #define ICS_ARCIN_V5_INTROFFSET 0x0004 | |
30 | #define ICS_ARCIN_V5_IDEOFFSET 0x2800 | |
31 | #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80 | |
32 | #define ICS_ARCIN_V5_IDESTEPPING 6 | |
33 | ||
34 | #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000 | |
35 | #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 | |
36 | #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 | |
37 | #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380 | |
38 | #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000 | |
39 | #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 | |
40 | #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 | |
41 | #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380 | |
42 | #define ICS_ARCIN_V6_IDESTEPPING 6 | |
43 | ||
44 | struct cardinfo { | |
45 | unsigned int dataoffset; | |
46 | unsigned int ctrloffset; | |
47 | unsigned int stepping; | |
48 | }; | |
49 | ||
50 | static struct cardinfo icside_cardinfo_v5 = { | |
51 | .dataoffset = ICS_ARCIN_V5_IDEOFFSET, | |
52 | .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET, | |
53 | .stepping = ICS_ARCIN_V5_IDESTEPPING, | |
54 | }; | |
55 | ||
56 | static struct cardinfo icside_cardinfo_v6_1 = { | |
57 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1, | |
58 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1, | |
59 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
60 | }; | |
61 | ||
62 | static struct cardinfo icside_cardinfo_v6_2 = { | |
63 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2, | |
64 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2, | |
65 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
66 | }; | |
67 | ||
68 | struct icside_state { | |
69 | unsigned int channel; | |
70 | unsigned int enabled; | |
71 | void __iomem *irq_port; | |
72 | void __iomem *ioc_base; | |
73 | unsigned int type; | |
74 | /* parent device... until the IDE core gets one of its own */ | |
75 | struct device *dev; | |
76 | ide_hwif_t *hwif[2]; | |
77 | }; | |
78 | ||
79 | #define ICS_TYPE_A3IN 0 | |
80 | #define ICS_TYPE_A3USER 1 | |
81 | #define ICS_TYPE_V6 3 | |
82 | #define ICS_TYPE_V5 15 | |
83 | #define ICS_TYPE_NOTYPE ((unsigned int)-1) | |
84 | ||
85 | /* ---------------- Version 5 PCB Support Functions --------------------- */ | |
86 | /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
87 | * Purpose : enable interrupts from card | |
88 | */ | |
89 | static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
90 | { | |
91 | struct icside_state *state = ec->irq_data; | |
92 | ||
93 | writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
94 | } | |
95 | ||
96 | /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
97 | * Purpose : disable interrupts from card | |
98 | */ | |
99 | static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
100 | { | |
101 | struct icside_state *state = ec->irq_data; | |
102 | ||
103 | readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
104 | } | |
105 | ||
106 | static const expansioncard_ops_t icside_ops_arcin_v5 = { | |
107 | .irqenable = icside_irqenable_arcin_v5, | |
108 | .irqdisable = icside_irqdisable_arcin_v5, | |
109 | }; | |
110 | ||
111 | ||
112 | /* ---------------- Version 6 PCB Support Functions --------------------- */ | |
113 | /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
114 | * Purpose : enable interrupts from card | |
115 | */ | |
116 | static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
117 | { | |
118 | struct icside_state *state = ec->irq_data; | |
119 | void __iomem *base = state->irq_port; | |
120 | ||
121 | state->enabled = 1; | |
122 | ||
123 | switch (state->channel) { | |
124 | case 0: | |
125 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); | |
126 | readb(base + ICS_ARCIN_V6_INTROFFSET_2); | |
127 | break; | |
128 | case 1: | |
129 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); | |
130 | readb(base + ICS_ARCIN_V6_INTROFFSET_1); | |
131 | break; | |
132 | } | |
133 | } | |
134 | ||
135 | /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
136 | * Purpose : disable interrupts from card | |
137 | */ | |
138 | static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
139 | { | |
140 | struct icside_state *state = ec->irq_data; | |
141 | ||
142 | state->enabled = 0; | |
143 | ||
144 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
145 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
146 | } | |
147 | ||
148 | /* Prototype: icside_irqprobe(struct expansion_card *ec) | |
149 | * Purpose : detect an active interrupt from card | |
150 | */ | |
151 | static int icside_irqpending_arcin_v6(struct expansion_card *ec) | |
152 | { | |
153 | struct icside_state *state = ec->irq_data; | |
154 | ||
155 | return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || | |
156 | readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; | |
157 | } | |
158 | ||
159 | static const expansioncard_ops_t icside_ops_arcin_v6 = { | |
160 | .irqenable = icside_irqenable_arcin_v6, | |
161 | .irqdisable = icside_irqdisable_arcin_v6, | |
162 | .irqpending = icside_irqpending_arcin_v6, | |
163 | }; | |
164 | ||
165 | /* | |
166 | * Handle routing of interrupts. This is called before | |
167 | * we write the command to the drive. | |
168 | */ | |
169 | static void icside_maskproc(ide_drive_t *drive, int mask) | |
170 | { | |
171 | ide_hwif_t *hwif = HWIF(drive); | |
172 | struct icside_state *state = hwif->hwif_data; | |
173 | unsigned long flags; | |
174 | ||
175 | local_irq_save(flags); | |
176 | ||
177 | state->channel = hwif->channel; | |
178 | ||
179 | if (state->enabled && !mask) { | |
180 | switch (hwif->channel) { | |
181 | case 0: | |
182 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
183 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
184 | break; | |
185 | case 1: | |
186 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
187 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
188 | break; | |
189 | } | |
190 | } else { | |
191 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
192 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
193 | } | |
194 | ||
195 | local_irq_restore(flags); | |
196 | } | |
197 | ||
198 | #ifdef CONFIG_BLK_DEV_IDEDMA_ICS | |
199 | ||
200 | #ifndef CONFIG_IDEDMA_ICS_AUTO | |
201 | #warning CONFIG_IDEDMA_ICS_AUTO=n support is obsolete, and will be removed soon. | |
202 | #endif | |
203 | ||
204 | /* | |
205 | * SG-DMA support. | |
206 | * | |
207 | * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. | |
208 | * There is only one DMA controller per card, which means that only | |
209 | * one drive can be accessed at one time. NOTE! We do not enforce that | |
210 | * here, but we rely on the main IDE driver spotting that both | |
211 | * interfaces use the same IRQ, which should guarantee this. | |
212 | */ | |
213 | ||
214 | static void icside_build_sglist(ide_drive_t *drive, struct request *rq) | |
215 | { | |
216 | ide_hwif_t *hwif = drive->hwif; | |
217 | struct icside_state *state = hwif->hwif_data; | |
218 | struct scatterlist *sg = hwif->sg_table; | |
219 | ||
220 | ide_map_sg(drive, rq); | |
221 | ||
222 | if (rq_data_dir(rq) == READ) | |
223 | hwif->sg_dma_direction = DMA_FROM_DEVICE; | |
224 | else | |
225 | hwif->sg_dma_direction = DMA_TO_DEVICE; | |
226 | ||
227 | hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents, | |
228 | hwif->sg_dma_direction); | |
229 | } | |
230 | ||
231 | /* | |
232 | * Configure the IOMD to give the appropriate timings for the transfer | |
233 | * mode being requested. We take the advice of the ATA standards, and | |
234 | * calculate the cycle time based on the transfer mode, and the EIDE | |
235 | * MW DMA specs that the drive provides in the IDENTIFY command. | |
236 | * | |
237 | * We have the following IOMD DMA modes to choose from: | |
238 | * | |
239 | * Type Active Recovery Cycle | |
240 | * A 250 (250) 312 (550) 562 (800) | |
241 | * B 187 250 437 | |
242 | * C 125 (125) 125 (375) 250 (500) | |
243 | * D 62 125 187 | |
244 | * | |
245 | * (figures in brackets are actual measured timings) | |
246 | * | |
247 | * However, we also need to take care of the read/write active and | |
248 | * recovery timings: | |
249 | * | |
250 | * Read Write | |
251 | * Mode Active -- Recovery -- Cycle IOMD type | |
252 | * MW0 215 50 215 480 A | |
253 | * MW1 80 50 50 150 C | |
254 | * MW2 70 25 25 120 C | |
255 | */ | |
256 | static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode) | |
257 | { | |
258 | int on = 0, cycle_time = 0, use_dma_info = 0; | |
259 | ||
260 | /* | |
261 | * Limit the transfer speed to MW_DMA_2. | |
262 | */ | |
263 | if (xfer_mode > XFER_MW_DMA_2) | |
264 | xfer_mode = XFER_MW_DMA_2; | |
265 | ||
266 | switch (xfer_mode) { | |
267 | case XFER_MW_DMA_2: | |
268 | cycle_time = 250; | |
269 | use_dma_info = 1; | |
270 | break; | |
271 | ||
272 | case XFER_MW_DMA_1: | |
273 | cycle_time = 250; | |
274 | use_dma_info = 1; | |
275 | break; | |
276 | ||
277 | case XFER_MW_DMA_0: | |
278 | cycle_time = 480; | |
279 | break; | |
280 | ||
281 | case XFER_SW_DMA_2: | |
282 | case XFER_SW_DMA_1: | |
283 | case XFER_SW_DMA_0: | |
284 | cycle_time = 480; | |
285 | break; | |
286 | } | |
287 | ||
288 | /* | |
289 | * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should | |
290 | * take care to note the values in the ID... | |
291 | */ | |
292 | if (use_dma_info && drive->id->eide_dma_time > cycle_time) | |
293 | cycle_time = drive->id->eide_dma_time; | |
294 | ||
295 | drive->drive_data = cycle_time; | |
296 | ||
297 | if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0) | |
298 | on = 1; | |
299 | else | |
300 | drive->drive_data = 480; | |
301 | ||
302 | printk("%s: %s selected (peak %dMB/s)\n", drive->name, | |
303 | ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data); | |
304 | ||
305 | drive->current_speed = xfer_mode; | |
306 | ||
307 | return on; | |
308 | } | |
309 | ||
7469aaf6 | 310 | static void icside_dma_host_off(ide_drive_t *drive) |
1da177e4 | 311 | { |
1da177e4 LT |
312 | } |
313 | ||
7469aaf6 | 314 | static void icside_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
315 | { |
316 | drive->using_dma = 0; | |
1da177e4 LT |
317 | } |
318 | ||
319 | static int icside_dma_host_on(ide_drive_t *drive) | |
320 | { | |
321 | return 0; | |
322 | } | |
323 | ||
324 | static int icside_dma_on(ide_drive_t *drive) | |
325 | { | |
326 | drive->using_dma = 1; | |
327 | return icside_dma_host_on(drive); | |
328 | } | |
329 | ||
330 | static int icside_dma_check(ide_drive_t *drive) | |
331 | { | |
332 | struct hd_driveid *id = drive->id; | |
333 | ide_hwif_t *hwif = HWIF(drive); | |
334 | int xfer_mode = XFER_PIO_2; | |
335 | int on; | |
336 | ||
337 | if (!(id->capability & 1) || !hwif->autodma) | |
338 | goto out; | |
339 | ||
340 | /* | |
341 | * Consult the list of known "bad" drives | |
342 | */ | |
343 | if (__ide_dma_bad_drive(drive)) | |
344 | goto out; | |
345 | ||
346 | /* | |
347 | * Enable DMA on any drive that has multiword DMA | |
348 | */ | |
349 | if (id->field_valid & 2) { | |
350 | xfer_mode = ide_dma_speed(drive, 0); | |
351 | goto out; | |
352 | } | |
353 | ||
354 | /* | |
355 | * Consult the list of known "good" drives | |
356 | */ | |
357 | if (__ide_dma_good_drive(drive)) { | |
358 | if (id->eide_dma_time > 150) | |
359 | goto out; | |
360 | xfer_mode = XFER_MW_DMA_1; | |
361 | } | |
362 | ||
363 | out: | |
364 | on = icside_set_speed(drive, xfer_mode); | |
365 | ||
3608b5d7 | 366 | return on ? 0 : -1; |
1da177e4 LT |
367 | } |
368 | ||
369 | static int icside_dma_end(ide_drive_t *drive) | |
370 | { | |
371 | ide_hwif_t *hwif = HWIF(drive); | |
372 | struct icside_state *state = hwif->hwif_data; | |
373 | ||
374 | drive->waiting_for_dma = 0; | |
375 | ||
376 | disable_dma(hwif->hw.dma); | |
377 | ||
378 | /* Teardown mappings after DMA has completed. */ | |
379 | dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents, | |
380 | hwif->sg_dma_direction); | |
381 | ||
382 | return get_dma_residue(hwif->hw.dma) != 0; | |
383 | } | |
384 | ||
385 | static void icside_dma_start(ide_drive_t *drive) | |
386 | { | |
387 | ide_hwif_t *hwif = HWIF(drive); | |
388 | ||
389 | /* We can not enable DMA on both channels simultaneously. */ | |
390 | BUG_ON(dma_channel_active(hwif->hw.dma)); | |
391 | enable_dma(hwif->hw.dma); | |
392 | } | |
393 | ||
394 | static int icside_dma_setup(ide_drive_t *drive) | |
395 | { | |
396 | ide_hwif_t *hwif = HWIF(drive); | |
397 | struct request *rq = hwif->hwgroup->rq; | |
398 | unsigned int dma_mode; | |
399 | ||
400 | if (rq_data_dir(rq)) | |
401 | dma_mode = DMA_MODE_WRITE; | |
402 | else | |
403 | dma_mode = DMA_MODE_READ; | |
404 | ||
405 | /* | |
406 | * We can not enable DMA on both channels. | |
407 | */ | |
408 | BUG_ON(dma_channel_active(hwif->hw.dma)); | |
409 | ||
410 | icside_build_sglist(drive, rq); | |
411 | ||
412 | /* | |
413 | * Ensure that we have the right interrupt routed. | |
414 | */ | |
415 | icside_maskproc(drive, 0); | |
416 | ||
417 | /* | |
418 | * Route the DMA signals to the correct interface. | |
419 | */ | |
420 | writeb(hwif->select_data, hwif->config_data); | |
421 | ||
422 | /* | |
423 | * Select the correct timing for this drive. | |
424 | */ | |
425 | set_dma_speed(hwif->hw.dma, drive->drive_data); | |
426 | ||
427 | /* | |
428 | * Tell the DMA engine about the SG table and | |
429 | * data direction. | |
430 | */ | |
431 | set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents); | |
432 | set_dma_mode(hwif->hw.dma, dma_mode); | |
433 | ||
434 | drive->waiting_for_dma = 1; | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd) | |
440 | { | |
441 | /* issue cmd to drive */ | |
442 | ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL); | |
443 | } | |
444 | ||
445 | static int icside_dma_test_irq(ide_drive_t *drive) | |
446 | { | |
447 | ide_hwif_t *hwif = HWIF(drive); | |
448 | struct icside_state *state = hwif->hwif_data; | |
449 | ||
450 | return readb(state->irq_port + | |
451 | (hwif->channel ? | |
452 | ICS_ARCIN_V6_INTRSTAT_2 : | |
453 | ICS_ARCIN_V6_INTRSTAT_1)) & 1; | |
454 | } | |
455 | ||
456 | static int icside_dma_timeout(ide_drive_t *drive) | |
457 | { | |
458 | printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); | |
459 | ||
460 | if (icside_dma_test_irq(drive)) | |
461 | return 0; | |
462 | ||
463 | ide_dump_status(drive, "DMA timeout", | |
464 | HWIF(drive)->INB(IDE_STATUS_REG)); | |
465 | ||
466 | return icside_dma_end(drive); | |
467 | } | |
468 | ||
469 | static int icside_dma_lostirq(ide_drive_t *drive) | |
470 | { | |
471 | printk(KERN_ERR "%s: IRQ lost\n", drive->name); | |
472 | return 1; | |
473 | } | |
474 | ||
475 | static void icside_dma_init(ide_hwif_t *hwif) | |
476 | { | |
477 | int autodma = 0; | |
478 | ||
479 | #ifdef CONFIG_IDEDMA_ICS_AUTO | |
480 | autodma = 1; | |
481 | #endif | |
482 | ||
483 | printk(" %s: SG-DMA", hwif->name); | |
484 | ||
485 | hwif->atapi_dma = 1; | |
486 | hwif->mwdma_mask = 7; /* MW0..2 */ | |
487 | hwif->swdma_mask = 7; /* SW0..2 */ | |
488 | ||
489 | hwif->dmatable_cpu = NULL; | |
490 | hwif->dmatable_dma = 0; | |
491 | hwif->speedproc = icside_set_speed; | |
492 | hwif->autodma = autodma; | |
493 | ||
494 | hwif->ide_dma_check = icside_dma_check; | |
7469aaf6 BZ |
495 | hwif->dma_host_off = icside_dma_host_off; |
496 | hwif->dma_off_quietly = icside_dma_off_quietly; | |
1da177e4 LT |
497 | hwif->ide_dma_host_on = icside_dma_host_on; |
498 | hwif->ide_dma_on = icside_dma_on; | |
499 | hwif->dma_setup = icside_dma_setup; | |
500 | hwif->dma_exec_cmd = icside_dma_exec_cmd; | |
501 | hwif->dma_start = icside_dma_start; | |
502 | hwif->ide_dma_end = icside_dma_end; | |
503 | hwif->ide_dma_test_irq = icside_dma_test_irq; | |
504 | hwif->ide_dma_timeout = icside_dma_timeout; | |
505 | hwif->ide_dma_lostirq = icside_dma_lostirq; | |
506 | ||
507 | hwif->drives[0].autodma = hwif->autodma; | |
508 | hwif->drives[1].autodma = hwif->autodma; | |
509 | ||
510 | printk(" capable%s\n", hwif->autodma ? ", auto-enable" : ""); | |
511 | } | |
512 | #else | |
513 | #define icside_dma_init(hwif) (0) | |
514 | #endif | |
515 | ||
516 | static ide_hwif_t *icside_find_hwif(unsigned long dataport) | |
517 | { | |
518 | ide_hwif_t *hwif; | |
519 | int index; | |
520 | ||
521 | for (index = 0; index < MAX_HWIFS; ++index) { | |
522 | hwif = &ide_hwifs[index]; | |
523 | if (hwif->io_ports[IDE_DATA_OFFSET] == dataport) | |
524 | goto found; | |
525 | } | |
526 | ||
527 | for (index = 0; index < MAX_HWIFS; ++index) { | |
528 | hwif = &ide_hwifs[index]; | |
529 | if (!hwif->io_ports[IDE_DATA_OFFSET]) | |
530 | goto found; | |
531 | } | |
532 | ||
533 | hwif = NULL; | |
534 | found: | |
535 | return hwif; | |
536 | } | |
537 | ||
538 | static ide_hwif_t * | |
539 | icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec) | |
540 | { | |
541 | unsigned long port = (unsigned long)base + info->dataoffset; | |
542 | ide_hwif_t *hwif; | |
543 | ||
544 | hwif = icside_find_hwif(port); | |
545 | if (hwif) { | |
546 | int i; | |
547 | ||
548 | memset(&hwif->hw, 0, sizeof(hw_regs_t)); | |
549 | ||
550 | /* | |
551 | * Ensure we're using MMIO | |
552 | */ | |
553 | default_hwif_mmiops(hwif); | |
2ad1e558 | 554 | hwif->mmio = 1; |
1da177e4 LT |
555 | |
556 | for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { | |
557 | hwif->hw.io_ports[i] = port; | |
558 | hwif->io_ports[i] = port; | |
559 | port += 1 << info->stepping; | |
560 | } | |
561 | hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset; | |
562 | hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset; | |
563 | hwif->hw.irq = ec->irq; | |
564 | hwif->irq = ec->irq; | |
565 | hwif->noprobe = 0; | |
566 | hwif->chipset = ide_acorn; | |
567 | hwif->gendev.parent = &ec->dev; | |
568 | } | |
569 | ||
570 | return hwif; | |
571 | } | |
572 | ||
573 | static int __init | |
574 | icside_register_v5(struct icside_state *state, struct expansion_card *ec) | |
575 | { | |
576 | ide_hwif_t *hwif; | |
577 | void __iomem *base; | |
578 | ||
579 | base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), | |
580 | ecard_resource_len(ec, ECARD_RES_MEMC)); | |
581 | if (!base) | |
582 | return -ENOMEM; | |
583 | ||
584 | state->irq_port = base; | |
585 | ||
586 | ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; | |
587 | ec->irqmask = 1; | |
588 | ec->irq_data = state; | |
589 | ec->ops = &icside_ops_arcin_v5; | |
590 | ||
591 | /* | |
592 | * Be on the safe side - disable interrupts | |
593 | */ | |
594 | icside_irqdisable_arcin_v5(ec, 0); | |
595 | ||
596 | hwif = icside_setup(base, &icside_cardinfo_v5, ec); | |
597 | if (!hwif) { | |
598 | iounmap(base); | |
599 | return -ENODEV; | |
600 | } | |
601 | ||
602 | state->hwif[0] = hwif; | |
603 | ||
604 | probe_hwif_init(hwif); | |
605 | create_proc_ide_interfaces(); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int __init | |
611 | icside_register_v6(struct icside_state *state, struct expansion_card *ec) | |
612 | { | |
613 | ide_hwif_t *hwif, *mate; | |
614 | void __iomem *ioc_base, *easi_base; | |
615 | unsigned int sel = 0; | |
616 | int ret; | |
617 | ||
618 | ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), | |
619 | ecard_resource_len(ec, ECARD_RES_IOCFAST)); | |
620 | if (!ioc_base) { | |
621 | ret = -ENOMEM; | |
622 | goto out; | |
623 | } | |
624 | ||
625 | easi_base = ioc_base; | |
626 | ||
627 | if (ecard_resource_flags(ec, ECARD_RES_EASI)) { | |
628 | easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), | |
629 | ecard_resource_len(ec, ECARD_RES_EASI)); | |
630 | if (!easi_base) { | |
631 | ret = -ENOMEM; | |
632 | goto unmap_slot; | |
633 | } | |
634 | ||
635 | /* | |
636 | * Enable access to the EASI region. | |
637 | */ | |
638 | sel = 1 << 5; | |
639 | } | |
640 | ||
641 | writeb(sel, ioc_base); | |
642 | ||
643 | ec->irq_data = state; | |
644 | ec->ops = &icside_ops_arcin_v6; | |
645 | ||
646 | state->irq_port = easi_base; | |
647 | state->ioc_base = ioc_base; | |
648 | ||
649 | /* | |
650 | * Be on the safe side - disable interrupts | |
651 | */ | |
652 | icside_irqdisable_arcin_v6(ec, 0); | |
653 | ||
654 | /* | |
655 | * Find and register the interfaces. | |
656 | */ | |
657 | hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec); | |
658 | mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec); | |
659 | ||
660 | if (!hwif || !mate) { | |
661 | ret = -ENODEV; | |
662 | goto unmap_port; | |
663 | } | |
664 | ||
665 | state->hwif[0] = hwif; | |
666 | state->hwif[1] = mate; | |
667 | ||
668 | hwif->maskproc = icside_maskproc; | |
669 | hwif->channel = 0; | |
670 | hwif->hwif_data = state; | |
671 | hwif->mate = mate; | |
672 | hwif->serialized = 1; | |
673 | hwif->config_data = (unsigned long)ioc_base; | |
674 | hwif->select_data = sel; | |
675 | hwif->hw.dma = ec->dma; | |
676 | ||
677 | mate->maskproc = icside_maskproc; | |
678 | mate->channel = 1; | |
679 | mate->hwif_data = state; | |
680 | mate->mate = hwif; | |
681 | mate->serialized = 1; | |
682 | mate->config_data = (unsigned long)ioc_base; | |
683 | mate->select_data = sel | 1; | |
684 | mate->hw.dma = ec->dma; | |
685 | ||
686 | if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) { | |
687 | icside_dma_init(hwif); | |
688 | icside_dma_init(mate); | |
689 | } | |
690 | ||
691 | probe_hwif_init(hwif); | |
692 | probe_hwif_init(mate); | |
693 | create_proc_ide_interfaces(); | |
694 | ||
695 | return 0; | |
696 | ||
697 | unmap_port: | |
698 | if (easi_base != ioc_base) | |
699 | iounmap(easi_base); | |
700 | unmap_slot: | |
701 | iounmap(ioc_base); | |
702 | out: | |
703 | return ret; | |
704 | } | |
705 | ||
706 | static int __devinit | |
707 | icside_probe(struct expansion_card *ec, const struct ecard_id *id) | |
708 | { | |
709 | struct icside_state *state; | |
710 | void __iomem *idmem; | |
711 | int ret; | |
712 | ||
713 | ret = ecard_request_resources(ec); | |
714 | if (ret) | |
715 | goto out; | |
716 | ||
717 | state = kmalloc(sizeof(struct icside_state), GFP_KERNEL); | |
718 | if (!state) { | |
719 | ret = -ENOMEM; | |
720 | goto release; | |
721 | } | |
722 | ||
723 | memset(state, 0, sizeof(state)); | |
724 | state->type = ICS_TYPE_NOTYPE; | |
725 | state->dev = &ec->dev; | |
726 | ||
727 | idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), | |
728 | ecard_resource_len(ec, ECARD_RES_IOCFAST)); | |
729 | if (idmem) { | |
730 | unsigned int type; | |
731 | ||
732 | type = readb(idmem + ICS_IDENT_OFFSET) & 1; | |
733 | type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; | |
734 | type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; | |
735 | type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; | |
736 | iounmap(idmem); | |
737 | ||
738 | state->type = type; | |
739 | } | |
740 | ||
741 | switch (state->type) { | |
742 | case ICS_TYPE_A3IN: | |
743 | dev_warn(&ec->dev, "A3IN unsupported\n"); | |
744 | ret = -ENODEV; | |
745 | break; | |
746 | ||
747 | case ICS_TYPE_A3USER: | |
748 | dev_warn(&ec->dev, "A3USER unsupported\n"); | |
749 | ret = -ENODEV; | |
750 | break; | |
751 | ||
752 | case ICS_TYPE_V5: | |
753 | ret = icside_register_v5(state, ec); | |
754 | break; | |
755 | ||
756 | case ICS_TYPE_V6: | |
757 | ret = icside_register_v6(state, ec); | |
758 | break; | |
759 | ||
760 | default: | |
761 | dev_warn(&ec->dev, "unknown interface type\n"); | |
762 | ret = -ENODEV; | |
763 | break; | |
764 | } | |
765 | ||
766 | if (ret == 0) { | |
767 | ecard_set_drvdata(ec, state); | |
768 | goto out; | |
769 | } | |
770 | ||
771 | kfree(state); | |
772 | release: | |
773 | ecard_release_resources(ec); | |
774 | out: | |
775 | return ret; | |
776 | } | |
777 | ||
778 | static void __devexit icside_remove(struct expansion_card *ec) | |
779 | { | |
780 | struct icside_state *state = ecard_get_drvdata(ec); | |
781 | ||
782 | switch (state->type) { | |
783 | case ICS_TYPE_V5: | |
784 | /* FIXME: tell IDE to stop using the interface */ | |
785 | ||
786 | /* Disable interrupts */ | |
787 | icside_irqdisable_arcin_v5(ec, 0); | |
788 | break; | |
789 | ||
790 | case ICS_TYPE_V6: | |
791 | /* FIXME: tell IDE to stop using the interface */ | |
792 | if (ec->dma != NO_DMA) | |
793 | free_dma(ec->dma); | |
794 | ||
795 | /* Disable interrupts */ | |
796 | icside_irqdisable_arcin_v6(ec, 0); | |
797 | ||
798 | /* Reset the ROM pointer/EASI selection */ | |
799 | writeb(0, state->ioc_base); | |
800 | break; | |
801 | } | |
802 | ||
803 | ecard_set_drvdata(ec, NULL); | |
804 | ec->ops = NULL; | |
805 | ec->irq_data = NULL; | |
806 | ||
807 | if (state->ioc_base) | |
808 | iounmap(state->ioc_base); | |
809 | if (state->ioc_base != state->irq_port) | |
810 | iounmap(state->irq_port); | |
811 | ||
812 | kfree(state); | |
813 | ecard_release_resources(ec); | |
814 | } | |
815 | ||
816 | static void icside_shutdown(struct expansion_card *ec) | |
817 | { | |
818 | struct icside_state *state = ecard_get_drvdata(ec); | |
819 | unsigned long flags; | |
820 | ||
821 | /* | |
822 | * Disable interrupts from this card. We need to do | |
823 | * this before disabling EASI since we may be accessing | |
824 | * this register via that region. | |
825 | */ | |
826 | local_irq_save(flags); | |
827 | ec->ops->irqdisable(ec, 0); | |
828 | local_irq_restore(flags); | |
829 | ||
830 | /* | |
831 | * Reset the ROM pointer so that we can read the ROM | |
832 | * after a soft reboot. This also disables access to | |
833 | * the IDE taskfile via the EASI region. | |
834 | */ | |
835 | if (state->ioc_base) | |
836 | writeb(0, state->ioc_base); | |
837 | } | |
838 | ||
839 | static const struct ecard_id icside_ids[] = { | |
840 | { MANU_ICS, PROD_ICS_IDE }, | |
841 | { MANU_ICS2, PROD_ICS2_IDE }, | |
842 | { 0xffff, 0xffff } | |
843 | }; | |
844 | ||
845 | static struct ecard_driver icside_driver = { | |
846 | .probe = icside_probe, | |
847 | .remove = __devexit_p(icside_remove), | |
848 | .shutdown = icside_shutdown, | |
849 | .id_table = icside_ids, | |
850 | .drv = { | |
851 | .name = "icside", | |
852 | }, | |
853 | }; | |
854 | ||
855 | static int __init icside_init(void) | |
856 | { | |
857 | return ecard_register_driver(&icside_driver); | |
858 | } | |
859 | ||
860 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
861 | MODULE_LICENSE("GPL"); | |
862 | MODULE_DESCRIPTION("ICS IDE driver"); | |
863 | ||
864 | module_init(icside_init); |