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7c7e92a9 AS |
1 | /* |
2 | * Palmchip bk3710 IDE controller | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com> | |
6 | * | |
7 | * ---------------------------------------------------------------------------- | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | * ---------------------------------------------------------------------------- | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <linux/types.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/hdreg.h> | |
31 | #include <linux/ide.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/clk.h> | |
35 | #include <linux/platform_device.h> | |
36 | ||
37 | /* Offset of the primary interface registers */ | |
38 | #define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0 | |
39 | ||
40 | /* Primary Control Offset */ | |
41 | #define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6 | |
42 | ||
43 | /* | |
44 | * PalmChip 3710 IDE Controller UDMA timing structure Definition | |
45 | */ | |
46 | struct palm_bk3710_udmatiming { | |
47 | unsigned int rptime; /* Ready to pause time */ | |
48 | unsigned int cycletime; /* Cycle Time */ | |
49 | }; | |
50 | ||
51 | #define BK3710_BMICP 0x00 | |
52 | #define BK3710_BMISP 0x02 | |
53 | #define BK3710_BMIDTP 0x04 | |
54 | #define BK3710_BMICS 0x08 | |
55 | #define BK3710_BMISS 0x0A | |
56 | #define BK3710_BMIDTS 0x0C | |
57 | #define BK3710_IDETIMP 0x40 | |
58 | #define BK3710_IDETIMS 0x42 | |
59 | #define BK3710_SIDETIM 0x44 | |
60 | #define BK3710_SLEWCTL 0x45 | |
61 | #define BK3710_IDESTATUS 0x47 | |
62 | #define BK3710_UDMACTL 0x48 | |
63 | #define BK3710_UDMATIM 0x4A | |
64 | #define BK3710_MISCCTL 0x50 | |
65 | #define BK3710_REGSTB 0x54 | |
66 | #define BK3710_REGRCVR 0x58 | |
67 | #define BK3710_DATSTB 0x5C | |
68 | #define BK3710_DATRCVR 0x60 | |
69 | #define BK3710_DMASTB 0x64 | |
70 | #define BK3710_DMARCVR 0x68 | |
71 | #define BK3710_UDMASTB 0x6C | |
72 | #define BK3710_UDMATRP 0x70 | |
73 | #define BK3710_UDMAENV 0x74 | |
74 | #define BK3710_IORDYTMP 0x78 | |
75 | #define BK3710_IORDYTMS 0x7C | |
76 | ||
ffab6cf4 | 77 | static unsigned ideclk_period; /* in nanoseconds */ |
7c7e92a9 AS |
78 | |
79 | static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = { | |
80 | {160, 240}, /* UDMA Mode 0 */ | |
81 | {125, 160}, /* UDMA Mode 1 */ | |
82 | {100, 120}, /* UDMA Mode 2 */ | |
83 | {100, 90}, /* UDMA Mode 3 */ | |
8c6e46dd | 84 | {100, 60}, /* UDMA Mode 4 */ |
a0f403bc | 85 | {85, 40}, /* UDMA Mode 5 */ |
7c7e92a9 AS |
86 | }; |
87 | ||
7c7e92a9 AS |
88 | static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, |
89 | unsigned int mode) | |
90 | { | |
91 | u8 tenv, trp, t0; | |
92 | u32 val32; | |
93 | u16 val16; | |
94 | ||
95 | /* DMA Data Setup */ | |
00fe8b7a | 96 | t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime, |
ffab6cf4 SS |
97 | ideclk_period) - 1; |
98 | tenv = DIV_ROUND_UP(20, ideclk_period) - 1; | |
00fe8b7a | 99 | trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime, |
ffab6cf4 | 100 | ideclk_period) - 1; |
7c7e92a9 AS |
101 | |
102 | /* udmatim Register */ | |
103 | val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0); | |
104 | val16 |= (mode << (dev ? 4 : 0)); | |
105 | writew(val16, base + BK3710_UDMATIM); | |
106 | ||
107 | /* udmastb Ultra DMA Access Strobe Width */ | |
108 | val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); | |
109 | val32 |= (t0 << (dev ? 8 : 0)); | |
110 | writel(val32, base + BK3710_UDMASTB); | |
111 | ||
112 | /* udmatrp Ultra DMA Ready to Pause Time */ | |
113 | val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); | |
114 | val32 |= (trp << (dev ? 8 : 0)); | |
115 | writel(val32, base + BK3710_UDMATRP); | |
116 | ||
117 | /* udmaenv Ultra DMA envelop Time */ | |
118 | val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); | |
119 | val32 |= (tenv << (dev ? 8 : 0)); | |
120 | writel(val32, base + BK3710_UDMAENV); | |
121 | ||
122 | /* Enable UDMA for Device */ | |
123 | val16 = readw(base + BK3710_UDMACTL) | (1 << dev); | |
124 | writew(val16, base + BK3710_UDMACTL); | |
125 | } | |
126 | ||
127 | static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev, | |
128 | unsigned short min_cycle, | |
129 | unsigned int mode) | |
130 | { | |
131 | u8 td, tkw, t0; | |
132 | u32 val32; | |
133 | u16 val16; | |
134 | struct ide_timing *t; | |
135 | int cycletime; | |
136 | ||
137 | t = ide_timing_find_mode(mode); | |
138 | cycletime = max_t(int, t->cycle, min_cycle); | |
139 | ||
140 | /* DMA Data Setup */ | |
ffab6cf4 SS |
141 | t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
142 | td = DIV_ROUND_UP(t->active, ideclk_period); | |
7c7e92a9 AS |
143 | tkw = t0 - td - 1; |
144 | td -= 1; | |
145 | ||
146 | val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); | |
147 | val32 |= (td << (dev ? 8 : 0)); | |
148 | writel(val32, base + BK3710_DMASTB); | |
149 | ||
150 | val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); | |
151 | val32 |= (tkw << (dev ? 8 : 0)); | |
152 | writel(val32, base + BK3710_DMARCVR); | |
153 | ||
154 | /* Disable UDMA for Device */ | |
155 | val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev); | |
156 | writew(val16, base + BK3710_UDMACTL); | |
157 | } | |
158 | ||
159 | static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, | |
160 | unsigned int dev, unsigned int cycletime, | |
161 | unsigned int mode) | |
162 | { | |
163 | u8 t2, t2i, t0; | |
164 | u32 val32; | |
165 | struct ide_timing *t; | |
166 | ||
167 | /* PIO Data Setup */ | |
ffab6cf4 | 168 | t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
00fe8b7a | 169 | t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active, |
ffab6cf4 | 170 | ideclk_period); |
7c7e92a9 AS |
171 | |
172 | t2i = t0 - t2 - 1; | |
173 | t2 -= 1; | |
174 | ||
175 | val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); | |
176 | val32 |= (t2 << (dev ? 8 : 0)); | |
177 | writel(val32, base + BK3710_DATSTB); | |
178 | ||
179 | val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); | |
180 | val32 |= (t2i << (dev ? 8 : 0)); | |
181 | writel(val32, base + BK3710_DATRCVR); | |
182 | ||
183 | if (mate && mate->present) { | |
184 | u8 mode2 = ide_get_best_pio_mode(mate, 255, 4); | |
185 | ||
186 | if (mode2 < mode) | |
187 | mode = mode2; | |
188 | } | |
189 | ||
190 | /* TASKFILE Setup */ | |
191 | t = ide_timing_find_mode(XFER_PIO_0 + mode); | |
ffab6cf4 SS |
192 | t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period); |
193 | t2 = DIV_ROUND_UP(t->act8b, ideclk_period); | |
7c7e92a9 AS |
194 | |
195 | t2i = t0 - t2 - 1; | |
196 | t2 -= 1; | |
197 | ||
198 | val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); | |
199 | val32 |= (t2 << (dev ? 8 : 0)); | |
200 | writel(val32, base + BK3710_REGSTB); | |
201 | ||
202 | val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); | |
203 | val32 |= (t2i << (dev ? 8 : 0)); | |
204 | writel(val32, base + BK3710_REGRCVR); | |
205 | } | |
206 | ||
207 | static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed) | |
208 | { | |
209 | int is_slave = drive->dn & 1; | |
210 | void __iomem *base = (void *)drive->hwif->dma_base; | |
211 | ||
212 | if (xferspeed >= XFER_UDMA_0) { | |
213 | palm_bk3710_setudmamode(base, is_slave, | |
214 | xferspeed - XFER_UDMA_0); | |
215 | } else { | |
216 | palm_bk3710_setdmamode(base, is_slave, drive->id->eide_dma_min, | |
217 | xferspeed); | |
218 | } | |
219 | } | |
220 | ||
221 | static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio) | |
222 | { | |
223 | unsigned int cycle_time; | |
224 | int is_slave = drive->dn & 1; | |
225 | ide_drive_t *mate; | |
226 | void __iomem *base = (void *)drive->hwif->dma_base; | |
227 | ||
228 | /* | |
229 | * Obtain the drive PIO data for tuning the Palm Chip registers | |
230 | */ | |
231 | cycle_time = ide_pio_cycle_time(drive, pio); | |
232 | mate = ide_get_paired_drive(drive); | |
233 | palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio); | |
234 | } | |
235 | ||
236 | static void __devinit palm_bk3710_chipinit(void __iomem *base) | |
237 | { | |
238 | /* | |
239 | * enable the reset_en of ATA controller so that when ata signals | |
240 | * are brought out, by writing into device config. at that | |
241 | * time por_n signal should not be 'Z' and have a stable value. | |
242 | */ | |
243 | writel(0x0300, base + BK3710_MISCCTL); | |
244 | ||
245 | /* wait for some time and deassert the reset of ATA Device. */ | |
246 | mdelay(100); | |
247 | ||
248 | /* Deassert the Reset */ | |
249 | writel(0x0200, base + BK3710_MISCCTL); | |
250 | ||
251 | /* | |
252 | * Program the IDETIMP Register Value based on the following assumptions | |
253 | * | |
254 | * (ATA_IDETIMP_IDEEN , ENABLE ) | | |
255 | * (ATA_IDETIMP_SLVTIMEN , DISABLE) | | |
256 | * (ATA_IDETIMP_RDYSMPL , 70NS) | | |
257 | * (ATA_IDETIMP_RDYRCVRY , 50NS) | | |
258 | * (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) | | |
259 | * (ATA_IDETIMP_PREPOST1 , DISABLE) | | |
260 | * (ATA_IDETIMP_RDYSEN1 , DISABLE) | | |
261 | * (ATA_IDETIMP_PIOFTIM1 , DISABLE) | | |
262 | * (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) | | |
263 | * (ATA_IDETIMP_PREPOST0 , DISABLE) | | |
264 | * (ATA_IDETIMP_RDYSEN0 , DISABLE) | | |
265 | * (ATA_IDETIMP_PIOFTIM0 , DISABLE) | |
266 | */ | |
267 | writew(0xB388, base + BK3710_IDETIMP); | |
268 | ||
269 | /* | |
270 | * Configure SIDETIM Register | |
271 | * (ATA_SIDETIM_RDYSMPS1 ,120NS ) | | |
272 | * (ATA_SIDETIM_RDYRCYS1 ,120NS ) | |
273 | */ | |
274 | writeb(0, base + BK3710_SIDETIM); | |
275 | ||
276 | /* | |
277 | * UDMACTL Ultra-ATA DMA Control | |
278 | * (ATA_UDMACTL_UDMAP1 , 0 ) | | |
279 | * (ATA_UDMACTL_UDMAP0 , 0 ) | |
280 | * | |
281 | */ | |
282 | writew(0, base + BK3710_UDMACTL); | |
283 | ||
284 | /* | |
285 | * MISCCTL Miscellaneous Conrol Register | |
286 | * (ATA_MISCCTL_RSTMODEP , 1) | | |
287 | * (ATA_MISCCTL_RESETP , 0) | | |
288 | * (ATA_MISCCTL_TIMORIDE , 1) | |
289 | */ | |
290 | writel(0x201, base + BK3710_MISCCTL); | |
291 | ||
292 | /* | |
293 | * IORDYTMP IORDY Timer for Primary Register | |
294 | * (ATA_IORDYTMP_IORDYTMP , 0xffff ) | |
295 | */ | |
296 | writel(0xFFFF, base + BK3710_IORDYTMP); | |
297 | ||
298 | /* | |
299 | * Configure BMISP Register | |
300 | * (ATA_BMISP_DMAEN1 , DISABLE ) | | |
301 | * (ATA_BMISP_DMAEN0 , DISABLE ) | | |
302 | * (ATA_BMISP_IORDYINT , CLEAR) | | |
303 | * (ATA_BMISP_INTRSTAT , CLEAR) | | |
304 | * (ATA_BMISP_DMAERROR , CLEAR) | |
305 | */ | |
306 | writew(0, base + BK3710_BMISP); | |
307 | ||
308 | palm_bk3710_setpiomode(base, NULL, 0, 600, 0); | |
309 | palm_bk3710_setpiomode(base, NULL, 1, 600, 0); | |
310 | } | |
c79b60dd | 311 | |
f454cbe8 | 312 | static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif) |
c79b60dd BZ |
313 | { |
314 | return ATA_CBL_PATA80; | |
315 | } | |
316 | ||
b552a2c1 BZ |
317 | static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif, |
318 | const struct ide_port_info *d) | |
319 | { | |
b552a2c1 BZ |
320 | printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); |
321 | ||
322 | if (ide_allocate_dma_engine(hwif)) | |
323 | return -1; | |
324 | ||
81e8d5a3 BZ |
325 | hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET; |
326 | ||
327 | hwif->dma_ops = &sff_dma_ops; | |
b552a2c1 BZ |
328 | |
329 | return 0; | |
330 | } | |
331 | ||
ac95beed BZ |
332 | static const struct ide_port_ops palm_bk3710_ports_ops = { |
333 | .set_pio_mode = palm_bk3710_set_pio_mode, | |
334 | .set_dma_mode = palm_bk3710_set_dma_mode, | |
335 | .cable_detect = palm_bk3710_cable_detect, | |
336 | }; | |
c79b60dd | 337 | |
a0f403bc | 338 | static struct ide_port_info __devinitdata palm_bk3710_port_info = { |
b552a2c1 | 339 | .init_dma = palm_bk3710_init_dma, |
ac95beed | 340 | .port_ops = &palm_bk3710_ports_ops, |
c5dd43ec | 341 | .host_flags = IDE_HFLAG_MMIO, |
c79b60dd | 342 | .pio_mask = ATA_PIO4, |
c79b60dd BZ |
343 | .mwdma_mask = ATA_MWDMA2, |
344 | }; | |
345 | ||
7c7e92a9 AS |
346 | static int __devinit palm_bk3710_probe(struct platform_device *pdev) |
347 | { | |
ffab6cf4 | 348 | struct clk *clk; |
7c7e92a9 | 349 | struct resource *mem, *irq; |
ffab6cf4 | 350 | unsigned long base, rate; |
6f904d01 | 351 | int i, rc; |
c97c6aca | 352 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
7c7e92a9 | 353 | |
a0f403bc | 354 | clk = clk_get(&pdev->dev, "IDECLK"); |
ffab6cf4 | 355 | if (IS_ERR(clk)) |
7c7e92a9 AS |
356 | return -ENODEV; |
357 | ||
ffab6cf4 SS |
358 | clk_enable(clk); |
359 | rate = clk_get_rate(clk); | |
360 | ideclk_period = 1000000000UL / rate; | |
361 | ||
7c7e92a9 | 362 | /* Register the IDE interface with Linux ATA Interface */ |
7824bc6b | 363 | memset(&hw, 0, sizeof(hw)); |
7c7e92a9 AS |
364 | |
365 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
366 | if (mem == NULL) { | |
367 | printk(KERN_ERR "failed to get memory region resource\n"); | |
368 | return -ENODEV; | |
369 | } | |
ce42a549 | 370 | |
7c7e92a9 AS |
371 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
372 | if (irq == NULL) { | |
373 | printk(KERN_ERR "failed to get IRQ resource\n"); | |
374 | return -ENODEV; | |
375 | } | |
376 | ||
ce42a549 SS |
377 | if (request_mem_region(mem->start, mem->end - mem->start + 1, |
378 | "palm_bk3710") == NULL) { | |
379 | printk(KERN_ERR "failed to request memory region\n"); | |
380 | return -EBUSY; | |
381 | } | |
382 | ||
383 | base = IO_ADDRESS(mem->start); | |
7c7e92a9 AS |
384 | |
385 | /* Configure the Palm Chip controller */ | |
ce42a549 | 386 | palm_bk3710_chipinit((void __iomem *)base); |
7c7e92a9 | 387 | |
7824bc6b | 388 | for (i = 0; i < IDE_NR_PORTS - 2; i++) |
ce42a549 SS |
389 | hw.io_ports_array[i] = base + IDE_PALM_ATA_PRI_REG_OFFSET + i; |
390 | hw.io_ports.ctl_addr = base + IDE_PALM_ATA_PRI_CTL_OFFSET; | |
7824bc6b BZ |
391 | hw.irq = irq->start; |
392 | hw.chipset = ide_palm3710; | |
7c7e92a9 | 393 | |
a0f403bc SS |
394 | palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 : |
395 | ATA_UDMA5; | |
396 | ||
6f904d01 BZ |
397 | rc = ide_host_add(&palm_bk3710_port_info, hws, NULL); |
398 | if (rc) | |
7824bc6b BZ |
399 | goto out; |
400 | ||
7c7e92a9 | 401 | return 0; |
7824bc6b BZ |
402 | out: |
403 | printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n"); | |
6f904d01 | 404 | return rc; |
7c7e92a9 AS |
405 | } |
406 | ||
458622fc KS |
407 | /* work with hotplug and coldplug */ |
408 | MODULE_ALIAS("platform:palm_bk3710"); | |
409 | ||
7c7e92a9 AS |
410 | static struct platform_driver platform_bk_driver = { |
411 | .driver = { | |
412 | .name = "palm_bk3710", | |
458622fc | 413 | .owner = THIS_MODULE, |
7c7e92a9 AS |
414 | }, |
415 | .probe = palm_bk3710_probe, | |
416 | .remove = NULL, | |
417 | }; | |
418 | ||
419 | static int __init palm_bk3710_init(void) | |
420 | { | |
421 | return platform_driver_register(&platform_bk_driver); | |
422 | } | |
423 | ||
424 | module_init(palm_bk3710_init); | |
425 | MODULE_LICENSE("GPL"); |