]>
Commit | Line | Data |
---|---|---|
26a940e2 | 1 | /* |
26a940e2 PP |
2 | * BRIEF MODULE DESCRIPTION |
3 | * AMD Alchemy Au1xxx IDE interface routines over the Static Bus | |
4 | * | |
5 | * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it under | |
8 | * the terms of the GNU General Public License as published by the Free Software | |
9 | * Foundation; either version 2 of the License, or (at your option) any later | |
10 | * version. | |
11 | * | |
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
13 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND | |
14 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
15 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
16 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
17 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
18 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
19 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
20 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
21 | * POSSIBILITY OF SUCH DAMAGE. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License along with | |
24 | * this program; if not, write to the Free Software Foundation, Inc., | |
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE | |
28 | * Interface and Linux Device Driver" Application Note. | |
29 | */ | |
26a940e2 PP |
30 | #include <linux/types.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/delay.h> | |
8f29e650 | 34 | #include <linux/platform_device.h> |
26a940e2 PP |
35 | #include <linux/init.h> |
36 | #include <linux/ide.h> | |
fabd3a22 | 37 | #include <linux/scatterlist.h> |
26a940e2 | 38 | |
26a940e2 PP |
39 | #include <asm/mach-au1x00/au1xxx.h> |
40 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
26a940e2 PP |
41 | #include <asm/mach-au1x00/au1xxx_ide.h> |
42 | ||
43 | #define DRV_NAME "au1200-ide" | |
8f29e650 | 44 | #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" |
26a940e2 | 45 | |
8f29e650 JC |
46 | /* enable the burstmode in the dbdma */ |
47 | #define IDE_AU1XXX_BURSTMODE 1 | |
26a940e2 | 48 | |
8f29e650 | 49 | static _auide_hwif auide_hwif; |
26a940e2 | 50 | |
26a940e2 PP |
51 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
52 | ||
8f29e650 | 53 | void auide_insw(unsigned long port, void *addr, u32 count) |
26a940e2 | 54 | { |
8f29e650 JC |
55 | _auide_hwif *ahwif = &auide_hwif; |
56 | chan_tab_t *ctp; | |
57 | au1x_ddma_desc_t *dp; | |
26a940e2 | 58 | |
8f29e650 JC |
59 | if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, |
60 | DDMA_FLAGS_NOIE)) { | |
eb63963a | 61 | printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); |
8f29e650 JC |
62 | return; |
63 | } | |
64 | ctp = *((chan_tab_t **)ahwif->rx_chan); | |
65 | dp = ctp->cur_ptr; | |
66 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
67 | ; | |
68 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
69 | } |
70 | ||
8f29e650 | 71 | void auide_outsw(unsigned long port, void *addr, u32 count) |
26a940e2 | 72 | { |
8f29e650 JC |
73 | _auide_hwif *ahwif = &auide_hwif; |
74 | chan_tab_t *ctp; | |
75 | au1x_ddma_desc_t *dp; | |
26a940e2 | 76 | |
8f29e650 JC |
77 | if(!put_source_flags(ahwif->tx_chan, (void*)addr, |
78 | count << 1, DDMA_FLAGS_NOIE)) { | |
eb63963a | 79 | printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); |
8f29e650 JC |
80 | return; |
81 | } | |
82 | ctp = *((chan_tab_t **)ahwif->tx_chan); | |
83 | dp = ctp->cur_ptr; | |
84 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
85 | ; | |
86 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
87 | } |
88 | ||
70f91e0d BZ |
89 | static void au1xxx_input_data(ide_drive_t *drive, struct request *rq, |
90 | void *buf, unsigned int len) | |
91 | { | |
92 | auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2); | |
93 | } | |
94 | ||
95 | static void au1xxx_output_data(ide_drive_t *drive, struct request *rq, | |
96 | void *buf, unsigned int len) | |
97 | { | |
98 | auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2); | |
99 | } | |
26a940e2 | 100 | #endif |
26a940e2 | 101 | |
26bcb879 | 102 | static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
26a940e2 | 103 | { |
88b2b32b | 104 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
8f29e650 JC |
105 | |
106 | /* set pio mode! */ | |
107 | switch(pio) { | |
108 | case 0: | |
109 | mem_sttime = SBC_IDE_TIMING(PIO0); | |
110 | ||
111 | /* set configuration for RCS2# */ | |
112 | mem_stcfg |= TS_MASK; | |
113 | mem_stcfg &= ~TCSOE_MASK; | |
114 | mem_stcfg &= ~TOECS_MASK; | |
115 | mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; | |
116 | break; | |
117 | ||
118 | case 1: | |
119 | mem_sttime = SBC_IDE_TIMING(PIO1); | |
120 | ||
121 | /* set configuration for RCS2# */ | |
122 | mem_stcfg |= TS_MASK; | |
123 | mem_stcfg &= ~TCSOE_MASK; | |
124 | mem_stcfg &= ~TOECS_MASK; | |
125 | mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; | |
126 | break; | |
127 | ||
128 | case 2: | |
129 | mem_sttime = SBC_IDE_TIMING(PIO2); | |
130 | ||
131 | /* set configuration for RCS2# */ | |
132 | mem_stcfg &= ~TS_MASK; | |
133 | mem_stcfg &= ~TCSOE_MASK; | |
134 | mem_stcfg &= ~TOECS_MASK; | |
135 | mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; | |
136 | break; | |
137 | ||
138 | case 3: | |
139 | mem_sttime = SBC_IDE_TIMING(PIO3); | |
140 | ||
141 | /* set configuration for RCS2# */ | |
142 | mem_stcfg &= ~TS_MASK; | |
143 | mem_stcfg &= ~TCSOE_MASK; | |
144 | mem_stcfg &= ~TOECS_MASK; | |
145 | mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; | |
146 | ||
147 | break; | |
148 | ||
149 | case 4: | |
150 | mem_sttime = SBC_IDE_TIMING(PIO4); | |
151 | ||
152 | /* set configuration for RCS2# */ | |
153 | mem_stcfg &= ~TS_MASK; | |
154 | mem_stcfg &= ~TCSOE_MASK; | |
155 | mem_stcfg &= ~TOECS_MASK; | |
156 | mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; | |
157 | break; | |
158 | } | |
159 | ||
160 | au_writel(mem_sttime,MEM_STTIME2); | |
161 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
162 | } |
163 | ||
88b2b32b | 164 | static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
26a940e2 | 165 | { |
88b2b32b | 166 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
26a940e2 | 167 | |
8f29e650 | 168 | switch(speed) { |
26a940e2 | 169 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
170 | case XFER_MW_DMA_2: |
171 | mem_sttime = SBC_IDE_TIMING(MDMA2); | |
172 | ||
173 | /* set configuration for RCS2# */ | |
174 | mem_stcfg &= ~TS_MASK; | |
175 | mem_stcfg &= ~TCSOE_MASK; | |
176 | mem_stcfg &= ~TOECS_MASK; | |
177 | mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; | |
178 | ||
8f29e650 JC |
179 | break; |
180 | case XFER_MW_DMA_1: | |
181 | mem_sttime = SBC_IDE_TIMING(MDMA1); | |
182 | ||
183 | /* set configuration for RCS2# */ | |
184 | mem_stcfg &= ~TS_MASK; | |
185 | mem_stcfg &= ~TCSOE_MASK; | |
186 | mem_stcfg &= ~TOECS_MASK; | |
187 | mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; | |
188 | ||
8f29e650 JC |
189 | break; |
190 | case XFER_MW_DMA_0: | |
191 | mem_sttime = SBC_IDE_TIMING(MDMA0); | |
192 | ||
193 | /* set configuration for RCS2# */ | |
194 | mem_stcfg |= TS_MASK; | |
195 | mem_stcfg &= ~TCSOE_MASK; | |
196 | mem_stcfg &= ~TOECS_MASK; | |
197 | mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; | |
198 | ||
8f29e650 | 199 | break; |
26a940e2 | 200 | #endif |
8f29e650 | 201 | } |
a523a175 | 202 | |
8f29e650 JC |
203 | au_writel(mem_sttime,MEM_STTIME2); |
204 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
205 | } |
206 | ||
207 | /* | |
208 | * Multi-Word DMA + DbDMA functions | |
209 | */ | |
26a940e2 | 210 | |
8f29e650 | 211 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
26a940e2 PP |
212 | static int auide_build_dmatable(ide_drive_t *drive) |
213 | { | |
8f29e650 JC |
214 | int i, iswrite, count = 0; |
215 | ide_hwif_t *hwif = HWIF(drive); | |
b65fac32 | 216 | struct request *rq = hwif->rq; |
a536f326 | 217 | _auide_hwif *ahwif = &auide_hwif; |
8f29e650 JC |
218 | struct scatterlist *sg; |
219 | ||
220 | iswrite = (rq_data_dir(rq) == WRITE); | |
221 | /* Save for interrupt context */ | |
222 | ahwif->drive = drive; | |
223 | ||
062f9f02 | 224 | hwif->sg_nents = i = ide_build_sglist(drive, rq); |
8f29e650 JC |
225 | |
226 | if (!i) | |
227 | return 0; | |
228 | ||
229 | /* fill the descriptors */ | |
230 | sg = hwif->sg_table; | |
231 | while (i && sg_dma_len(sg)) { | |
232 | u32 cur_addr; | |
233 | u32 cur_len; | |
234 | ||
235 | cur_addr = sg_dma_address(sg); | |
236 | cur_len = sg_dma_len(sg); | |
237 | ||
238 | while (cur_len) { | |
239 | u32 flags = DDMA_FLAGS_NOIE; | |
240 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
241 | ||
242 | if (++count >= PRD_ENTRIES) { | |
243 | printk(KERN_WARNING "%s: DMA table too small\n", | |
244 | drive->name); | |
245 | goto use_pio_instead; | |
246 | } | |
247 | ||
248 | /* Lets enable intr for the last descriptor only */ | |
249 | if (1==i) | |
250 | flags = DDMA_FLAGS_IE; | |
251 | else | |
252 | flags = DDMA_FLAGS_NOIE; | |
253 | ||
254 | if (iswrite) { | |
255 | if(!put_source_flags(ahwif->tx_chan, | |
45711f1a | 256 | (void*) sg_virt(sg), |
8f29e650 JC |
257 | tc, flags)) { |
258 | printk(KERN_ERR "%s failed %d\n", | |
eb63963a | 259 | __func__, __LINE__); |
26a940e2 | 260 | } |
8f29e650 | 261 | } else |
26a940e2 | 262 | { |
8f29e650 | 263 | if(!put_dest_flags(ahwif->rx_chan, |
45711f1a | 264 | (void*) sg_virt(sg), |
8f29e650 JC |
265 | tc, flags)) { |
266 | printk(KERN_ERR "%s failed %d\n", | |
eb63963a | 267 | __func__, __LINE__); |
26a940e2 | 268 | } |
8f29e650 | 269 | } |
26a940e2 | 270 | |
8f29e650 JC |
271 | cur_addr += tc; |
272 | cur_len -= tc; | |
273 | } | |
55c16a70 | 274 | sg = sg_next(sg); |
8f29e650 JC |
275 | i--; |
276 | } | |
26a940e2 | 277 | |
8f29e650 JC |
278 | if (count) |
279 | return 1; | |
26a940e2 | 280 | |
8f29e650 | 281 | use_pio_instead: |
062f9f02 | 282 | ide_destroy_dmatable(drive); |
26a940e2 | 283 | |
8f29e650 | 284 | return 0; /* revert to PIO for this request */ |
26a940e2 PP |
285 | } |
286 | ||
287 | static int auide_dma_end(ide_drive_t *drive) | |
288 | { | |
8f29e650 | 289 | ide_hwif_t *hwif = HWIF(drive); |
26a940e2 | 290 | |
8f29e650 | 291 | if (hwif->sg_nents) { |
062f9f02 | 292 | ide_destroy_dmatable(drive); |
8f29e650 JC |
293 | hwif->sg_nents = 0; |
294 | } | |
26a940e2 | 295 | |
8f29e650 | 296 | return 0; |
26a940e2 PP |
297 | } |
298 | ||
299 | static void auide_dma_start(ide_drive_t *drive ) | |
300 | { | |
26a940e2 PP |
301 | } |
302 | ||
26a940e2 PP |
303 | |
304 | static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
305 | { | |
8f29e650 JC |
306 | /* issue cmd to drive */ |
307 | ide_execute_command(drive, command, &ide_dma_intr, | |
308 | (2*WAIT_CMD), NULL); | |
26a940e2 PP |
309 | } |
310 | ||
311 | static int auide_dma_setup(ide_drive_t *drive) | |
b65fac32 BZ |
312 | { |
313 | struct request *rq = drive->hwif->rq; | |
26a940e2 | 314 | |
8f29e650 JC |
315 | if (!auide_build_dmatable(drive)) { |
316 | ide_map_sg(drive, rq); | |
317 | return 1; | |
318 | } | |
26a940e2 | 319 | |
8f29e650 JC |
320 | drive->waiting_for_dma = 1; |
321 | return 0; | |
26a940e2 PP |
322 | } |
323 | ||
26a940e2 | 324 | static int auide_dma_test_irq(ide_drive_t *drive) |
c67c216d | 325 | { |
8f29e650 JC |
326 | /* If dbdma didn't execute the STOP command yet, the |
327 | * active bit is still set | |
26a940e2 | 328 | */ |
8f29e650 JC |
329 | drive->waiting_for_dma++; |
330 | if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { | |
331 | printk(KERN_WARNING "%s: timeout waiting for ddma to \ | |
26a940e2 | 332 | complete\n", drive->name); |
8f29e650 JC |
333 | return 1; |
334 | } | |
335 | udelay(10); | |
336 | return 0; | |
26a940e2 PP |
337 | } |
338 | ||
15ce926a | 339 | static void auide_dma_host_set(ide_drive_t *drive, int on) |
26a940e2 | 340 | { |
26a940e2 PP |
341 | } |
342 | ||
53e62d3a | 343 | static void auide_ddma_tx_callback(int irq, void *param) |
26a940e2 | 344 | { |
8f29e650 JC |
345 | _auide_hwif *ahwif = (_auide_hwif*)param; |
346 | ahwif->drive->waiting_for_dma = 0; | |
26a940e2 PP |
347 | } |
348 | ||
53e62d3a | 349 | static void auide_ddma_rx_callback(int irq, void *param) |
26a940e2 | 350 | { |
8f29e650 JC |
351 | _auide_hwif *ahwif = (_auide_hwif*)param; |
352 | ahwif->drive->waiting_for_dma = 0; | |
353 | } | |
354 | ||
355 | #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ | |
26a940e2 | 356 | |
8f29e650 JC |
357 | static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) |
358 | { | |
359 | dev->dev_id = dev_id; | |
fcbd3b4b | 360 | dev->dev_physaddr = (u32)IDE_PHYS_ADDR; |
8f29e650 JC |
361 | dev->dev_intlevel = 0; |
362 | dev->dev_intpolarity = 0; | |
363 | dev->dev_tsize = tsize; | |
364 | dev->dev_devwidth = devwidth; | |
365 | dev->dev_flags = flags; | |
26a940e2 PP |
366 | } |
367 | ||
5e37bdc0 | 368 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
f37afdac | 369 | static const struct ide_dma_ops au1xxx_dma_ops = { |
5e37bdc0 BZ |
370 | .dma_host_set = auide_dma_host_set, |
371 | .dma_setup = auide_dma_setup, | |
372 | .dma_exec_cmd = auide_dma_exec_cmd, | |
373 | .dma_start = auide_dma_start, | |
374 | .dma_end = auide_dma_end, | |
375 | .dma_test_irq = auide_dma_test_irq, | |
de23ec9c | 376 | .dma_lost_irq = ide_dma_lost_irq, |
ffa15a69 | 377 | .dma_timeout = ide_dma_timeout, |
5e37bdc0 BZ |
378 | }; |
379 | ||
85528659 BZ |
380 | static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
381 | { | |
a536f326 | 382 | _auide_hwif *auide = &auide_hwif; |
8f29e650 JC |
383 | dbdev_tab_t source_dev_tab, target_dev_tab; |
384 | u32 dev_id, tsize, devwidth, flags; | |
26a940e2 | 385 | |
fcbd3b4b | 386 | dev_id = IDE_DDMA_REQ; |
26a940e2 | 387 | |
f629b38b BZ |
388 | tsize = 8; /* 1 */ |
389 | devwidth = 32; /* 16 */ | |
26a940e2 | 390 | |
8f29e650 JC |
391 | #ifdef IDE_AU1XXX_BURSTMODE |
392 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
26a940e2 | 393 | #else |
8f29e650 | 394 | flags = DEV_FLAGS_SYNC; |
26a940e2 PP |
395 | #endif |
396 | ||
8f29e650 JC |
397 | /* setup dev_tab for tx channel */ |
398 | auide_init_dbdma_dev( &source_dev_tab, | |
399 | dev_id, | |
400 | tsize, devwidth, DEV_FLAGS_OUT | flags); | |
401 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
402 | ||
403 | auide_init_dbdma_dev( &source_dev_tab, | |
404 | dev_id, | |
405 | tsize, devwidth, DEV_FLAGS_IN | flags); | |
406 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
407 | ||
408 | /* We also need to add a target device for the DMA */ | |
409 | auide_init_dbdma_dev( &target_dev_tab, | |
410 | (u32)DSCR_CMD0_ALWAYS, | |
411 | tsize, devwidth, DEV_FLAGS_ANYUSE); | |
412 | auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); | |
413 | ||
414 | /* Get a channel for TX */ | |
415 | auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, | |
416 | auide->tx_dev_id, | |
417 | auide_ddma_tx_callback, | |
418 | (void*)auide); | |
419 | ||
420 | /* Get a channel for RX */ | |
421 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
422 | auide->target_dev_id, | |
423 | auide_ddma_rx_callback, | |
424 | (void*)auide); | |
425 | ||
426 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
427 | NUM_DESCRIPTORS); | |
428 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
429 | NUM_DESCRIPTORS); | |
2bbd57ca BZ |
430 | |
431 | /* FIXME: check return value */ | |
432 | (void)ide_allocate_dma_engine(hwif); | |
8f29e650 JC |
433 | |
434 | au1xxx_dbdma_start( auide->tx_chan ); | |
435 | au1xxx_dbdma_start( auide->rx_chan ); | |
436 | ||
437 | return 0; | |
438 | } | |
26a940e2 | 439 | #else |
85528659 | 440 | static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
8f29e650 | 441 | { |
a536f326 | 442 | _auide_hwif *auide = &auide_hwif; |
8f29e650 JC |
443 | dbdev_tab_t source_dev_tab; |
444 | int flags; | |
26a940e2 | 445 | |
8f29e650 JC |
446 | #ifdef IDE_AU1XXX_BURSTMODE |
447 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
448 | #else | |
449 | flags = DEV_FLAGS_SYNC; | |
26a940e2 | 450 | #endif |
26a940e2 | 451 | |
8f29e650 JC |
452 | /* setup dev_tab for tx channel */ |
453 | auide_init_dbdma_dev( &source_dev_tab, | |
454 | (u32)DSCR_CMD0_ALWAYS, | |
455 | 8, 32, DEV_FLAGS_OUT | flags); | |
456 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
457 | ||
458 | auide_init_dbdma_dev( &source_dev_tab, | |
459 | (u32)DSCR_CMD0_ALWAYS, | |
460 | 8, 32, DEV_FLAGS_IN | flags); | |
461 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
462 | ||
463 | /* Get a channel for TX */ | |
464 | auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, | |
465 | auide->tx_dev_id, | |
466 | NULL, | |
467 | (void*)auide); | |
468 | ||
469 | /* Get a channel for RX */ | |
470 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
471 | DSCR_CMD0_ALWAYS, | |
472 | NULL, | |
473 | (void*)auide); | |
474 | ||
475 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
476 | NUM_DESCRIPTORS); | |
477 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
478 | NUM_DESCRIPTORS); | |
479 | ||
480 | au1xxx_dbdma_start( auide->tx_chan ); | |
481 | au1xxx_dbdma_start( auide->rx_chan ); | |
482 | ||
483 | return 0; | |
26a940e2 | 484 | } |
8f29e650 | 485 | #endif |
26a940e2 PP |
486 | |
487 | static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) | |
488 | { | |
8f29e650 | 489 | int i; |
4c3032d8 | 490 | unsigned long *ata_regs = hw->io_ports_array; |
8f29e650 JC |
491 | |
492 | /* FIXME? */ | |
4c3032d8 | 493 | for (i = 0; i < 8; i++) |
fcbd3b4b | 494 | *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT); |
8f29e650 JC |
495 | |
496 | /* set the Alternative Status register */ | |
fcbd3b4b | 497 | *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT); |
26a940e2 PP |
498 | } |
499 | ||
374e042c BZ |
500 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA |
501 | static const struct ide_tp_ops au1xxx_tp_ops = { | |
502 | .exec_command = ide_exec_command, | |
503 | .read_status = ide_read_status, | |
504 | .read_altstatus = ide_read_altstatus, | |
505 | .read_sff_dma_status = ide_read_sff_dma_status, | |
506 | ||
507 | .set_irq = ide_set_irq, | |
508 | ||
509 | .tf_load = ide_tf_load, | |
510 | .tf_read = ide_tf_read, | |
511 | ||
512 | .input_data = au1xxx_input_data, | |
513 | .output_data = au1xxx_output_data, | |
514 | }; | |
515 | #endif | |
516 | ||
ac95beed BZ |
517 | static const struct ide_port_ops au1xxx_port_ops = { |
518 | .set_pio_mode = au1xxx_set_pio_mode, | |
519 | .set_dma_mode = auide_set_dma_mode, | |
ac95beed BZ |
520 | }; |
521 | ||
c413b9b9 | 522 | static const struct ide_port_info au1xxx_port_info = { |
85528659 | 523 | .init_dma = auide_ddma_init, |
374e042c BZ |
524 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA |
525 | .tp_ops = &au1xxx_tp_ops, | |
526 | #endif | |
ac95beed | 527 | .port_ops = &au1xxx_port_ops, |
5e37bdc0 BZ |
528 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
529 | .dma_ops = &au1xxx_dma_ops, | |
530 | #endif | |
c413b9b9 | 531 | .host_flags = IDE_HFLAG_POST_SET_MODE | |
807b90d0 | 532 | IDE_HFLAG_NO_IO_32BIT | |
c413b9b9 BZ |
533 | IDE_HFLAG_UNMASK_IRQS, |
534 | .pio_mask = ATA_PIO4, | |
535 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
536 | .mwdma_mask = ATA_MWDMA2, | |
537 | #endif | |
538 | }; | |
539 | ||
26a940e2 PP |
540 | static int au_ide_probe(struct device *dev) |
541 | { | |
542 | struct platform_device *pdev = to_platform_device(dev); | |
8f29e650 | 543 | _auide_hwif *ahwif = &auide_hwif; |
26a940e2 | 544 | struct resource *res; |
48c3c107 | 545 | struct ide_host *host; |
26a940e2 | 546 | int ret = 0; |
c97c6aca | 547 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
26a940e2 PP |
548 | |
549 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
8f29e650 | 550 | char *mode = "MWDMA2"; |
26a940e2 | 551 | #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
8f29e650 | 552 | char *mode = "PIO+DDMA(offload)"; |
26a940e2 PP |
553 | #endif |
554 | ||
8f29e650 | 555 | memset(&auide_hwif, 0, sizeof(_auide_hwif)); |
26a940e2 PP |
556 | ahwif->irq = platform_get_irq(pdev, 0); |
557 | ||
558 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
559 | ||
560 | if (res == NULL) { | |
561 | pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id); | |
562 | ret = -ENODEV; | |
48944738 DV |
563 | goto out; |
564 | } | |
565 | if (ahwif->irq < 0) { | |
566 | pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id); | |
567 | ret = -ENODEV; | |
26a940e2 PP |
568 | goto out; |
569 | } | |
570 | ||
b4dcaea3 SS |
571 | if (!request_mem_region(res->start, res->end - res->start + 1, |
572 | pdev->name)) { | |
26a940e2 | 573 | pr_debug("%s: request_mem_region failed\n", DRV_NAME); |
8f29e650 | 574 | ret = -EBUSY; |
26a940e2 | 575 | goto out; |
8f29e650 | 576 | } |
26a940e2 | 577 | |
b4dcaea3 | 578 | ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1); |
26a940e2 PP |
579 | if (ahwif->regbase == 0) { |
580 | ret = -ENOMEM; | |
581 | goto out; | |
582 | } | |
583 | ||
9239b333 BZ |
584 | memset(&hw, 0, sizeof(hw)); |
585 | auide_setup_ports(&hw, ahwif); | |
aa79a2fa | 586 | hw.irq = ahwif->irq; |
ed1f7889 | 587 | hw.dev = dev; |
aa79a2fa BZ |
588 | hw.chipset = ide_au1xxx; |
589 | ||
6f904d01 BZ |
590 | ret = ide_host_add(&au1xxx_port_info, hws, &host); |
591 | if (ret) | |
48c3c107 | 592 | goto out; |
5cbf79cd | 593 | |
48c3c107 | 594 | auide_hwif.hwif = host->ports[0]; |
5cbf79cd | 595 | |
48c3c107 | 596 | dev_set_drvdata(dev, host); |
26a940e2 | 597 | |
8f29e650 | 598 | printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); |
26a940e2 | 599 | |
8f29e650 JC |
600 | out: |
601 | return ret; | |
26a940e2 PP |
602 | } |
603 | ||
604 | static int au_ide_remove(struct device *dev) | |
605 | { | |
606 | struct platform_device *pdev = to_platform_device(dev); | |
607 | struct resource *res; | |
48c3c107 | 608 | struct ide_host *host = dev_get_drvdata(dev); |
8f29e650 | 609 | _auide_hwif *ahwif = &auide_hwif; |
26a940e2 | 610 | |
48c3c107 | 611 | ide_host_remove(host); |
26a940e2 PP |
612 | |
613 | iounmap((void *)ahwif->regbase); | |
614 | ||
615 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b4dcaea3 | 616 | release_mem_region(res->start, res->end - res->start + 1); |
26a940e2 PP |
617 | |
618 | return 0; | |
619 | } | |
620 | ||
621 | static struct device_driver au1200_ide_driver = { | |
622 | .name = "au1200-ide", | |
623 | .bus = &platform_bus_type, | |
624 | .probe = au_ide_probe, | |
625 | .remove = au_ide_remove, | |
626 | }; | |
627 | ||
628 | static int __init au_ide_init(void) | |
629 | { | |
630 | return driver_register(&au1200_ide_driver); | |
631 | } | |
632 | ||
8f29e650 | 633 | static void __exit au_ide_exit(void) |
26a940e2 PP |
634 | { |
635 | driver_unregister(&au1200_ide_driver); | |
636 | } | |
637 | ||
26a940e2 PP |
638 | MODULE_LICENSE("GPL"); |
639 | MODULE_DESCRIPTION("AU1200 IDE driver"); | |
640 | ||
641 | module_init(au_ide_init); | |
642 | module_exit(au_ide_exit); |