[mirror_ubuntu-artful-kernel.git] / drivers / ide / cmd64x.c

/*
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007-2010	Bartlomiej Zolnierkiewicz
 * Copyright (C) 2007,2009	MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cmd64x"

/*
 * CMD64x specific registers definition.
 */
#define CFR		0x50
#define   CFR_INTR_CH0		0x04

#define	CMDTIM		0x52
#define	ARTTIM0		0x53
#define	DRWTIM0		0x54
#define ARTTIM1 	0x55
#define DRWTIM1		0x56
#define ARTTIM23	0x57
#define   ARTTIM23_DIS_RA2	0x04
#define   ARTTIM23_DIS_RA3	0x08
#define   ARTTIM23_INTR_CH1	0x10
#define DRWTIM2		0x58
#define BRST		0x59
#define DRWTIM3		0x5b

#define BMIDECR0	0x70
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define UDIDETCR0	0x73
#define DTPR0		0x74
#define BMIDECR1	0x78
#define BMIDECSR	0x79
#define UDIDETCR1	0x7B
#define DTPR1		0x7C

static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
	const unsigned long T = 1000000 / bus_speed;
	static const u8 recovery_values[] =
		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
	struct ide_timing t;
	u8 arttim = 0;

	ide_timing_compute(drive, mode, &t, T, 0);

	/*
	 * In case we've got too long recovery phase, try to lengthen
	 * the active phase
	 */
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)		/* shouldn't actually happen... */
		t.active = 16;

	/*
	 * Convert values to internal chipset representation
	 */
	t.recover = recovery_values[t.recover];
	t.active &= 0x0f;

	/* Program the active/recovery counts into the DRWTIM register */
	pci_write_config_byte(dev, drwtim_regs[drive->dn],
			      (t.active << 4) | t.recover);

	if (mode >= XFER_SW_DMA_0)
		return;

	/*
	 * The primary channel has individual address setup timing registers
	 * for each drive and the hardware selects the slowest timing itself.
	 * The secondary channel has one common register and we have to select
	 * the slowest address setup timing ourselves.
	 */
	if (hwif->channel) {
		ide_drive_t *pair = ide_get_pair_dev(drive);

		ide_set_drivedata(drive, (void *)(unsigned long)t.setup);

		if (pair)
			t.setup = max_t(u8, t.setup,
					(unsigned long)ide_get_drivedata(pair));
	}

	if (t.setup > 5)		/* shouldn't actually happen... */
		t.setup = 5;

	/*
	 * Program the address setup clocks into the ARTTIM registers.
	 * Avoid clearing the secondary channel's interrupt bit.
	 */
	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	if (hwif->channel)
		arttim &= ~ARTTIM23_INTR_CH1;
	arttim &= ~0xc0;
	arttim |= setup_values[t.setup];
	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
}

/*
 * Attempts to set drive's PIO mode.
 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 */

static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	/*
	 * Filter out the prefetch control values
	 * to prevent PIO5 from being programmed
	 */
	if (pio == 8 || pio == 9)
		return;

	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
}

static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 unit			= drive->dn & 0x01;
	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;

	pci_read_config_byte(dev, pciU, &regU);
	regU &= ~(unit ? 0xCA : 0x35);

	switch(speed) {
	case XFER_UDMA_5:
		regU |= unit ? 0x0A : 0x05;
		break;
	case XFER_UDMA_4:
		regU |= unit ? 0x4A : 0x15;
		break;
	case XFER_UDMA_3:
		regU |= unit ? 0x8A : 0x25;
		break;
	case XFER_UDMA_2:
		regU |= unit ? 0x42 : 0x11;
		break;
	case XFER_UDMA_1:
		regU |= unit ? 0x82 : 0x21;
		break;
	case XFER_UDMA_0:
		regU |= unit ? 0xC2 : 0x31;
		break;
	case XFER_MW_DMA_2:
	case XFER_MW_DMA_1:
	case XFER_MW_DMA_0:
		cmd64x_program_timings(drive, speed);
		break;
	}

	pci_write_config_byte(dev, pciU, regU);
}

static void cmd648_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8  irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8  mrdmode		= inb(base + 1);

	/* clear the interrupt bit */
	outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
	     base + 1);
}

static void cmd64x_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	/* clear the interrupt bit */
	(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
}

static int cmd648_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8 mrdmode		= inb(base + 1);

	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, mrdmode, irq_mask);

	return (mrdmode & irq_mask) ? 1 : 0;
}

static int cmd64x_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);

	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, irq_stat, irq_mask);

	return (irq_stat & irq_mask) ? 1 : 0;
}

/*
 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 * event order for DMA transfers.
 */

static int cmd646_1_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	/* get DMA status */
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* read DMA command state */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* clear the INTR & ERROR bits */
	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int init_chipset_cmd64x(struct pci_dev *dev)
{
	u8 mrdmode = 0;

	/* Set a good latency timer and cache line size value. */
	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	/* FIXME: pci_set_master() to ensure a good latency timer value */

	/*
	 * Enable interrupts, select MEMORY READ LINE for reads.
	 *
	 * NOTE: although not mentioned in the PCI0646U specs,
	 * bits 0-1 are write only and won't be read back as
	 * set or not -- PCI0646U2 specs clarify this point.
	 */
	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;
	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));

	return 0;
}

static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev  *dev	= to_pci_dev(hwif->dev);
	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	switch (dev->device) {
	case PCI_DEVICE_ID_CMD_648:
	case PCI_DEVICE_ID_CMD_649:
 		pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
		return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	default:
		return ATA_CBL_PATA40;
	}
}

static const struct ide_port_ops cmd64x_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd64x_clear_irq,
	.test_irq		= cmd64x_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_port_ops cmd648_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd648_clear_irq,
	.test_irq		= cmd648_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= cmd646_1_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
	{	/* 0: CMD643 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
		.port_ops	= &cmd64x_port_ops,
		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
				  IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* no udma */
	},
	{	/* 1: CMD646 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},
	{	/* 2: CMD648 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 3: CMD649 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = cmd64x_chipsets[idx];

	if (idx == 1) {
		/*
		 * UltraDMA only supported on PCI646U and PCI646U2, which
		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
		 * Actually, although the CMD tech support people won't
		 * tell me the details, the 0x03 revision cannot support
		 * UDMA correctly without hardware modifications, and even
		 * then it only works with Quantum disks due to some
		 * hold time assumptions in the 646U part which are fixed
		 * in the 646U2.
		 *
		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
		 */
		if (dev->revision < 5) {
			d.udma_mask = 0x00;
			/*
			 * The original PCI0646 didn't have the primary
			 * channel enable bit, it appeared starting with
			 * PCI0646U (i.e. revision ID 3).
			 */
			if (dev->revision < 3) {
				d.enablebits[0].reg = 0;
				d.port_ops = &cmd64x_port_ops;
				if (dev->revision == 1)
					d.dma_ops = &cmd646_rev1_dma_ops;
			}
		}
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id cmd64x_pci_tbl[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);

static struct pci_driver cmd64x_pci_driver = {
	.name		= "CMD64x_IDE",
	.id_table	= cmd64x_pci_tbl,
	.probe		= cmd64x_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cmd64x_ide_init(void)
{
	return ide_pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_ide_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

module_init(cmd64x_ide_init);
module_exit(cmd64x_ide_exit);

MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
60e7a82f	1	/*
1da177e4	2	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4 LT	3	* Due to massive hardware bugs, UltraDMA is only supported
	4	* on the 646U2 and not on the 646U.
	5	*
	6	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	7	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	8	*
	9	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
60349ab9	10	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
30e5ffc3	11	* Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	12	*/
1da177e4 LT	13
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/types.h>
	16	#include <linux/pci.h>
1da177e4 LT	17	#include <linux/ide.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/io.h>
	21
ced3ec8a BZ	22	#define DRV_NAME "cmd64x"
ced3ec8a BZ	23
1da177e4 LT	24	/*
	25	* CMD64x specific registers definition.
	26	*/
	27	#define CFR 0x50
e51e2528	28	#define CFR_INTR_CH0 0x04
1da177e4 LT	29
	30	#define CMDTIM 0x52
	31	#define ARTTIM0 0x53
	32	#define DRWTIM0 0x54
	33	#define ARTTIM1 0x55
	34	#define DRWTIM1 0x56
	35	#define ARTTIM23 0x57
	36	#define ARTTIM23_DIS_RA2 0x04
	37	#define ARTTIM23_DIS_RA3 0x08
	38	#define ARTTIM23_INTR_CH1 0x10
1da177e4 LT	39	#define DRWTIM2 0x58
	40	#define BRST 0x59
	41	#define DRWTIM3 0x5b
	42
	43	#define BMIDECR0 0x70
	44	#define MRDMODE 0x71
	45	#define MRDMODE_INTR_CH0 0x04
	46	#define MRDMODE_INTR_CH1 0x08
1da177e4 LT	47	#define UDIDETCR0 0x73
	48	#define DTPR0 0x74
	49	#define BMIDECR1 0x78
	50	#define BMIDECSR 0x79
1da177e4 LT	51	#define UDIDETCR1 0x7B
	52	#define DTPR1 0x7C
	53
60349ab9	54	static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
1da177e4	55	{
60349ab9	56	ide_hwif_t *hwif = drive->hwif;
ebae41a5	57	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
60349ab9 BZ	58	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
60349ab9 BZ	59	const unsigned long T = 1000000 / bus_speed;
60e7a82f	60	static const u8 recovery_values[] =
1da177e4	61	{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60349ab9 BZ	62	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
60349ab9 BZ	63	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
60e7a82f	64	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
60349ab9 BZ	65	struct ide_timing t;
60349ab9 BZ	66	u8 arttim = 0;
60e7a82f	67
60349ab9	68	ide_timing_compute(drive, mode, &t, T, 0);
60e7a82f	69
1da177e4	70	/*
60e7a82f SS	71	* In case we've got too long recovery phase, try to lengthen
60e7a82f SS	72	* the active phase
1da177e4	73	*/
60349ab9 BZ	74	if (t.recover > 16) {
	75	t.active += t.recover - 16;
	76	t.recover = 16;
1da177e4	77	}
60349ab9 BZ	78	if (t.active > 16) /* shouldn't actually happen... */
60349ab9 BZ	79	t.active = 16;
60e7a82f	80
1da177e4 LT	81	/*
	82	* Convert values to internal chipset representation
	83	*/
60349ab9 BZ	84	t.recover = recovery_values[t.recover];
60349ab9 BZ	85	t.active &= 0x0f;
1da177e4	86
60e7a82f	87	/* Program the active/recovery counts into the DRWTIM register */
60349ab9 BZ	88	pci_write_config_byte(dev, drwtim_regs[drive->dn],
60349ab9 BZ	89	(t.active << 4) \| t.recover);
1da177e4	90
60349ab9 BZ	91	if (mode >= XFER_SW_DMA_0)
60349ab9 BZ	92	return;
60e7a82f SS	93
	94	/*
	95	* The primary channel has individual address setup timing registers
	96	* for each drive and the hardware selects the slowest timing itself.
	97	* The secondary channel has one common register and we have to select
	98	* the slowest address setup timing ourselves.
	99	*/
	100	if (hwif->channel) {
5d44a150	101	ide_drive_t *pair = ide_get_pair_dev(drive);
60e7a82f	102
60349ab9	103	ide_set_drivedata(drive, (void *)(unsigned long)t.setup);
5d44a150 BZ	104
5d44a150 BZ	105	if (pair)
60349ab9	106	t.setup = max_t(u8, t.setup,
5bfb151f	107	(unsigned long)ide_get_drivedata(pair));
1da177e4	108	}
1da177e4	109
60349ab9 BZ	110	if (t.setup > 5) /* shouldn't actually happen... */
60349ab9 BZ	111	t.setup = 5;
1da177e4	112
60e7a82f SS	113	/*
	114	* Program the address setup clocks into the ARTTIM registers.
	115	* Avoid clearing the secondary channel's interrupt bit.
	116	*/
	117	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	118	if (hwif->channel)
	119	arttim &= ~ARTTIM23_INTR_CH1;
	120	arttim &= ~0xc0;
60349ab9	121	arttim \|= setup_values[t.setup];
60e7a82f	122	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
f92d50e6 SS	123	}
	124
	125	/*
	126	* Attempts to set drive's PIO mode.
26bcb879	127	* Special cases are 8: prefetch off, 9: prefetch on (both never worked)
f92d50e6	128	*/
26bcb879	129
e085b3ca	130	static void cmd64x_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
f92d50e6	131	{
e085b3ca BZ	132	const u8 pio = drive->pio_mode - XFER_PIO_0;
e085b3ca BZ	133
f92d50e6 SS	134	/*
	135	* Filter out the prefetch control values
	136	* to prevent PIO5 from being programmed
	137	*/
	138	if (pio == 8 \|\| pio == 9)
	139	return;
	140
60349ab9	141	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
1da177e4 LT	142	}
1da177e4 LT	143
88b2b32b	144	static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	145	{
898ec223	146	ide_hwif_t *hwif = drive->hwif;
36501650	147	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e7a82f SS	148	u8 unit = drive->dn & 0x01;
60e7a82f SS	149	u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
1da177e4	150
22cabc26 BZ	151	pci_read_config_byte(dev, pciU, &regU);
22cabc26 BZ	152	regU &= ~(unit ? 0xCA : 0x35);
1da177e4 LT	153
1da177e4 LT	154	switch(speed) {
60e7a82f SS	155	case XFER_UDMA_5:
	156	regU \|= unit ? 0x0A : 0x05;
	157	break;
	158	case XFER_UDMA_4:
	159	regU \|= unit ? 0x4A : 0x15;
	160	break;
	161	case XFER_UDMA_3:
	162	regU \|= unit ? 0x8A : 0x25;
	163	break;
	164	case XFER_UDMA_2:
	165	regU \|= unit ? 0x42 : 0x11;
	166	break;
	167	case XFER_UDMA_1:
	168	regU \|= unit ? 0x82 : 0x21;
	169	break;
	170	case XFER_UDMA_0:
	171	regU \|= unit ? 0xC2 : 0x31;
	172	break;
	173	case XFER_MW_DMA_2:
60e7a82f	174	case XFER_MW_DMA_1:
60e7a82f	175	case XFER_MW_DMA_0:
60349ab9	176	cmd64x_program_timings(drive, speed);
60e7a82f	177	break;
1da177e4 LT	178	}
1da177e4 LT	179
22cabc26	180	pci_write_config_byte(dev, pciU, regU);
1da177e4 LT	181	}
1da177e4 LT	182
30e5ffc3	183	static void cmd648_clear_irq(ide_drive_t *drive)
1da177e4	184	{
898ec223	185	ide_hwif_t *hwif = drive->hwif;
30e5ffc3 SS	186	struct pci_dev *dev = to_pci_dev(hwif->dev);
30e5ffc3 SS	187	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	188	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	189	MRDMODE_INTR_CH0;
1c029fd6	190	u8 mrdmode = inb(base + 1);
66602c83 SS	191
66602c83 SS	192	/* clear the interrupt bit */
6183289c	193	outb((mrdmode & ~(MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1)) \| irq_mask,
1c029fd6	194	base + 1);
1da177e4 LT	195	}
1da177e4 LT	196
30e5ffc3	197	static void cmd64x_clear_irq(ide_drive_t *drive)
1da177e4	198	{
898ec223	199	ide_hwif_t *hwif = drive->hwif;
36501650	200	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	201	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	202	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	203	CFR_INTR_CH0;
	204	u8 irq_stat = 0;
1da177e4	205
66602c83 SS	206	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	207	/* clear the interrupt bit */
	208	(void) pci_write_config_byte(dev, irq_reg, irq_stat \| irq_mask);
66602c83 SS	209	}
66602c83 SS	210
628df2f3	211	static int cmd648_test_irq(ide_hwif_t *hwif)
66602c83	212	{
628df2f3 SS	213	struct pci_dev *dev = to_pci_dev(hwif->dev);
628df2f3 SS	214	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	215	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	216	MRDMODE_INTR_CH0;
1c029fd6	217	u8 mrdmode = inb(base + 1);
66602c83	218
628df2f3 SS	219	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	220	hwif->name, mrdmode, irq_mask);
66602c83	221
628df2f3	222	return (mrdmode & irq_mask) ? 1 : 0;
1da177e4 LT	223	}
1da177e4 LT	224
628df2f3	225	static int cmd64x_test_irq(ide_hwif_t *hwif)
1da177e4	226	{
36501650	227	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	228	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	229	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	230	CFR_INTR_CH0;
66602c83	231	u8 irq_stat = 0;
e51e2528 SS	232
e51e2528 SS	233	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4	234
628df2f3 SS	235	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	236	hwif->name, irq_stat, irq_mask);
1da177e4	237
628df2f3	238	return (irq_stat & irq_mask) ? 1 : 0;
1da177e4 LT	239	}
	240
	241	/*
	242	* ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
	243	* event order for DMA transfers.
	244	*/
	245
5e37bdc0	246	static int cmd646_1_dma_end(ide_drive_t *drive)
1da177e4	247	{
898ec223	248	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	249	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	250
1da177e4	251	/* get DMA status */
cab7f8ed	252	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
1da177e4	253	/* read DMA command state */
cab7f8ed	254	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	255	/* stop DMA */
cab7f8ed	256	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	257	/* clear the INTR & ERROR bits */
cab7f8ed	258	outb(dma_stat \| 6, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	259	/* verify good DMA status */
	260	return (dma_stat & 7) != 4;
	261	}
	262
2ed0ef54	263	static int init_chipset_cmd64x(struct pci_dev *dev)
1da177e4	264	{
1da177e4 LT	265	u8 mrdmode = 0;
1da177e4 LT	266
1da177e4 LT	267	/* Set a good latency timer and cache line size value. */
	268	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	269	/* FIXME: pci_set_master() to ensure a good latency timer value */
	270
83a6d4ab SS	271	/*
	272	* Enable interrupts, select MEMORY READ LINE for reads.
	273	*
	274	* NOTE: although not mentioned in the PCI0646U specs,
	275	* bits 0-1 are write only and won't be read back as
	276	* set or not -- PCI0646U2 specs clarify this point.
1da177e4	277	*/
83a6d4ab SS	278	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	279	mrdmode &= ~0x30;
	280	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode \| 0x02));
1da177e4	281
1da177e4 LT	282	return 0;
	283	}
	284
f454cbe8	285	static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
1da177e4	286	{
36501650	287	struct pci_dev *dev = to_pci_dev(hwif->dev);
83a6d4ab	288	u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
1da177e4	289
83a6d4ab SS	290	switch (dev->device) {
	291	case PCI_DEVICE_ID_CMD_648:
	292	case PCI_DEVICE_ID_CMD_649:
	293	pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
49521f97	294	return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
83a6d4ab	295	default:
49521f97	296	return ATA_CBL_PATA40;
1da177e4	297	}
1da177e4 LT	298	}
1da177e4 LT	299
ac95beed BZ	300	static const struct ide_port_ops cmd64x_port_ops = {
	301	.set_pio_mode = cmd64x_set_pio_mode,
	302	.set_dma_mode = cmd64x_set_dma_mode,
30e5ffc3	303	.clear_irq = cmd64x_clear_irq,
628df2f3	304	.test_irq = cmd64x_test_irq,
30e5ffc3 SS	305	.cable_detect = cmd64x_cable_detect,
	306	};
	307
	308	static const struct ide_port_ops cmd648_port_ops = {
	309	.set_pio_mode = cmd64x_set_pio_mode,
	310	.set_dma_mode = cmd64x_set_dma_mode,
	311	.clear_irq = cmd648_clear_irq,
628df2f3	312	.test_irq = cmd648_test_irq,
ac95beed BZ	313	.cable_detect = cmd64x_cable_detect,
	314	};
	315
f37afdac BZ	316	static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	317	.dma_host_set = ide_dma_host_set,
	318	.dma_setup = ide_dma_setup,
f37afdac	319	.dma_start = ide_dma_start,
5e37bdc0	320	.dma_end = cmd646_1_dma_end,
f37afdac BZ	321	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	322	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	323	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	324	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	325	};
5e37bdc0 BZ	326
85620436	327	static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
ced3ec8a BZ	328	{ /* 0: CMD643 */
ced3ec8a BZ	329	.name = DRV_NAME,
1da177e4	330	.init_chipset = init_chipset_cmd64x,
7accbffd	331	.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
ac95beed	332	.port_ops = &cmd64x_port_ops,
8ac2b42a	333	.host_flags = IDE_HFLAG_CLEAR_SIMPLEX \|
9bd7496f MP	334	IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	335	IDE_HFLAG_SERIALIZE,
4099d143	336	.pio_mask = ATA_PIO5,
5f8b6c34	337	.mwdma_mask = ATA_MWDMA2,
18137207	338	.udma_mask = 0x00, /* no udma */
ced3ec8a BZ	339	},
	340	{ /* 1: CMD646 */
	341	.name = DRV_NAME,
1da177e4	342	.init_chipset = init_chipset_cmd64x,
7accbffd	343	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	344	.port_ops = &cmd648_port_ops,
9bd7496f MP	345	.host_flags = IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	346	IDE_HFLAG_SERIALIZE,
4099d143	347	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	348	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	349	.udma_mask = ATA_UDMA2,
ced3ec8a BZ	350	},
	351	{ /* 2: CMD648 */
	352	.name = DRV_NAME,
1da177e4	353	.init_chipset = init_chipset_cmd64x,
7accbffd	354	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	355	.port_ops = &cmd648_port_ops,
5e71d9c5	356	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	357	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	358	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	359	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	360	},
	361	{ /* 3: CMD649 */
	362	.name = DRV_NAME,
1da177e4	363	.init_chipset = init_chipset_cmd64x,
7accbffd	364	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	365	.port_ops = &cmd648_port_ops,
5e71d9c5	366	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	367	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	368	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	369	.udma_mask = ATA_UDMA5,
1da177e4 LT	370	}
	371	};
	372
	373	static int __devinit cmd64x_init_one(struct pci_dev dev, const struct pci_device_id id)
	374	{
039788e1	375	struct ide_port_info d;
bfd314a3 BZ	376	u8 idx = id->driver_data;
	377
	378	d = cmd64x_chipsets[idx];
	379
5e37bdc0 BZ	380	if (idx == 1) {
	381	/*
	382	* UltraDMA only supported on PCI646U and PCI646U2, which
	383	* correspond to revisions 0x03, 0x05 and 0x07 respectively.
	384	* Actually, although the CMD tech support people won't
	385	* tell me the details, the 0x03 revision cannot support
	386	* UDMA correctly without hardware modifications, and even
	387	* then it only works with Quantum disks due to some
	388	* hold time assumptions in the 646U part which are fixed
	389	* in the 646U2.
	390	*
	391	* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
	392	*/
	393	if (dev->revision < 5) {
	394	d.udma_mask = 0x00;
	395	/*
	396	* The original PCI0646 didn't have the primary
	397	* channel enable bit, it appeared starting with
	398	* PCI0646U (i.e. revision ID 3).
	399	*/
	400	if (dev->revision < 3) {
	401	d.enablebits[0].reg = 0;
30e5ffc3	402	d.port_ops = &cmd64x_port_ops;
5e37bdc0 BZ	403	if (dev->revision == 1)
5e37bdc0 BZ	404	d.dma_ops = &cmd646_rev1_dma_ops;
5e37bdc0 BZ	405	}
	406	}
	407	}
7accbffd	408
6cdf6eb3	409	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	410	}
1da177e4 LT	411
9cbcc5e3 BZ	412	static const struct pci_device_id cmd64x_pci_tbl[] = {
	413	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	414	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	415	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	416	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
1da177e4 LT	417	{ 0, },
	418	};
	419	MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
	420
a9ab09e2	421	static struct pci_driver cmd64x_pci_driver = {
1da177e4 LT	422	.name = "CMD64x_IDE",
	423	.id_table = cmd64x_pci_tbl,
	424	.probe = cmd64x_init_one,
e2b15b47	425	.remove = ide_pci_remove,
feb22b7f BZ	426	.suspend = ide_pci_suspend,
feb22b7f BZ	427	.resume = ide_pci_resume,
1da177e4 LT	428	};
1da177e4 LT	429
82ab1eec	430	static int __init cmd64x_ide_init(void)
1da177e4	431	{
a9ab09e2	432	return ide_pci_register_driver(&cmd64x_pci_driver);
1da177e4 LT	433	}
1da177e4 LT	434
e2b15b47 BZ	435	static void __exit cmd64x_ide_exit(void)
e2b15b47 BZ	436	{
a9ab09e2	437	pci_unregister_driver(&cmd64x_pci_driver);
e2b15b47 BZ	438	}
e2b15b47 BZ	439
1da177e4	440	module_init(cmd64x_ide_init);
e2b15b47	441	module_exit(cmd64x_ide_exit);
1da177e4	442
60349ab9	443	MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	444	MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
1da177e4 LT	445	MODULE_LICENSE("GPL");