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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer |
3 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator | |
4 | * | |
5 | * CYPRESS CY82C693 chipset IDE controller | |
6 | * | |
7 | * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards. | |
8 | * Writing the driver was quite simple, since most of the job is | |
175f354b | 9 | * done by the generic pci-ide support. |
1da177e4 LT |
10 | * The hard part was finding the CY82C693's datasheet on Cypress's |
11 | * web page :-(. But Altavista solved this problem :-). | |
12 | * | |
13 | * | |
14 | * Notes: | |
15 | * - I recently got a 16.8G IBM DTTA, so I was able to test it with | |
16 | * a large and fast disk - the results look great, so I'd say the | |
17 | * driver is working fine :-) | |
175f354b PC |
18 | * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA |
19 | * - this is my first linux driver, so there's probably a lot of room | |
1da177e4 | 20 | * for optimizations and bug fixing, so feel free to do it. |
175f354b | 21 | * - if using PIO mode it's a good idea to set the PIO mode and |
1da177e4 LT |
22 | * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda |
23 | * - I had some problems with my IBM DHEA with PIO modes < 2 | |
24 | * (lost interrupts) ????? | |
25 | * - first tests with DMA look okay, they seem to work, but there is a | |
26 | * problem with sound - the BusMaster IDE TimeOut should fixed this | |
27 | * | |
28 | * Ancient History: | |
29 | * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693 | |
30 | * ASK@1999-01-23: v0.33 made a few minor code clean ups | |
31 | * removed DMA clock speed setting by default | |
32 | * added boot message | |
33 | * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut | |
34 | * added support to set DMA Controller Clock Speed | |
35 | * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes | |
36 | * on some drives. | |
37 | * ASK@1998-10-29: v0.3 added support to set DMA modes | |
38 | * ASK@1998-10-28: v0.2 added support to set PIO modes | |
39 | * ASK@1998-10-27: v0.1 first version - chipset detection | |
40 | * | |
41 | */ | |
42 | ||
1da177e4 LT |
43 | #include <linux/module.h> |
44 | #include <linux/types.h> | |
45 | #include <linux/pci.h> | |
1da177e4 LT |
46 | #include <linux/ide.h> |
47 | #include <linux/init.h> | |
48 | ||
49 | #include <asm/io.h> | |
50 | ||
ced3ec8a BZ |
51 | #define DRV_NAME "cy82c693" |
52 | ||
1da177e4 LT |
53 | /* |
54 | * NOTE: the value for busmaster timeout is tricky and I got it by | |
55 | * trial and error! By using a to low value will cause DMA timeouts | |
56 | * and drop IDE performance, and by using a to high value will cause | |
57 | * audio playback to scatter. | |
58 | * If you know a better value or how to calc it, please let me know. | |
59 | */ | |
60 | ||
61 | /* twice the value written in cy82c693ub datasheet */ | |
62 | #define BUSMASTER_TIMEOUT 0x50 | |
63 | /* | |
64 | * the value above was tested on my machine and it seems to work okay | |
65 | */ | |
66 | ||
67 | /* here are the offset definitions for the registers */ | |
68 | #define CY82_IDE_CMDREG 0x04 | |
69 | #define CY82_IDE_ADDRSETUP 0x48 | |
70 | #define CY82_IDE_MASTER_IOR 0x4C | |
71 | #define CY82_IDE_MASTER_IOW 0x4D | |
72 | #define CY82_IDE_SLAVE_IOR 0x4E | |
73 | #define CY82_IDE_SLAVE_IOW 0x4F | |
74 | #define CY82_IDE_MASTER_8BIT 0x50 | |
75 | #define CY82_IDE_SLAVE_8BIT 0x51 | |
76 | ||
77 | #define CY82_INDEX_PORT 0x22 | |
78 | #define CY82_DATA_PORT 0x23 | |
79 | ||
1da177e4 LT |
80 | #define CY82_INDEX_CHANNEL0 0x30 |
81 | #define CY82_INDEX_CHANNEL1 0x31 | |
82 | #define CY82_INDEX_TIMEOUT 0x32 | |
83 | ||
1da177e4 LT |
84 | /* the min and max PCI bus speed in MHz - from datasheet */ |
85 | #define CY82C963_MIN_BUS_SPEED 25 | |
86 | #define CY82C963_MAX_BUS_SPEED 33 | |
87 | ||
88 | /* the struct for the PIO mode timings */ | |
89 | typedef struct pio_clocks_s { | |
90 | u8 address_time; /* Address setup (clocks) */ | |
91 | u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */ | |
92 | u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */ | |
93 | u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */ | |
94 | } pio_clocks_t; | |
95 | ||
96 | /* | |
97 | * calc clocks using bus_speed | |
98 | * returns (rounded up) time in bus clocks for time in ns | |
99 | */ | |
175f354b | 100 | static int calc_clk(int time, int bus_speed) |
1da177e4 LT |
101 | { |
102 | int clocks; | |
103 | ||
175f354b | 104 | clocks = (time*bus_speed+999)/1000 - 1; |
1da177e4 LT |
105 | |
106 | if (clocks < 0) | |
107 | clocks = 0; | |
108 | ||
109 | if (clocks > 0x0F) | |
110 | clocks = 0x0F; | |
111 | ||
112 | return clocks; | |
113 | } | |
114 | ||
115 | /* | |
116 | * compute the values for the clock registers for PIO | |
117 | * mode and pci_clk [MHz] speed | |
118 | * | |
119 | * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used | |
120 | * for mode 3 and 4 drives 8 and 16-bit timings are the same | |
121 | * | |
175f354b PC |
122 | */ |
123 | static void compute_clocks(u8 pio, pio_clocks_t *p_pclk) | |
1da177e4 | 124 | { |
713a590d | 125 | struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); |
1da177e4 | 126 | int clk1, clk2; |
30e5ee4d | 127 | int bus_speed = ide_pci_clk ? ide_pci_clk : 33; |
1da177e4 LT |
128 | |
129 | /* we don't check against CY82C693's min and max speed, | |
130 | * so you can play with the idebus=xx parameter | |
131 | */ | |
132 | ||
1da177e4 | 133 | /* let's calc the address setup time clocks */ |
713a590d | 134 | p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed); |
1da177e4 LT |
135 | |
136 | /* let's calc the active and recovery time clocks */ | |
713a590d | 137 | clk1 = calc_clk(t->active, bus_speed); |
1da177e4 LT |
138 | |
139 | /* calc recovery timing */ | |
713a590d | 140 | clk2 = t->cycle - t->active - t->setup; |
1da177e4 LT |
141 | |
142 | clk2 = calc_clk(clk2, bus_speed); | |
143 | ||
144 | clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */ | |
145 | ||
146 | /* note: we use the same values for 16bit IOR and IOW | |
175f354b | 147 | * those are all the same, since I don't have other |
1da177e4 LT |
148 | * timings than those from ide-lib.c |
149 | */ | |
150 | ||
151 | p_pclk->time_16r = (u8)clk1; | |
152 | p_pclk->time_16w = (u8)clk1; | |
153 | ||
154 | /* what are good values for 8bit ?? */ | |
155 | p_pclk->time_8 = (u8)clk1; | |
156 | } | |
157 | ||
158 | /* | |
159 | * set DMA mode a specific channel for CY82C693 | |
160 | */ | |
161 | ||
8704de8f | 162 | static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) |
1da177e4 | 163 | { |
8704de8f BZ |
164 | ide_hwif_t *hwif = drive->hwif; |
165 | u8 single = (mode & 0x10) >> 4, index = 0, data = 0; | |
1da177e4 | 166 | |
8704de8f | 167 | index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; |
1da177e4 | 168 | |
8704de8f | 169 | data = (mode & 3) | (single << 2); |
1da177e4 | 170 | |
0ecdca26 BZ |
171 | outb(index, CY82_INDEX_PORT); |
172 | outb(data, CY82_DATA_PORT); | |
1da177e4 | 173 | |
175f354b | 174 | /* |
1da177e4 LT |
175 | * note: below we set the value for Bus Master IDE TimeOut Register |
176 | * I'm not absolutly sure what this does, but it solved my problem | |
177 | * with IDE DMA and sound, so I now can play sound and work with | |
178 | * my IDE driver at the same time :-) | |
179 | * | |
180 | * If you know the correct (best) value for this register please | |
181 | * let me know - ASK | |
182 | */ | |
183 | ||
184 | data = BUSMASTER_TIMEOUT; | |
0ecdca26 BZ |
185 | outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); |
186 | outb(data, CY82_DATA_PORT); | |
1da177e4 LT |
187 | } |
188 | ||
26bcb879 | 189 | static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 190 | { |
898ec223 | 191 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 192 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
193 | pio_clocks_t pclk; |
194 | unsigned int addrCtrl; | |
195 | ||
196 | /* select primary or secondary channel */ | |
197 | if (hwif->index > 0) { /* drive is on the secondary channel */ | |
652aa162 | 198 | dev = pci_get_slot(dev->bus, dev->devfn+1); |
1da177e4 LT |
199 | if (!dev) { |
200 | printk(KERN_ERR "%s: tune_drive: " | |
201 | "Cannot find secondary interface!\n", | |
202 | drive->name); | |
203 | return; | |
204 | } | |
205 | } | |
206 | ||
1da177e4 LT |
207 | /* let's calc the values for this PIO mode */ |
208 | compute_clocks(pio, &pclk); | |
209 | ||
210 | /* now let's write the clocks registers */ | |
123995b9 | 211 | if ((drive->dn & 1) == 0) { |
1da177e4 LT |
212 | /* |
213 | * set master drive | |
214 | * address setup control register | |
215 | * is 32 bit !!! | |
175f354b | 216 | */ |
1da177e4 | 217 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); |
175f354b | 218 | |
1da177e4 LT |
219 | addrCtrl &= (~0xF); |
220 | addrCtrl |= (unsigned int)pclk.address_time; | |
221 | pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); | |
222 | ||
223 | /* now let's set the remaining registers */ | |
224 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); | |
225 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); | |
226 | pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); | |
1da177e4 LT |
227 | } else { |
228 | /* | |
229 | * set slave drive | |
230 | * address setup control register | |
231 | * is 32 bit !!! | |
175f354b | 232 | */ |
1da177e4 LT |
233 | pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); |
234 | ||
235 | addrCtrl &= (~0xF0); | |
236 | addrCtrl |= ((unsigned int)pclk.address_time<<4); | |
237 | pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); | |
238 | ||
239 | /* now let's set the remaining registers */ | |
240 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); | |
241 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); | |
242 | pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); | |
175f354b | 243 | } |
1da177e4 LT |
244 | } |
245 | ||
e851b620 | 246 | static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) |
1da177e4 | 247 | { |
f32d26ae | 248 | static ide_hwif_t *primary; |
36501650 | 249 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
f32d26ae | 250 | |
36501650 | 251 | if (PCI_FUNC(dev->devfn) == 1) |
1da177e4 LT |
252 | primary = hwif; |
253 | else { | |
254 | hwif->mate = primary; | |
255 | hwif->channel = 1; | |
256 | } | |
257 | } | |
258 | ||
ac95beed BZ |
259 | static const struct ide_port_ops cy82c693_port_ops = { |
260 | .set_pio_mode = cy82c693_set_pio_mode, | |
261 | .set_dma_mode = cy82c693_set_dma_mode, | |
262 | }; | |
263 | ||
85620436 | 264 | static const struct ide_port_info cy82c693_chipset __devinitdata = { |
ced3ec8a | 265 | .name = DRV_NAME, |
7b77d864 | 266 | .init_iops = init_iops_cy82c693, |
ac95beed | 267 | .port_ops = &cy82c693_port_ops, |
951784b6 | 268 | .host_flags = IDE_HFLAG_SINGLE, |
4099d143 | 269 | .pio_mask = ATA_PIO4, |
8704de8f BZ |
270 | .swdma_mask = ATA_SWDMA2, |
271 | .mwdma_mask = ATA_MWDMA2, | |
1da177e4 LT |
272 | }; |
273 | ||
274 | static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
275 | { | |
1da177e4 LT |
276 | struct pci_dev *dev2; |
277 | int ret = -ENODEV; | |
278 | ||
279 | /* CY82C693 is more than only a IDE controller. | |
280 | Function 1 is primary IDE channel, function 2 - secondary. */ | |
175f354b | 281 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
1da177e4 | 282 | PCI_FUNC(dev->devfn) == 1) { |
652aa162 | 283 | dev2 = pci_get_slot(dev->bus, dev->devfn + 1); |
6cdf6eb3 | 284 | ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL); |
cd68841b BZ |
285 | if (ret) |
286 | pci_dev_put(dev2); | |
1da177e4 LT |
287 | } |
288 | return ret; | |
289 | } | |
290 | ||
cd68841b BZ |
291 | static void __devexit cy82c693_remove(struct pci_dev *dev) |
292 | { | |
293 | struct ide_host *host = pci_get_drvdata(dev); | |
294 | struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; | |
295 | ||
296 | ide_pci_remove(dev); | |
297 | pci_dev_put(dev2); | |
298 | } | |
299 | ||
9cbcc5e3 BZ |
300 | static const struct pci_device_id cy82c693_pci_tbl[] = { |
301 | { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 }, | |
1da177e4 LT |
302 | { 0, }, |
303 | }; | |
304 | MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl); | |
305 | ||
a9ab09e2 | 306 | static struct pci_driver cy82c693_pci_driver = { |
1da177e4 LT |
307 | .name = "Cypress_IDE", |
308 | .id_table = cy82c693_pci_tbl, | |
309 | .probe = cy82c693_init_one, | |
a69999e2 | 310 | .remove = __devexit_p(cy82c693_remove), |
feb22b7f BZ |
311 | .suspend = ide_pci_suspend, |
312 | .resume = ide_pci_resume, | |
1da177e4 LT |
313 | }; |
314 | ||
82ab1eec | 315 | static int __init cy82c693_ide_init(void) |
1da177e4 | 316 | { |
a9ab09e2 | 317 | return ide_pci_register_driver(&cy82c693_pci_driver); |
1da177e4 LT |
318 | } |
319 | ||
cd68841b BZ |
320 | static void __exit cy82c693_ide_exit(void) |
321 | { | |
a9ab09e2 | 322 | pci_unregister_driver(&cy82c693_pci_driver); |
cd68841b BZ |
323 | } |
324 | ||
1da177e4 | 325 | module_init(cy82c693_ide_init); |
cd68841b | 326 | module_exit(cy82c693_ide_exit); |
1da177e4 LT |
327 | |
328 | MODULE_AUTHOR("Andreas Krebs, Andre Hedrick"); | |
329 | MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE"); | |
330 | MODULE_LICENSE("GPL"); |