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Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (c) 1996-2004 Russell King. |
3 | * | |
4 | * Please note that this platform does not support 32-bit IDE IO. | |
5 | */ | |
6 | ||
1da177e4 LT |
7 | #include <linux/string.h> |
8 | #include <linux/module.h> | |
9 | #include <linux/ioport.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/blkdev.h> | |
12 | #include <linux/errno.h> | |
1da177e4 LT |
13 | #include <linux/ide.h> |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/scatterlist.h> | |
ba5b55d0 | 18 | #include <linux/io.h> |
1da177e4 LT |
19 | |
20 | #include <asm/dma.h> | |
21 | #include <asm/ecard.h> | |
1da177e4 | 22 | |
67717e22 BZ |
23 | #define DRV_NAME "icside" |
24 | ||
1da177e4 LT |
25 | #define ICS_IDENT_OFFSET 0x2280 |
26 | ||
27 | #define ICS_ARCIN_V5_INTRSTAT 0x0000 | |
28 | #define ICS_ARCIN_V5_INTROFFSET 0x0004 | |
29 | #define ICS_ARCIN_V5_IDEOFFSET 0x2800 | |
30 | #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80 | |
31 | #define ICS_ARCIN_V5_IDESTEPPING 6 | |
32 | ||
33 | #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000 | |
34 | #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 | |
35 | #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 | |
36 | #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380 | |
37 | #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000 | |
38 | #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 | |
39 | #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 | |
40 | #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380 | |
41 | #define ICS_ARCIN_V6_IDESTEPPING 6 | |
42 | ||
43 | struct cardinfo { | |
44 | unsigned int dataoffset; | |
45 | unsigned int ctrloffset; | |
46 | unsigned int stepping; | |
47 | }; | |
48 | ||
49 | static struct cardinfo icside_cardinfo_v5 = { | |
50 | .dataoffset = ICS_ARCIN_V5_IDEOFFSET, | |
51 | .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET, | |
52 | .stepping = ICS_ARCIN_V5_IDESTEPPING, | |
53 | }; | |
54 | ||
55 | static struct cardinfo icside_cardinfo_v6_1 = { | |
56 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1, | |
57 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1, | |
58 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
59 | }; | |
60 | ||
61 | static struct cardinfo icside_cardinfo_v6_2 = { | |
62 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2, | |
63 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2, | |
64 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
65 | }; | |
66 | ||
67 | struct icside_state { | |
68 | unsigned int channel; | |
69 | unsigned int enabled; | |
70 | void __iomem *irq_port; | |
71 | void __iomem *ioc_base; | |
26839f09 | 72 | unsigned int sel; |
1da177e4 | 73 | unsigned int type; |
48c3c107 | 74 | struct ide_host *host; |
1da177e4 LT |
75 | }; |
76 | ||
77 | #define ICS_TYPE_A3IN 0 | |
78 | #define ICS_TYPE_A3USER 1 | |
79 | #define ICS_TYPE_V6 3 | |
80 | #define ICS_TYPE_V5 15 | |
81 | #define ICS_TYPE_NOTYPE ((unsigned int)-1) | |
82 | ||
83 | /* ---------------- Version 5 PCB Support Functions --------------------- */ | |
84 | /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
85 | * Purpose : enable interrupts from card | |
86 | */ | |
87 | static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
88 | { | |
89 | struct icside_state *state = ec->irq_data; | |
90 | ||
91 | writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
92 | } | |
93 | ||
94 | /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
95 | * Purpose : disable interrupts from card | |
96 | */ | |
97 | static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
98 | { | |
99 | struct icside_state *state = ec->irq_data; | |
100 | ||
101 | readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
102 | } | |
103 | ||
104 | static const expansioncard_ops_t icside_ops_arcin_v5 = { | |
105 | .irqenable = icside_irqenable_arcin_v5, | |
106 | .irqdisable = icside_irqdisable_arcin_v5, | |
107 | }; | |
108 | ||
109 | ||
110 | /* ---------------- Version 6 PCB Support Functions --------------------- */ | |
111 | /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
112 | * Purpose : enable interrupts from card | |
113 | */ | |
114 | static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
115 | { | |
116 | struct icside_state *state = ec->irq_data; | |
117 | void __iomem *base = state->irq_port; | |
118 | ||
119 | state->enabled = 1; | |
120 | ||
121 | switch (state->channel) { | |
122 | case 0: | |
123 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); | |
124 | readb(base + ICS_ARCIN_V6_INTROFFSET_2); | |
125 | break; | |
126 | case 1: | |
127 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); | |
128 | readb(base + ICS_ARCIN_V6_INTROFFSET_1); | |
129 | break; | |
130 | } | |
131 | } | |
132 | ||
133 | /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
134 | * Purpose : disable interrupts from card | |
135 | */ | |
136 | static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
137 | { | |
138 | struct icside_state *state = ec->irq_data; | |
139 | ||
140 | state->enabled = 0; | |
141 | ||
142 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
143 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
144 | } | |
145 | ||
146 | /* Prototype: icside_irqprobe(struct expansion_card *ec) | |
147 | * Purpose : detect an active interrupt from card | |
148 | */ | |
149 | static int icside_irqpending_arcin_v6(struct expansion_card *ec) | |
150 | { | |
151 | struct icside_state *state = ec->irq_data; | |
152 | ||
153 | return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || | |
154 | readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; | |
155 | } | |
156 | ||
157 | static const expansioncard_ops_t icside_ops_arcin_v6 = { | |
158 | .irqenable = icside_irqenable_arcin_v6, | |
159 | .irqdisable = icside_irqdisable_arcin_v6, | |
160 | .irqpending = icside_irqpending_arcin_v6, | |
161 | }; | |
162 | ||
163 | /* | |
164 | * Handle routing of interrupts. This is called before | |
165 | * we write the command to the drive. | |
166 | */ | |
167 | static void icside_maskproc(ide_drive_t *drive, int mask) | |
168 | { | |
898ec223 | 169 | ide_hwif_t *hwif = drive->hwif; |
26839f09 BZ |
170 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
171 | struct icside_state *state = ecard_get_drvdata(ec); | |
1da177e4 LT |
172 | unsigned long flags; |
173 | ||
174 | local_irq_save(flags); | |
175 | ||
176 | state->channel = hwif->channel; | |
177 | ||
178 | if (state->enabled && !mask) { | |
179 | switch (hwif->channel) { | |
180 | case 0: | |
181 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
182 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
183 | break; | |
184 | case 1: | |
185 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
186 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
187 | break; | |
188 | } | |
189 | } else { | |
190 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
191 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
192 | } | |
193 | ||
194 | local_irq_restore(flags); | |
195 | } | |
196 | ||
ac95beed BZ |
197 | static const struct ide_port_ops icside_v6_no_dma_port_ops = { |
198 | .maskproc = icside_maskproc, | |
199 | }; | |
200 | ||
1da177e4 | 201 | #ifdef CONFIG_BLK_DEV_IDEDMA_ICS |
1da177e4 LT |
202 | /* |
203 | * SG-DMA support. | |
204 | * | |
205 | * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. | |
206 | * There is only one DMA controller per card, which means that only | |
207 | * one drive can be accessed at one time. NOTE! We do not enforce that | |
208 | * here, but we rely on the main IDE driver spotting that both | |
209 | * interfaces use the same IRQ, which should guarantee this. | |
210 | */ | |
211 | ||
1da177e4 LT |
212 | /* |
213 | * Configure the IOMD to give the appropriate timings for the transfer | |
214 | * mode being requested. We take the advice of the ATA standards, and | |
215 | * calculate the cycle time based on the transfer mode, and the EIDE | |
216 | * MW DMA specs that the drive provides in the IDENTIFY command. | |
217 | * | |
218 | * We have the following IOMD DMA modes to choose from: | |
219 | * | |
220 | * Type Active Recovery Cycle | |
221 | * A 250 (250) 312 (550) 562 (800) | |
222 | * B 187 250 437 | |
223 | * C 125 (125) 125 (375) 250 (500) | |
224 | * D 62 125 187 | |
225 | * | |
226 | * (figures in brackets are actual measured timings) | |
227 | * | |
228 | * However, we also need to take care of the read/write active and | |
229 | * recovery timings: | |
230 | * | |
231 | * Read Write | |
232 | * Mode Active -- Recovery -- Cycle IOMD type | |
233 | * MW0 215 50 215 480 A | |
234 | * MW1 80 50 50 150 C | |
235 | * MW2 70 25 25 120 C | |
236 | */ | |
88b2b32b | 237 | static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode) |
1da177e4 | 238 | { |
f44ae58a | 239 | int cycle_time, use_dma_info = 0; |
1da177e4 | 240 | |
1da177e4 LT |
241 | switch (xfer_mode) { |
242 | case XFER_MW_DMA_2: | |
243 | cycle_time = 250; | |
244 | use_dma_info = 1; | |
245 | break; | |
246 | ||
247 | case XFER_MW_DMA_1: | |
248 | cycle_time = 250; | |
249 | use_dma_info = 1; | |
250 | break; | |
251 | ||
252 | case XFER_MW_DMA_0: | |
253 | cycle_time = 480; | |
254 | break; | |
255 | ||
256 | case XFER_SW_DMA_2: | |
257 | case XFER_SW_DMA_1: | |
258 | case XFER_SW_DMA_0: | |
259 | cycle_time = 480; | |
260 | break; | |
261 | } | |
262 | ||
263 | /* | |
264 | * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should | |
265 | * take care to note the values in the ID... | |
266 | */ | |
4dde4492 BZ |
267 | if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time) |
268 | cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME]; | |
1da177e4 LT |
269 | |
270 | drive->drive_data = cycle_time; | |
271 | ||
1da177e4 LT |
272 | printk("%s: %s selected (peak %dMB/s)\n", drive->name, |
273 | ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data); | |
1da177e4 LT |
274 | } |
275 | ||
ac95beed BZ |
276 | static const struct ide_port_ops icside_v6_port_ops = { |
277 | .set_dma_mode = icside_set_dma_mode, | |
278 | .maskproc = icside_maskproc, | |
279 | }; | |
280 | ||
15ce926a | 281 | static void icside_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 282 | { |
1da177e4 LT |
283 | } |
284 | ||
1da177e4 LT |
285 | static int icside_dma_end(ide_drive_t *drive) |
286 | { | |
898ec223 | 287 | ide_hwif_t *hwif = drive->hwif; |
f8341c1c | 288 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
1da177e4 LT |
289 | |
290 | drive->waiting_for_dma = 0; | |
291 | ||
f8341c1c | 292 | disable_dma(ec->dma); |
1da177e4 LT |
293 | |
294 | /* Teardown mappings after DMA has completed. */ | |
062f9f02 | 295 | ide_destroy_dmatable(drive); |
1da177e4 | 296 | |
f8341c1c | 297 | return get_dma_residue(ec->dma) != 0; |
1da177e4 LT |
298 | } |
299 | ||
300 | static void icside_dma_start(ide_drive_t *drive) | |
301 | { | |
898ec223 | 302 | ide_hwif_t *hwif = drive->hwif; |
f8341c1c | 303 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
1da177e4 LT |
304 | |
305 | /* We can not enable DMA on both channels simultaneously. */ | |
f8341c1c BZ |
306 | BUG_ON(dma_channel_active(ec->dma)); |
307 | enable_dma(ec->dma); | |
1da177e4 LT |
308 | } |
309 | ||
22981694 | 310 | static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) |
1da177e4 | 311 | { |
898ec223 | 312 | ide_hwif_t *hwif = drive->hwif; |
f8341c1c | 313 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
26839f09 | 314 | struct icside_state *state = ecard_get_drvdata(ec); |
1da177e4 LT |
315 | unsigned int dma_mode; |
316 | ||
22981694 | 317 | if (cmd->tf_flags & IDE_TFLAG_WRITE) |
1da177e4 LT |
318 | dma_mode = DMA_MODE_WRITE; |
319 | else | |
320 | dma_mode = DMA_MODE_READ; | |
321 | ||
322 | /* | |
323 | * We can not enable DMA on both channels. | |
324 | */ | |
f8341c1c | 325 | BUG_ON(dma_channel_active(ec->dma)); |
1da177e4 | 326 | |
1da177e4 LT |
327 | /* |
328 | * Ensure that we have the right interrupt routed. | |
329 | */ | |
330 | icside_maskproc(drive, 0); | |
331 | ||
332 | /* | |
333 | * Route the DMA signals to the correct interface. | |
334 | */ | |
26839f09 | 335 | writeb(state->sel | hwif->channel, state->ioc_base); |
1da177e4 LT |
336 | |
337 | /* | |
338 | * Select the correct timing for this drive. | |
339 | */ | |
f8341c1c | 340 | set_dma_speed(ec->dma, drive->drive_data); |
1da177e4 LT |
341 | |
342 | /* | |
343 | * Tell the DMA engine about the SG table and | |
344 | * data direction. | |
345 | */ | |
22981694 | 346 | set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents); |
f8341c1c | 347 | set_dma_mode(ec->dma, dma_mode); |
1da177e4 LT |
348 | |
349 | drive->waiting_for_dma = 1; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
1da177e4 LT |
354 | static int icside_dma_test_irq(ide_drive_t *drive) |
355 | { | |
898ec223 | 356 | ide_hwif_t *hwif = drive->hwif; |
26839f09 BZ |
357 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
358 | struct icside_state *state = ecard_get_drvdata(ec); | |
1da177e4 LT |
359 | |
360 | return readb(state->irq_port + | |
361 | (hwif->channel ? | |
362 | ICS_ARCIN_V6_INTRSTAT_2 : | |
363 | ICS_ARCIN_V6_INTRSTAT_1)) & 1; | |
364 | } | |
365 | ||
91432f48 | 366 | static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 367 | { |
1da177e4 LT |
368 | hwif->dmatable_cpu = NULL; |
369 | hwif->dmatable_dma = 0; | |
1da177e4 | 370 | |
91432f48 | 371 | return 0; |
1da177e4 | 372 | } |
5e37bdc0 | 373 | |
f37afdac | 374 | static const struct ide_dma_ops icside_v6_dma_ops = { |
5e37bdc0 BZ |
375 | .dma_host_set = icside_dma_host_set, |
376 | .dma_setup = icside_dma_setup, | |
5e37bdc0 BZ |
377 | .dma_start = icside_dma_start, |
378 | .dma_end = icside_dma_end, | |
379 | .dma_test_irq = icside_dma_test_irq, | |
ffa15a69 | 380 | .dma_timeout = ide_dma_timeout, |
de23ec9c | 381 | .dma_lost_irq = ide_dma_lost_irq, |
5e37bdc0 BZ |
382 | }; |
383 | #else | |
384 | #define icside_v6_dma_ops NULL | |
1da177e4 LT |
385 | #endif |
386 | ||
91432f48 BZ |
387 | static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
388 | { | |
389 | return -EOPNOTSUPP; | |
390 | } | |
391 | ||
b25afdf1 BZ |
392 | static void icside_setup_ports(hw_regs_t *hw, void __iomem *base, |
393 | struct cardinfo *info, struct expansion_card *ec) | |
1da177e4 LT |
394 | { |
395 | unsigned long port = (unsigned long)base + info->dataoffset; | |
1da177e4 | 396 | |
b25afdf1 BZ |
397 | hw->io_ports.data_addr = port; |
398 | hw->io_ports.error_addr = port + (1 << info->stepping); | |
399 | hw->io_ports.nsect_addr = port + (2 << info->stepping); | |
400 | hw->io_ports.lbal_addr = port + (3 << info->stepping); | |
401 | hw->io_ports.lbam_addr = port + (4 << info->stepping); | |
402 | hw->io_ports.lbah_addr = port + (5 << info->stepping); | |
403 | hw->io_ports.device_addr = port + (6 << info->stepping); | |
404 | hw->io_ports.status_addr = port + (7 << info->stepping); | |
405 | hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset; | |
406 | ||
407 | hw->irq = ec->irq; | |
408 | hw->dev = &ec->dev; | |
409 | hw->chipset = ide_acorn; | |
1da177e4 LT |
410 | } |
411 | ||
33050ec7 BZ |
412 | static const struct ide_port_info icside_v5_port_info = { |
413 | .host_flags = IDE_HFLAG_NO_DMA, | |
414 | }; | |
415 | ||
d16d7667 | 416 | static int __devinit |
1da177e4 LT |
417 | icside_register_v5(struct icside_state *state, struct expansion_card *ec) |
418 | { | |
1da177e4 | 419 | void __iomem *base; |
48c3c107 | 420 | struct ide_host *host; |
c97c6aca | 421 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
8a69580e | 422 | int ret; |
1da177e4 | 423 | |
10bdaaa0 | 424 | base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); |
1da177e4 LT |
425 | if (!base) |
426 | return -ENOMEM; | |
427 | ||
428 | state->irq_port = base; | |
429 | ||
430 | ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; | |
431 | ec->irqmask = 1; | |
c7b87f3d RK |
432 | |
433 | ecard_setirq(ec, &icside_ops_arcin_v5, state); | |
1da177e4 LT |
434 | |
435 | /* | |
436 | * Be on the safe side - disable interrupts | |
437 | */ | |
438 | icside_irqdisable_arcin_v5(ec, 0); | |
439 | ||
b25afdf1 BZ |
440 | icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec); |
441 | ||
33050ec7 | 442 | host = ide_host_alloc(&icside_v5_port_info, hws); |
48c3c107 | 443 | if (host == NULL) |
1da177e4 | 444 | return -ENODEV; |
1da177e4 | 445 | |
48c3c107 | 446 | state->host = host; |
1da177e4 | 447 | |
26839f09 BZ |
448 | ecard_set_drvdata(ec, state); |
449 | ||
33050ec7 | 450 | ret = ide_host_register(host, &icside_v5_port_info, hws); |
8a69580e BZ |
451 | if (ret) |
452 | goto err_free; | |
1da177e4 LT |
453 | |
454 | return 0; | |
8a69580e BZ |
455 | err_free: |
456 | ide_host_free(host); | |
457 | ecard_set_drvdata(ec, NULL); | |
458 | return ret; | |
1da177e4 LT |
459 | } |
460 | ||
c413b9b9 | 461 | static const struct ide_port_info icside_v6_port_info __initdata = { |
91432f48 | 462 | .init_dma = icside_dma_off_init, |
ac95beed | 463 | .port_ops = &icside_v6_no_dma_port_ops, |
5e37bdc0 | 464 | .dma_ops = &icside_v6_dma_ops, |
c5dd43ec | 465 | .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO, |
c413b9b9 BZ |
466 | .mwdma_mask = ATA_MWDMA2, |
467 | .swdma_mask = ATA_SWDMA2, | |
468 | }; | |
469 | ||
d16d7667 | 470 | static int __devinit |
1da177e4 LT |
471 | icside_register_v6(struct icside_state *state, struct expansion_card *ec) |
472 | { | |
1da177e4 | 473 | void __iomem *ioc_base, *easi_base; |
48c3c107 | 474 | struct ide_host *host; |
1da177e4 LT |
475 | unsigned int sel = 0; |
476 | int ret; | |
c97c6aca | 477 | hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL }; |
c413b9b9 | 478 | struct ide_port_info d = icside_v6_port_info; |
1da177e4 | 479 | |
10bdaaa0 | 480 | ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
1da177e4 LT |
481 | if (!ioc_base) { |
482 | ret = -ENOMEM; | |
483 | goto out; | |
484 | } | |
485 | ||
486 | easi_base = ioc_base; | |
487 | ||
488 | if (ecard_resource_flags(ec, ECARD_RES_EASI)) { | |
10bdaaa0 | 489 | easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); |
1da177e4 LT |
490 | if (!easi_base) { |
491 | ret = -ENOMEM; | |
10bdaaa0 | 492 | goto out; |
1da177e4 LT |
493 | } |
494 | ||
495 | /* | |
496 | * Enable access to the EASI region. | |
497 | */ | |
498 | sel = 1 << 5; | |
499 | } | |
500 | ||
501 | writeb(sel, ioc_base); | |
502 | ||
c7b87f3d | 503 | ecard_setirq(ec, &icside_ops_arcin_v6, state); |
1da177e4 LT |
504 | |
505 | state->irq_port = easi_base; | |
506 | state->ioc_base = ioc_base; | |
26839f09 | 507 | state->sel = sel; |
1da177e4 LT |
508 | |
509 | /* | |
510 | * Be on the safe side - disable interrupts | |
511 | */ | |
512 | icside_irqdisable_arcin_v6(ec, 0); | |
513 | ||
b25afdf1 BZ |
514 | icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec); |
515 | icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec); | |
516 | ||
48c3c107 BZ |
517 | host = ide_host_alloc(&d, hws); |
518 | if (host == NULL) | |
b25afdf1 | 519 | return -ENODEV; |
1da177e4 | 520 | |
48c3c107 | 521 | state->host = host; |
1da177e4 | 522 | |
26839f09 | 523 | ecard_set_drvdata(ec, state); |
1da177e4 | 524 | |
67717e22 | 525 | if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { |
91432f48 | 526 | d.init_dma = icside_dma_init; |
9c391bae | 527 | d.port_ops = &icside_v6_port_ops; |
5e37bdc0 | 528 | d.dma_ops = NULL; |
91432f48 | 529 | } |
1da177e4 | 530 | |
d224b626 | 531 | ret = ide_host_register(host, &d, hws); |
8a69580e BZ |
532 | if (ret) |
533 | goto err_free; | |
1da177e4 LT |
534 | |
535 | return 0; | |
8a69580e BZ |
536 | err_free: |
537 | ide_host_free(host); | |
538 | if (d.dma_ops) | |
539 | free_dma(ec->dma); | |
540 | ecard_set_drvdata(ec, NULL); | |
541 | out: | |
1da177e4 LT |
542 | return ret; |
543 | } | |
544 | ||
545 | static int __devinit | |
546 | icside_probe(struct expansion_card *ec, const struct ecard_id *id) | |
547 | { | |
548 | struct icside_state *state; | |
549 | void __iomem *idmem; | |
550 | int ret; | |
551 | ||
552 | ret = ecard_request_resources(ec); | |
553 | if (ret) | |
554 | goto out; | |
555 | ||
cc60d8ba | 556 | state = kzalloc(sizeof(struct icside_state), GFP_KERNEL); |
1da177e4 LT |
557 | if (!state) { |
558 | ret = -ENOMEM; | |
559 | goto release; | |
560 | } | |
561 | ||
1da177e4 | 562 | state->type = ICS_TYPE_NOTYPE; |
1da177e4 | 563 | |
10bdaaa0 | 564 | idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
1da177e4 LT |
565 | if (idmem) { |
566 | unsigned int type; | |
567 | ||
568 | type = readb(idmem + ICS_IDENT_OFFSET) & 1; | |
569 | type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; | |
570 | type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; | |
571 | type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; | |
10bdaaa0 | 572 | ecardm_iounmap(ec, idmem); |
1da177e4 LT |
573 | |
574 | state->type = type; | |
575 | } | |
576 | ||
577 | switch (state->type) { | |
578 | case ICS_TYPE_A3IN: | |
579 | dev_warn(&ec->dev, "A3IN unsupported\n"); | |
580 | ret = -ENODEV; | |
581 | break; | |
582 | ||
583 | case ICS_TYPE_A3USER: | |
584 | dev_warn(&ec->dev, "A3USER unsupported\n"); | |
585 | ret = -ENODEV; | |
586 | break; | |
587 | ||
588 | case ICS_TYPE_V5: | |
589 | ret = icside_register_v5(state, ec); | |
590 | break; | |
591 | ||
592 | case ICS_TYPE_V6: | |
593 | ret = icside_register_v6(state, ec); | |
594 | break; | |
595 | ||
596 | default: | |
597 | dev_warn(&ec->dev, "unknown interface type\n"); | |
598 | ret = -ENODEV; | |
599 | break; | |
600 | } | |
601 | ||
26839f09 | 602 | if (ret == 0) |
1da177e4 | 603 | goto out; |
1da177e4 LT |
604 | |
605 | kfree(state); | |
606 | release: | |
607 | ecard_release_resources(ec); | |
608 | out: | |
609 | return ret; | |
610 | } | |
611 | ||
612 | static void __devexit icside_remove(struct expansion_card *ec) | |
613 | { | |
614 | struct icside_state *state = ecard_get_drvdata(ec); | |
615 | ||
616 | switch (state->type) { | |
617 | case ICS_TYPE_V5: | |
618 | /* FIXME: tell IDE to stop using the interface */ | |
619 | ||
620 | /* Disable interrupts */ | |
621 | icside_irqdisable_arcin_v5(ec, 0); | |
622 | break; | |
623 | ||
624 | case ICS_TYPE_V6: | |
625 | /* FIXME: tell IDE to stop using the interface */ | |
626 | if (ec->dma != NO_DMA) | |
627 | free_dma(ec->dma); | |
628 | ||
629 | /* Disable interrupts */ | |
630 | icside_irqdisable_arcin_v6(ec, 0); | |
631 | ||
632 | /* Reset the ROM pointer/EASI selection */ | |
633 | writeb(0, state->ioc_base); | |
634 | break; | |
635 | } | |
636 | ||
637 | ecard_set_drvdata(ec, NULL); | |
1da177e4 | 638 | |
1da177e4 LT |
639 | kfree(state); |
640 | ecard_release_resources(ec); | |
641 | } | |
642 | ||
643 | static void icside_shutdown(struct expansion_card *ec) | |
644 | { | |
645 | struct icside_state *state = ecard_get_drvdata(ec); | |
646 | unsigned long flags; | |
647 | ||
648 | /* | |
649 | * Disable interrupts from this card. We need to do | |
650 | * this before disabling EASI since we may be accessing | |
651 | * this register via that region. | |
652 | */ | |
653 | local_irq_save(flags); | |
654 | ec->ops->irqdisable(ec, 0); | |
655 | local_irq_restore(flags); | |
656 | ||
657 | /* | |
658 | * Reset the ROM pointer so that we can read the ROM | |
659 | * after a soft reboot. This also disables access to | |
660 | * the IDE taskfile via the EASI region. | |
661 | */ | |
662 | if (state->ioc_base) | |
663 | writeb(0, state->ioc_base); | |
664 | } | |
665 | ||
666 | static const struct ecard_id icside_ids[] = { | |
667 | { MANU_ICS, PROD_ICS_IDE }, | |
668 | { MANU_ICS2, PROD_ICS2_IDE }, | |
669 | { 0xffff, 0xffff } | |
670 | }; | |
671 | ||
672 | static struct ecard_driver icside_driver = { | |
673 | .probe = icside_probe, | |
674 | .remove = __devexit_p(icside_remove), | |
675 | .shutdown = icside_shutdown, | |
676 | .id_table = icside_ids, | |
677 | .drv = { | |
678 | .name = "icside", | |
679 | }, | |
680 | }; | |
681 | ||
682 | static int __init icside_init(void) | |
683 | { | |
684 | return ecard_register_driver(&icside_driver); | |
685 | } | |
686 | ||
1137fb67 | 687 | static void __exit icside_exit(void) |
8e27cb11 | 688 | { |
1137fb67 | 689 | ecard_remove_driver(&icside_driver); |
8e27cb11 BZ |
690 | } |
691 | ||
1da177e4 LT |
692 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
693 | MODULE_LICENSE("GPL"); | |
694 | MODULE_DESCRIPTION("ICS IDE driver"); | |
695 | ||
696 | module_init(icside_init); | |
8e27cb11 | 697 | module_exit(icside_exit); |