]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (c) 1996-2004 Russell King. |
3 | * | |
4 | * Please note that this platform does not support 32-bit IDE IO. | |
5 | */ | |
6 | ||
1da177e4 LT |
7 | #include <linux/string.h> |
8 | #include <linux/module.h> | |
9 | #include <linux/ioport.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/blkdev.h> | |
12 | #include <linux/errno.h> | |
1da177e4 LT |
13 | #include <linux/ide.h> |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/scatterlist.h> | |
ba5b55d0 | 18 | #include <linux/io.h> |
1da177e4 LT |
19 | |
20 | #include <asm/dma.h> | |
21 | #include <asm/ecard.h> | |
1da177e4 | 22 | |
67717e22 BZ |
23 | #define DRV_NAME "icside" |
24 | ||
1da177e4 LT |
25 | #define ICS_IDENT_OFFSET 0x2280 |
26 | ||
27 | #define ICS_ARCIN_V5_INTRSTAT 0x0000 | |
28 | #define ICS_ARCIN_V5_INTROFFSET 0x0004 | |
29 | #define ICS_ARCIN_V5_IDEOFFSET 0x2800 | |
30 | #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80 | |
31 | #define ICS_ARCIN_V5_IDESTEPPING 6 | |
32 | ||
33 | #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000 | |
34 | #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 | |
35 | #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 | |
36 | #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380 | |
37 | #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000 | |
38 | #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 | |
39 | #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 | |
40 | #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380 | |
41 | #define ICS_ARCIN_V6_IDESTEPPING 6 | |
42 | ||
43 | struct cardinfo { | |
44 | unsigned int dataoffset; | |
45 | unsigned int ctrloffset; | |
46 | unsigned int stepping; | |
47 | }; | |
48 | ||
49 | static struct cardinfo icside_cardinfo_v5 = { | |
50 | .dataoffset = ICS_ARCIN_V5_IDEOFFSET, | |
51 | .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET, | |
52 | .stepping = ICS_ARCIN_V5_IDESTEPPING, | |
53 | }; | |
54 | ||
55 | static struct cardinfo icside_cardinfo_v6_1 = { | |
56 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1, | |
57 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1, | |
58 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
59 | }; | |
60 | ||
61 | static struct cardinfo icside_cardinfo_v6_2 = { | |
62 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2, | |
63 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2, | |
64 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
65 | }; | |
66 | ||
67 | struct icside_state { | |
68 | unsigned int channel; | |
69 | unsigned int enabled; | |
70 | void __iomem *irq_port; | |
71 | void __iomem *ioc_base; | |
26839f09 | 72 | unsigned int sel; |
1da177e4 | 73 | unsigned int type; |
48c3c107 | 74 | struct ide_host *host; |
1da177e4 LT |
75 | }; |
76 | ||
77 | #define ICS_TYPE_A3IN 0 | |
78 | #define ICS_TYPE_A3USER 1 | |
79 | #define ICS_TYPE_V6 3 | |
80 | #define ICS_TYPE_V5 15 | |
81 | #define ICS_TYPE_NOTYPE ((unsigned int)-1) | |
82 | ||
83 | /* ---------------- Version 5 PCB Support Functions --------------------- */ | |
84 | /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
85 | * Purpose : enable interrupts from card | |
86 | */ | |
87 | static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
88 | { | |
89 | struct icside_state *state = ec->irq_data; | |
90 | ||
91 | writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
92 | } | |
93 | ||
94 | /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
95 | * Purpose : disable interrupts from card | |
96 | */ | |
97 | static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
98 | { | |
99 | struct icside_state *state = ec->irq_data; | |
100 | ||
101 | readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
102 | } | |
103 | ||
104 | static const expansioncard_ops_t icside_ops_arcin_v5 = { | |
105 | .irqenable = icside_irqenable_arcin_v5, | |
106 | .irqdisable = icside_irqdisable_arcin_v5, | |
107 | }; | |
108 | ||
109 | ||
110 | /* ---------------- Version 6 PCB Support Functions --------------------- */ | |
111 | /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
112 | * Purpose : enable interrupts from card | |
113 | */ | |
114 | static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
115 | { | |
116 | struct icside_state *state = ec->irq_data; | |
117 | void __iomem *base = state->irq_port; | |
118 | ||
119 | state->enabled = 1; | |
120 | ||
121 | switch (state->channel) { | |
122 | case 0: | |
123 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); | |
124 | readb(base + ICS_ARCIN_V6_INTROFFSET_2); | |
125 | break; | |
126 | case 1: | |
127 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); | |
128 | readb(base + ICS_ARCIN_V6_INTROFFSET_1); | |
129 | break; | |
130 | } | |
131 | } | |
132 | ||
133 | /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
134 | * Purpose : disable interrupts from card | |
135 | */ | |
136 | static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
137 | { | |
138 | struct icside_state *state = ec->irq_data; | |
139 | ||
140 | state->enabled = 0; | |
141 | ||
142 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
143 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
144 | } | |
145 | ||
146 | /* Prototype: icside_irqprobe(struct expansion_card *ec) | |
147 | * Purpose : detect an active interrupt from card | |
148 | */ | |
149 | static int icside_irqpending_arcin_v6(struct expansion_card *ec) | |
150 | { | |
151 | struct icside_state *state = ec->irq_data; | |
152 | ||
153 | return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || | |
154 | readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; | |
155 | } | |
156 | ||
157 | static const expansioncard_ops_t icside_ops_arcin_v6 = { | |
158 | .irqenable = icside_irqenable_arcin_v6, | |
159 | .irqdisable = icside_irqdisable_arcin_v6, | |
160 | .irqpending = icside_irqpending_arcin_v6, | |
161 | }; | |
162 | ||
163 | /* | |
164 | * Handle routing of interrupts. This is called before | |
165 | * we write the command to the drive. | |
166 | */ | |
167 | static void icside_maskproc(ide_drive_t *drive, int mask) | |
168 | { | |
898ec223 | 169 | ide_hwif_t *hwif = drive->hwif; |
26839f09 BZ |
170 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
171 | struct icside_state *state = ecard_get_drvdata(ec); | |
1da177e4 LT |
172 | unsigned long flags; |
173 | ||
174 | local_irq_save(flags); | |
175 | ||
176 | state->channel = hwif->channel; | |
177 | ||
178 | if (state->enabled && !mask) { | |
179 | switch (hwif->channel) { | |
180 | case 0: | |
181 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
182 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
183 | break; | |
184 | case 1: | |
185 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
186 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
187 | break; | |
188 | } | |
189 | } else { | |
190 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
191 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
192 | } | |
193 | ||
194 | local_irq_restore(flags); | |
195 | } | |
196 | ||
ac95beed BZ |
197 | static const struct ide_port_ops icside_v6_no_dma_port_ops = { |
198 | .maskproc = icside_maskproc, | |
199 | }; | |
200 | ||
1da177e4 | 201 | #ifdef CONFIG_BLK_DEV_IDEDMA_ICS |
1da177e4 LT |
202 | /* |
203 | * SG-DMA support. | |
204 | * | |
205 | * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. | |
206 | * There is only one DMA controller per card, which means that only | |
207 | * one drive can be accessed at one time. NOTE! We do not enforce that | |
208 | * here, but we rely on the main IDE driver spotting that both | |
209 | * interfaces use the same IRQ, which should guarantee this. | |
210 | */ | |
211 | ||
1da177e4 LT |
212 | /* |
213 | * Configure the IOMD to give the appropriate timings for the transfer | |
214 | * mode being requested. We take the advice of the ATA standards, and | |
215 | * calculate the cycle time based on the transfer mode, and the EIDE | |
216 | * MW DMA specs that the drive provides in the IDENTIFY command. | |
217 | * | |
218 | * We have the following IOMD DMA modes to choose from: | |
219 | * | |
220 | * Type Active Recovery Cycle | |
221 | * A 250 (250) 312 (550) 562 (800) | |
222 | * B 187 250 437 | |
223 | * C 125 (125) 125 (375) 250 (500) | |
224 | * D 62 125 187 | |
225 | * | |
226 | * (figures in brackets are actual measured timings) | |
227 | * | |
228 | * However, we also need to take care of the read/write active and | |
229 | * recovery timings: | |
230 | * | |
231 | * Read Write | |
232 | * Mode Active -- Recovery -- Cycle IOMD type | |
233 | * MW0 215 50 215 480 A | |
234 | * MW1 80 50 50 150 C | |
235 | * MW2 70 25 25 120 C | |
236 | */ | |
88b2b32b | 237 | static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode) |
1da177e4 | 238 | { |
f44ae58a | 239 | int cycle_time, use_dma_info = 0; |
1da177e4 | 240 | |
1da177e4 LT |
241 | switch (xfer_mode) { |
242 | case XFER_MW_DMA_2: | |
243 | cycle_time = 250; | |
244 | use_dma_info = 1; | |
245 | break; | |
246 | ||
247 | case XFER_MW_DMA_1: | |
248 | cycle_time = 250; | |
249 | use_dma_info = 1; | |
250 | break; | |
251 | ||
252 | case XFER_MW_DMA_0: | |
253 | cycle_time = 480; | |
254 | break; | |
255 | ||
256 | case XFER_SW_DMA_2: | |
257 | case XFER_SW_DMA_1: | |
258 | case XFER_SW_DMA_0: | |
259 | cycle_time = 480; | |
260 | break; | |
261 | } | |
262 | ||
263 | /* | |
264 | * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should | |
265 | * take care to note the values in the ID... | |
266 | */ | |
4dde4492 BZ |
267 | if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time) |
268 | cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME]; | |
1da177e4 LT |
269 | |
270 | drive->drive_data = cycle_time; | |
271 | ||
1da177e4 LT |
272 | printk("%s: %s selected (peak %dMB/s)\n", drive->name, |
273 | ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data); | |
1da177e4 LT |
274 | } |
275 | ||
ac95beed BZ |
276 | static const struct ide_port_ops icside_v6_port_ops = { |
277 | .set_dma_mode = icside_set_dma_mode, | |
278 | .maskproc = icside_maskproc, | |
279 | }; | |
280 | ||
15ce926a | 281 | static void icside_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 282 | { |
1da177e4 LT |
283 | } |
284 | ||
1da177e4 LT |
285 | static int icside_dma_end(ide_drive_t *drive) |
286 | { | |
898ec223 | 287 | ide_hwif_t *hwif = drive->hwif; |
f8341c1c | 288 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
1da177e4 | 289 | |
f8341c1c | 290 | disable_dma(ec->dma); |
1da177e4 | 291 | |
f8341c1c | 292 | return get_dma_residue(ec->dma) != 0; |
1da177e4 LT |
293 | } |
294 | ||
295 | static void icside_dma_start(ide_drive_t *drive) | |
296 | { | |
898ec223 | 297 | ide_hwif_t *hwif = drive->hwif; |
f8341c1c | 298 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
1da177e4 LT |
299 | |
300 | /* We can not enable DMA on both channels simultaneously. */ | |
f8341c1c BZ |
301 | BUG_ON(dma_channel_active(ec->dma)); |
302 | enable_dma(ec->dma); | |
1da177e4 LT |
303 | } |
304 | ||
22981694 | 305 | static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) |
1da177e4 | 306 | { |
898ec223 | 307 | ide_hwif_t *hwif = drive->hwif; |
f8341c1c | 308 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
26839f09 | 309 | struct icside_state *state = ecard_get_drvdata(ec); |
1da177e4 LT |
310 | unsigned int dma_mode; |
311 | ||
22981694 | 312 | if (cmd->tf_flags & IDE_TFLAG_WRITE) |
1da177e4 LT |
313 | dma_mode = DMA_MODE_WRITE; |
314 | else | |
315 | dma_mode = DMA_MODE_READ; | |
316 | ||
317 | /* | |
318 | * We can not enable DMA on both channels. | |
319 | */ | |
f8341c1c | 320 | BUG_ON(dma_channel_active(ec->dma)); |
1da177e4 | 321 | |
1da177e4 LT |
322 | /* |
323 | * Ensure that we have the right interrupt routed. | |
324 | */ | |
325 | icside_maskproc(drive, 0); | |
326 | ||
327 | /* | |
328 | * Route the DMA signals to the correct interface. | |
329 | */ | |
26839f09 | 330 | writeb(state->sel | hwif->channel, state->ioc_base); |
1da177e4 LT |
331 | |
332 | /* | |
333 | * Select the correct timing for this drive. | |
334 | */ | |
f8341c1c | 335 | set_dma_speed(ec->dma, drive->drive_data); |
1da177e4 LT |
336 | |
337 | /* | |
338 | * Tell the DMA engine about the SG table and | |
339 | * data direction. | |
340 | */ | |
22981694 | 341 | set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents); |
f8341c1c | 342 | set_dma_mode(ec->dma, dma_mode); |
1da177e4 | 343 | |
1da177e4 LT |
344 | return 0; |
345 | } | |
346 | ||
1da177e4 LT |
347 | static int icside_dma_test_irq(ide_drive_t *drive) |
348 | { | |
898ec223 | 349 | ide_hwif_t *hwif = drive->hwif; |
26839f09 BZ |
350 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
351 | struct icside_state *state = ecard_get_drvdata(ec); | |
1da177e4 LT |
352 | |
353 | return readb(state->irq_port + | |
354 | (hwif->channel ? | |
355 | ICS_ARCIN_V6_INTRSTAT_2 : | |
356 | ICS_ARCIN_V6_INTRSTAT_1)) & 1; | |
357 | } | |
358 | ||
91432f48 | 359 | static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 360 | { |
1da177e4 LT |
361 | hwif->dmatable_cpu = NULL; |
362 | hwif->dmatable_dma = 0; | |
1da177e4 | 363 | |
91432f48 | 364 | return 0; |
1da177e4 | 365 | } |
5e37bdc0 | 366 | |
f37afdac | 367 | static const struct ide_dma_ops icside_v6_dma_ops = { |
5e37bdc0 BZ |
368 | .dma_host_set = icside_dma_host_set, |
369 | .dma_setup = icside_dma_setup, | |
5e37bdc0 BZ |
370 | .dma_start = icside_dma_start, |
371 | .dma_end = icside_dma_end, | |
372 | .dma_test_irq = icside_dma_test_irq, | |
de23ec9c | 373 | .dma_lost_irq = ide_dma_lost_irq, |
5e37bdc0 BZ |
374 | }; |
375 | #else | |
376 | #define icside_v6_dma_ops NULL | |
1da177e4 LT |
377 | #endif |
378 | ||
91432f48 BZ |
379 | static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
380 | { | |
381 | return -EOPNOTSUPP; | |
382 | } | |
383 | ||
b25afdf1 BZ |
384 | static void icside_setup_ports(hw_regs_t *hw, void __iomem *base, |
385 | struct cardinfo *info, struct expansion_card *ec) | |
1da177e4 LT |
386 | { |
387 | unsigned long port = (unsigned long)base + info->dataoffset; | |
1da177e4 | 388 | |
b25afdf1 BZ |
389 | hw->io_ports.data_addr = port; |
390 | hw->io_ports.error_addr = port + (1 << info->stepping); | |
391 | hw->io_ports.nsect_addr = port + (2 << info->stepping); | |
392 | hw->io_ports.lbal_addr = port + (3 << info->stepping); | |
393 | hw->io_ports.lbam_addr = port + (4 << info->stepping); | |
394 | hw->io_ports.lbah_addr = port + (5 << info->stepping); | |
395 | hw->io_ports.device_addr = port + (6 << info->stepping); | |
396 | hw->io_ports.status_addr = port + (7 << info->stepping); | |
397 | hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset; | |
398 | ||
399 | hw->irq = ec->irq; | |
400 | hw->dev = &ec->dev; | |
1da177e4 LT |
401 | } |
402 | ||
33050ec7 BZ |
403 | static const struct ide_port_info icside_v5_port_info = { |
404 | .host_flags = IDE_HFLAG_NO_DMA, | |
29e52cf7 | 405 | .chipset = ide_acorn, |
33050ec7 BZ |
406 | }; |
407 | ||
d16d7667 | 408 | static int __devinit |
1da177e4 LT |
409 | icside_register_v5(struct icside_state *state, struct expansion_card *ec) |
410 | { | |
1da177e4 | 411 | void __iomem *base; |
48c3c107 | 412 | struct ide_host *host; |
c97c6aca | 413 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
8a69580e | 414 | int ret; |
1da177e4 | 415 | |
10bdaaa0 | 416 | base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); |
1da177e4 LT |
417 | if (!base) |
418 | return -ENOMEM; | |
419 | ||
420 | state->irq_port = base; | |
421 | ||
422 | ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; | |
423 | ec->irqmask = 1; | |
c7b87f3d RK |
424 | |
425 | ecard_setirq(ec, &icside_ops_arcin_v5, state); | |
1da177e4 LT |
426 | |
427 | /* | |
428 | * Be on the safe side - disable interrupts | |
429 | */ | |
430 | icside_irqdisable_arcin_v5(ec, 0); | |
431 | ||
b25afdf1 BZ |
432 | icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec); |
433 | ||
33050ec7 | 434 | host = ide_host_alloc(&icside_v5_port_info, hws); |
48c3c107 | 435 | if (host == NULL) |
1da177e4 | 436 | return -ENODEV; |
1da177e4 | 437 | |
48c3c107 | 438 | state->host = host; |
1da177e4 | 439 | |
26839f09 BZ |
440 | ecard_set_drvdata(ec, state); |
441 | ||
33050ec7 | 442 | ret = ide_host_register(host, &icside_v5_port_info, hws); |
8a69580e BZ |
443 | if (ret) |
444 | goto err_free; | |
1da177e4 LT |
445 | |
446 | return 0; | |
8a69580e BZ |
447 | err_free: |
448 | ide_host_free(host); | |
449 | ecard_set_drvdata(ec, NULL); | |
450 | return ret; | |
1da177e4 LT |
451 | } |
452 | ||
c413b9b9 | 453 | static const struct ide_port_info icside_v6_port_info __initdata = { |
91432f48 | 454 | .init_dma = icside_dma_off_init, |
ac95beed | 455 | .port_ops = &icside_v6_no_dma_port_ops, |
5e37bdc0 | 456 | .dma_ops = &icside_v6_dma_ops, |
c5dd43ec | 457 | .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO, |
c413b9b9 BZ |
458 | .mwdma_mask = ATA_MWDMA2, |
459 | .swdma_mask = ATA_SWDMA2, | |
29e52cf7 | 460 | .chipset = ide_acorn, |
c413b9b9 BZ |
461 | }; |
462 | ||
d16d7667 | 463 | static int __devinit |
1da177e4 LT |
464 | icside_register_v6(struct icside_state *state, struct expansion_card *ec) |
465 | { | |
1da177e4 | 466 | void __iomem *ioc_base, *easi_base; |
48c3c107 | 467 | struct ide_host *host; |
1da177e4 LT |
468 | unsigned int sel = 0; |
469 | int ret; | |
b019447c | 470 | hw_regs_t hw[2], *hws[] = { &hw[0], &hw[1], NULL, NULL }; |
c413b9b9 | 471 | struct ide_port_info d = icside_v6_port_info; |
1da177e4 | 472 | |
10bdaaa0 | 473 | ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
1da177e4 LT |
474 | if (!ioc_base) { |
475 | ret = -ENOMEM; | |
476 | goto out; | |
477 | } | |
478 | ||
479 | easi_base = ioc_base; | |
480 | ||
481 | if (ecard_resource_flags(ec, ECARD_RES_EASI)) { | |
10bdaaa0 | 482 | easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); |
1da177e4 LT |
483 | if (!easi_base) { |
484 | ret = -ENOMEM; | |
10bdaaa0 | 485 | goto out; |
1da177e4 LT |
486 | } |
487 | ||
488 | /* | |
489 | * Enable access to the EASI region. | |
490 | */ | |
491 | sel = 1 << 5; | |
492 | } | |
493 | ||
494 | writeb(sel, ioc_base); | |
495 | ||
c7b87f3d | 496 | ecard_setirq(ec, &icside_ops_arcin_v6, state); |
1da177e4 LT |
497 | |
498 | state->irq_port = easi_base; | |
499 | state->ioc_base = ioc_base; | |
26839f09 | 500 | state->sel = sel; |
1da177e4 LT |
501 | |
502 | /* | |
503 | * Be on the safe side - disable interrupts | |
504 | */ | |
505 | icside_irqdisable_arcin_v6(ec, 0); | |
506 | ||
b25afdf1 BZ |
507 | icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec); |
508 | icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec); | |
509 | ||
48c3c107 BZ |
510 | host = ide_host_alloc(&d, hws); |
511 | if (host == NULL) | |
b25afdf1 | 512 | return -ENODEV; |
1da177e4 | 513 | |
48c3c107 | 514 | state->host = host; |
1da177e4 | 515 | |
26839f09 | 516 | ecard_set_drvdata(ec, state); |
1da177e4 | 517 | |
67717e22 | 518 | if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { |
91432f48 | 519 | d.init_dma = icside_dma_init; |
9c391bae | 520 | d.port_ops = &icside_v6_port_ops; |
5e37bdc0 | 521 | d.dma_ops = NULL; |
91432f48 | 522 | } |
1da177e4 | 523 | |
d224b626 | 524 | ret = ide_host_register(host, &d, hws); |
8a69580e BZ |
525 | if (ret) |
526 | goto err_free; | |
1da177e4 LT |
527 | |
528 | return 0; | |
8a69580e BZ |
529 | err_free: |
530 | ide_host_free(host); | |
531 | if (d.dma_ops) | |
532 | free_dma(ec->dma); | |
533 | ecard_set_drvdata(ec, NULL); | |
534 | out: | |
1da177e4 LT |
535 | return ret; |
536 | } | |
537 | ||
538 | static int __devinit | |
539 | icside_probe(struct expansion_card *ec, const struct ecard_id *id) | |
540 | { | |
541 | struct icside_state *state; | |
542 | void __iomem *idmem; | |
543 | int ret; | |
544 | ||
545 | ret = ecard_request_resources(ec); | |
546 | if (ret) | |
547 | goto out; | |
548 | ||
cc60d8ba | 549 | state = kzalloc(sizeof(struct icside_state), GFP_KERNEL); |
1da177e4 LT |
550 | if (!state) { |
551 | ret = -ENOMEM; | |
552 | goto release; | |
553 | } | |
554 | ||
1da177e4 | 555 | state->type = ICS_TYPE_NOTYPE; |
1da177e4 | 556 | |
10bdaaa0 | 557 | idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
1da177e4 LT |
558 | if (idmem) { |
559 | unsigned int type; | |
560 | ||
561 | type = readb(idmem + ICS_IDENT_OFFSET) & 1; | |
562 | type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; | |
563 | type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; | |
564 | type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; | |
10bdaaa0 | 565 | ecardm_iounmap(ec, idmem); |
1da177e4 LT |
566 | |
567 | state->type = type; | |
568 | } | |
569 | ||
570 | switch (state->type) { | |
571 | case ICS_TYPE_A3IN: | |
572 | dev_warn(&ec->dev, "A3IN unsupported\n"); | |
573 | ret = -ENODEV; | |
574 | break; | |
575 | ||
576 | case ICS_TYPE_A3USER: | |
577 | dev_warn(&ec->dev, "A3USER unsupported\n"); | |
578 | ret = -ENODEV; | |
579 | break; | |
580 | ||
581 | case ICS_TYPE_V5: | |
582 | ret = icside_register_v5(state, ec); | |
583 | break; | |
584 | ||
585 | case ICS_TYPE_V6: | |
586 | ret = icside_register_v6(state, ec); | |
587 | break; | |
588 | ||
589 | default: | |
590 | dev_warn(&ec->dev, "unknown interface type\n"); | |
591 | ret = -ENODEV; | |
592 | break; | |
593 | } | |
594 | ||
26839f09 | 595 | if (ret == 0) |
1da177e4 | 596 | goto out; |
1da177e4 LT |
597 | |
598 | kfree(state); | |
599 | release: | |
600 | ecard_release_resources(ec); | |
601 | out: | |
602 | return ret; | |
603 | } | |
604 | ||
605 | static void __devexit icside_remove(struct expansion_card *ec) | |
606 | { | |
607 | struct icside_state *state = ecard_get_drvdata(ec); | |
608 | ||
609 | switch (state->type) { | |
610 | case ICS_TYPE_V5: | |
611 | /* FIXME: tell IDE to stop using the interface */ | |
612 | ||
613 | /* Disable interrupts */ | |
614 | icside_irqdisable_arcin_v5(ec, 0); | |
615 | break; | |
616 | ||
617 | case ICS_TYPE_V6: | |
618 | /* FIXME: tell IDE to stop using the interface */ | |
619 | if (ec->dma != NO_DMA) | |
620 | free_dma(ec->dma); | |
621 | ||
622 | /* Disable interrupts */ | |
623 | icside_irqdisable_arcin_v6(ec, 0); | |
624 | ||
625 | /* Reset the ROM pointer/EASI selection */ | |
626 | writeb(0, state->ioc_base); | |
627 | break; | |
628 | } | |
629 | ||
630 | ecard_set_drvdata(ec, NULL); | |
1da177e4 | 631 | |
1da177e4 LT |
632 | kfree(state); |
633 | ecard_release_resources(ec); | |
634 | } | |
635 | ||
636 | static void icside_shutdown(struct expansion_card *ec) | |
637 | { | |
638 | struct icside_state *state = ecard_get_drvdata(ec); | |
639 | unsigned long flags; | |
640 | ||
641 | /* | |
642 | * Disable interrupts from this card. We need to do | |
643 | * this before disabling EASI since we may be accessing | |
644 | * this register via that region. | |
645 | */ | |
646 | local_irq_save(flags); | |
647 | ec->ops->irqdisable(ec, 0); | |
648 | local_irq_restore(flags); | |
649 | ||
650 | /* | |
651 | * Reset the ROM pointer so that we can read the ROM | |
652 | * after a soft reboot. This also disables access to | |
653 | * the IDE taskfile via the EASI region. | |
654 | */ | |
655 | if (state->ioc_base) | |
656 | writeb(0, state->ioc_base); | |
657 | } | |
658 | ||
659 | static const struct ecard_id icside_ids[] = { | |
660 | { MANU_ICS, PROD_ICS_IDE }, | |
661 | { MANU_ICS2, PROD_ICS2_IDE }, | |
662 | { 0xffff, 0xffff } | |
663 | }; | |
664 | ||
665 | static struct ecard_driver icside_driver = { | |
666 | .probe = icside_probe, | |
667 | .remove = __devexit_p(icside_remove), | |
668 | .shutdown = icside_shutdown, | |
669 | .id_table = icside_ids, | |
670 | .drv = { | |
671 | .name = "icside", | |
672 | }, | |
673 | }; | |
674 | ||
675 | static int __init icside_init(void) | |
676 | { | |
677 | return ecard_register_driver(&icside_driver); | |
678 | } | |
679 | ||
1137fb67 | 680 | static void __exit icside_exit(void) |
8e27cb11 | 681 | { |
1137fb67 | 682 | ecard_remove_driver(&icside_driver); |
8e27cb11 BZ |
683 | } |
684 | ||
1da177e4 LT |
685 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
686 | MODULE_LICENSE("GPL"); | |
687 | MODULE_DESCRIPTION("ICS IDE driver"); | |
688 | ||
689 | module_init(icside_init); | |
8e27cb11 | 690 | module_exit(icside_exit); |