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1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1995-1998 Mark Lord |
3 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
4 | * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 LT |
6 | * May be copied or modified under the terms of the GNU General Public License |
7 | */ | |
8 | ||
9 | /* | |
10 | * Special Thanks to Mark for his Six years of work. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | /* | |
14 | * This module provides support for the bus-master IDE DMA functions | |
15 | * of various PCI chipsets, including the Intel PIIX (i82371FB for | |
16 | * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and | |
17 | * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) | |
18 | * ("PIIX" stands for "PCI ISA IDE Xcellerator"). | |
19 | * | |
20 | * Pretty much the same code works for other IDE PCI bus-mastering chipsets. | |
21 | * | |
22 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
23 | * | |
24 | * By default, DMA support is prepared for use, but is currently enabled only | |
25 | * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), | |
26 | * or which are recognized as "good" (see table below). Drives with only mode0 | |
27 | * or mode1 (multi/single) DMA should also work with this chipset/driver | |
28 | * (eg. MC2112A) but are not enabled by default. | |
29 | * | |
30 | * Use "hdparm -i" to view modes supported by a given drive. | |
31 | * | |
32 | * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling | |
33 | * DMA support, but must be (re-)compiled against this kernel version or later. | |
34 | * | |
35 | * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. | |
36 | * If problems arise, ide.c will disable DMA operation after a few retries. | |
37 | * This error recovery mechanism works and has been extremely well exercised. | |
38 | * | |
39 | * IDE drives, depending on their vintage, may support several different modes | |
40 | * of DMA operation. The boot-time modes are indicated with a "*" in | |
41 | * the "hdparm -i" listing, and can be changed with *knowledgeable* use of | |
42 | * the "hdparm -X" feature. There is seldom a need to do this, as drives | |
43 | * normally power-up with their "best" PIO/DMA modes enabled. | |
44 | * | |
45 | * Testing has been done with a rather extensive number of drives, | |
46 | * with Quantum & Western Digital models generally outperforming the pack, | |
47 | * and Fujitsu & Conner (and some Seagate which are really Conner) drives | |
48 | * showing more lackluster throughput. | |
49 | * | |
50 | * Keep an eye on /var/adm/messages for "DMA disabled" messages. | |
51 | * | |
52 | * Some people have reported trouble with Intel Zappa motherboards. | |
53 | * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, | |
54 | * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe | |
55 | * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). | |
56 | * | |
57 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for | |
58 | * fixing the problem with the BIOS on some Acer motherboards. | |
59 | * | |
60 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
61 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
62 | * | |
63 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
64 | * at generic DMA -- his patches were referred to when preparing this code. | |
65 | * | |
66 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
67 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
68 | * | |
69 | * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. | |
70 | * | |
71 | * ATA-66/100 and recovery functions, I forgot the rest...... | |
72 | * | |
73 | */ | |
74 | ||
1da177e4 LT |
75 | #include <linux/module.h> |
76 | #include <linux/types.h> | |
77 | #include <linux/kernel.h> | |
78 | #include <linux/timer.h> | |
79 | #include <linux/mm.h> | |
80 | #include <linux/interrupt.h> | |
81 | #include <linux/pci.h> | |
82 | #include <linux/init.h> | |
83 | #include <linux/ide.h> | |
84 | #include <linux/delay.h> | |
85 | #include <linux/scatterlist.h> | |
5c05ff68 | 86 | #include <linux/dma-mapping.h> |
1da177e4 LT |
87 | |
88 | #include <asm/io.h> | |
89 | #include <asm/irq.h> | |
90 | ||
1da177e4 LT |
91 | static const struct drive_list_entry drive_whitelist [] = { |
92 | ||
c2d3ce8c JH |
93 | { "Micropolis 2112A" , NULL }, |
94 | { "CONNER CTMA 4000" , NULL }, | |
95 | { "CONNER CTT8000-A" , NULL }, | |
96 | { "ST34342A" , NULL }, | |
1da177e4 LT |
97 | { NULL , NULL } |
98 | }; | |
99 | ||
100 | static const struct drive_list_entry drive_blacklist [] = { | |
101 | ||
c2d3ce8c JH |
102 | { "WDC AC11000H" , NULL }, |
103 | { "WDC AC22100H" , NULL }, | |
104 | { "WDC AC32500H" , NULL }, | |
105 | { "WDC AC33100H" , NULL }, | |
106 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
107 | { "WDC AC32100H" , "24.09P07" }, |
108 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
109 | { "Compaq CRD-8241B" , NULL }, |
110 | { "CRD-8400B" , NULL }, | |
111 | { "CRD-8480B", NULL }, | |
112 | { "CRD-8482B", NULL }, | |
113 | { "CRD-84" , NULL }, | |
114 | { "SanDisk SDP3B" , NULL }, | |
115 | { "SanDisk SDP3B-64" , NULL }, | |
116 | { "SANYO CD-ROM CRD" , NULL }, | |
117 | { "HITACHI CDR-8" , NULL }, | |
118 | { "HITACHI CDR-8335" , NULL }, | |
119 | { "HITACHI CDR-8435" , NULL }, | |
120 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
121 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
122 | { "CD-532E-A" , NULL }, | |
123 | { "E-IDE CD-ROM CR-840", NULL }, | |
124 | { "CD-ROM Drive/F5A", NULL }, | |
125 | { "WPI CDD-820", NULL }, | |
126 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
127 | { "SAMSUNG CD-ROM SC", NULL }, | |
128 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
129 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 130 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 131 | { "Seagate STT20000A", NULL }, |
b0bc65b9 | 132 | { "CD-ROM CDR_U200", "1.09" }, |
1da177e4 LT |
133 | { NULL , NULL } |
134 | ||
135 | }; | |
136 | ||
1da177e4 LT |
137 | /** |
138 | * ide_dma_intr - IDE DMA interrupt handler | |
139 | * @drive: the drive the interrupt is for | |
140 | * | |
141 | * Handle an interrupt completing a read/write DMA transfer on an | |
142 | * IDE device | |
143 | */ | |
144 | ||
145 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
146 | { | |
147 | u8 stat = 0, dma_stat = 0; | |
148 | ||
149 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
150 | stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ | |
151 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { | |
152 | if (!dma_stat) { | |
153 | struct request *rq = HWGROUP(drive)->rq; | |
154 | ||
4d7a984b | 155 | task_end_request(drive, rq, stat); |
1da177e4 LT |
156 | return ide_stopped; |
157 | } | |
158 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
159 | drive->name, dma_stat); | |
160 | } | |
161 | return ide_error(drive, "dma_intr", stat); | |
162 | } | |
163 | ||
164 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
165 | ||
75d7d963 BZ |
166 | static int ide_dma_good_drive(ide_drive_t *drive) |
167 | { | |
168 | return ide_in_drive_list(drive->id, drive_whitelist); | |
169 | } | |
170 | ||
1da177e4 LT |
171 | /** |
172 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
173 | * @drive: the drive to build the DMA table for | |
174 | * @rq: the request holding the sg list | |
175 | * | |
5c05ff68 BZ |
176 | * Perform the DMA mapping magic necessary to access the source or |
177 | * target buffers of a request via DMA. The lower layers of the | |
1da177e4 | 178 | * kernel provide the necessary cache management so that we can |
5c05ff68 | 179 | * operate in a portable fashion. |
1da177e4 LT |
180 | */ |
181 | ||
182 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
183 | { | |
184 | ide_hwif_t *hwif = HWIF(drive); | |
185 | struct scatterlist *sg = hwif->sg_table; | |
186 | ||
1da177e4 LT |
187 | ide_map_sg(drive, rq); |
188 | ||
189 | if (rq_data_dir(rq) == READ) | |
5c05ff68 | 190 | hwif->sg_dma_direction = DMA_FROM_DEVICE; |
1da177e4 | 191 | else |
5c05ff68 | 192 | hwif->sg_dma_direction = DMA_TO_DEVICE; |
1da177e4 | 193 | |
5c05ff68 BZ |
194 | return dma_map_sg(hwif->dev, sg, hwif->sg_nents, |
195 | hwif->sg_dma_direction); | |
1da177e4 LT |
196 | } |
197 | ||
198 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
199 | ||
062f9f02 | 200 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
201 | /** |
202 | * ide_build_dmatable - build IDE DMA table | |
203 | * | |
204 | * ide_build_dmatable() prepares a dma request. We map the command | |
205 | * to get the pci bus addresses of the buffers and then build up | |
206 | * the PRD table that the IDE layer wants to be fed. The code | |
207 | * knows about the 64K wrap bug in the CS5530. | |
208 | * | |
209 | * Returns the number of built PRD entries if all went okay, | |
210 | * returns 0 otherwise. | |
211 | * | |
212 | * May also be invoked from trm290.c | |
213 | */ | |
214 | ||
215 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
216 | { | |
217 | ide_hwif_t *hwif = HWIF(drive); | |
218 | unsigned int *table = hwif->dmatable_cpu; | |
219 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
220 | unsigned int count = 0; | |
221 | int i; | |
222 | struct scatterlist *sg; | |
223 | ||
224 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
225 | ||
226 | if (!i) | |
227 | return 0; | |
228 | ||
229 | sg = hwif->sg_table; | |
230 | while (i) { | |
231 | u32 cur_addr; | |
232 | u32 cur_len; | |
233 | ||
234 | cur_addr = sg_dma_address(sg); | |
235 | cur_len = sg_dma_len(sg); | |
236 | ||
237 | /* | |
238 | * Fill in the dma table, without crossing any 64kB boundaries. | |
239 | * Most hardware requires 16-bit alignment of all blocks, | |
240 | * but the trm290 requires 32-bit alignment. | |
241 | */ | |
242 | ||
243 | while (cur_len) { | |
244 | if (count++ >= PRD_ENTRIES) { | |
245 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
246 | goto use_pio_instead; | |
247 | } else { | |
248 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
249 | ||
250 | if (bcount > cur_len) | |
251 | bcount = cur_len; | |
252 | *table++ = cpu_to_le32(cur_addr); | |
253 | xcount = bcount & 0xffff; | |
254 | if (is_trm290) | |
255 | xcount = ((xcount >> 2) - 1) << 16; | |
256 | if (xcount == 0x0000) { | |
257 | /* | |
258 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
259 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
260 | * So here we break the 64KB entry into two 32KB entries instead. | |
261 | */ | |
262 | if (count++ >= PRD_ENTRIES) { | |
263 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
264 | goto use_pio_instead; | |
265 | } | |
266 | *table++ = cpu_to_le32(0x8000); | |
267 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
268 | xcount = 0x8000; | |
269 | } | |
270 | *table++ = cpu_to_le32(xcount); | |
271 | cur_addr += bcount; | |
272 | cur_len -= bcount; | |
273 | } | |
274 | } | |
275 | ||
55c16a70 | 276 | sg = sg_next(sg); |
1da177e4 LT |
277 | i--; |
278 | } | |
279 | ||
280 | if (count) { | |
281 | if (!is_trm290) | |
282 | *--table |= cpu_to_le32(0x80000000); | |
283 | return count; | |
284 | } | |
f6fb786d | 285 | |
1da177e4 | 286 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); |
f6fb786d | 287 | |
1da177e4 | 288 | use_pio_instead: |
f6fb786d BZ |
289 | ide_destroy_dmatable(drive); |
290 | ||
1da177e4 LT |
291 | return 0; /* revert to PIO for this request */ |
292 | } | |
293 | ||
294 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
062f9f02 | 295 | #endif |
1da177e4 LT |
296 | |
297 | /** | |
298 | * ide_destroy_dmatable - clean up DMA mapping | |
299 | * @drive: The drive to unmap | |
300 | * | |
301 | * Teardown mappings after DMA has completed. This must be called | |
302 | * after the completion of each use of ide_build_dmatable and before | |
303 | * the next use of ide_build_dmatable. Failure to do so will cause | |
304 | * an oops as only one mapping can be live for each target at a given | |
305 | * time. | |
306 | */ | |
307 | ||
308 | void ide_destroy_dmatable (ide_drive_t *drive) | |
309 | { | |
36501650 | 310 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 311 | |
5c05ff68 | 312 | dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, |
36501650 | 313 | hwif->sg_dma_direction); |
1da177e4 LT |
314 | } |
315 | ||
316 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
317 | ||
062f9f02 | 318 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
319 | /** |
320 | * config_drive_for_dma - attempt to activate IDE DMA | |
321 | * @drive: the drive to place in DMA mode | |
322 | * | |
323 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
324 | * then attempt to place it into DMA mode. Drives that are known to | |
325 | * support DMA but predate the DMA properties or that are known | |
326 | * to have DMA handling bugs are also set up appropriately based | |
327 | * on the good/bad drive lists. | |
328 | */ | |
329 | ||
330 | static int config_drive_for_dma (ide_drive_t *drive) | |
331 | { | |
1116fae5 | 332 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 333 | struct hd_driveid *id = drive->id; |
1da177e4 | 334 | |
33c1002e BZ |
335 | if (drive->media != ide_disk) { |
336 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
bcbf6ee3 | 337 | return 0; |
33c1002e | 338 | } |
1116fae5 | 339 | |
0ae2e178 BZ |
340 | /* |
341 | * Enable DMA on any drive that has | |
342 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
343 | */ | |
344 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
345 | return 1; | |
346 | ||
347 | /* | |
348 | * Enable DMA on any drive that has mode2 DMA | |
349 | * (multi or single) enabled | |
350 | */ | |
351 | if (id->field_valid & 2) /* regular DMA */ | |
352 | if ((id->dma_mword & 0x404) == 0x404 || | |
353 | (id->dma_1word & 0x404) == 0x404) | |
354 | return 1; | |
3608b5d7 | 355 | |
0ae2e178 BZ |
356 | /* Consult the list of known "good" drives */ |
357 | if (ide_dma_good_drive(drive)) | |
358 | return 1; | |
359 | ||
360 | return 0; | |
1da177e4 LT |
361 | } |
362 | ||
363 | /** | |
364 | * dma_timer_expiry - handle a DMA timeout | |
365 | * @drive: Drive that timed out | |
366 | * | |
367 | * An IDE DMA transfer timed out. In the event of an error we ask | |
368 | * the driver to resolve the problem, if a DMA transfer is still | |
369 | * in progress we continue to wait (arguably we need to add a | |
370 | * secondary 'I don't care what the drive thinks' timeout here) | |
371 | * Finally if we have an interrupt we let it complete the I/O. | |
372 | * But only one time - we clear expiry and if it's still not | |
373 | * completed after WAIT_CMD, we error and retry in PIO. | |
374 | * This can occur if an interrupt is lost or due to hang or bugs. | |
375 | */ | |
376 | ||
377 | static int dma_timer_expiry (ide_drive_t *drive) | |
378 | { | |
379 | ide_hwif_t *hwif = HWIF(drive); | |
380 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
381 | ||
382 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
383 | drive->name, dma_stat); | |
384 | ||
385 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
386 | return WAIT_CMD; | |
387 | ||
388 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
389 | ||
390 | /* 1 dmaing, 2 error, 4 intr */ | |
391 | if (dma_stat & 2) /* ERROR */ | |
392 | return -1; | |
393 | ||
394 | if (dma_stat & 1) /* DMAing */ | |
395 | return WAIT_CMD; | |
396 | ||
397 | if (dma_stat & 4) /* Got an Interrupt */ | |
398 | return WAIT_CMD; | |
399 | ||
400 | return 0; /* Status is unknown -- reset the bus */ | |
401 | } | |
402 | ||
403 | /** | |
15ce926a | 404 | * ide_dma_host_set - Enable/disable DMA on a host |
1da177e4 LT |
405 | * @drive: drive to control |
406 | * | |
15ce926a BZ |
407 | * Enable/disable DMA on an IDE controller following generic |
408 | * bus-mastering IDE controller behaviour. | |
1da177e4 LT |
409 | */ |
410 | ||
15ce926a | 411 | void ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 LT |
412 | { |
413 | ide_hwif_t *hwif = HWIF(drive); | |
414 | u8 unit = (drive->select.b.unit & 0x01); | |
415 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
416 | ||
15ce926a BZ |
417 | if (on) |
418 | dma_stat |= (1 << (5 + unit)); | |
419 | else | |
420 | dma_stat &= ~(1 << (5 + unit)); | |
421 | ||
422 | hwif->OUTB(dma_stat, hwif->dma_status); | |
1da177e4 LT |
423 | } |
424 | ||
15ce926a | 425 | EXPORT_SYMBOL_GPL(ide_dma_host_set); |
4a546e04 | 426 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
427 | |
428 | /** | |
7469aaf6 | 429 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
430 | * @drive: drive to control |
431 | * | |
432 | * Turn off the current DMA on this IDE controller. | |
433 | */ | |
434 | ||
7469aaf6 | 435 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
436 | { |
437 | drive->using_dma = 0; | |
438 | ide_toggle_bounce(drive, 0); | |
439 | ||
15ce926a | 440 | drive->hwif->dma_host_set(drive, 0); |
1da177e4 LT |
441 | } |
442 | ||
7469aaf6 | 443 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
444 | |
445 | /** | |
7469aaf6 | 446 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
447 | * @drive: drive to disable DMA on |
448 | * | |
449 | * Disable IDE DMA for a device on this IDE controller. | |
450 | * Inform the user that DMA has been disabled. | |
451 | */ | |
452 | ||
7469aaf6 | 453 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
454 | { |
455 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
4a546e04 | 456 | ide_dma_off_quietly(drive); |
1da177e4 LT |
457 | } |
458 | ||
7469aaf6 | 459 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 | 460 | |
1da177e4 | 461 | /** |
4a546e04 | 462 | * ide_dma_on - Enable DMA on a device |
1da177e4 LT |
463 | * @drive: drive to enable DMA on |
464 | * | |
465 | * Enable IDE DMA for a device on this IDE controller. | |
466 | */ | |
4a546e04 BZ |
467 | |
468 | void ide_dma_on(ide_drive_t *drive) | |
1da177e4 | 469 | { |
1da177e4 LT |
470 | drive->using_dma = 1; |
471 | ide_toggle_bounce(drive, 1); | |
472 | ||
15ce926a | 473 | drive->hwif->dma_host_set(drive, 1); |
1da177e4 LT |
474 | } |
475 | ||
4a546e04 | 476 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
477 | /** |
478 | * ide_dma_setup - begin a DMA phase | |
479 | * @drive: target device | |
480 | * | |
481 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
482 | * and then set up the DMA transfer registers for a device | |
483 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
484 | * override this function if they need to | |
485 | * | |
486 | * Returns 0 on success. If a PIO fallback is required then 1 | |
487 | * is returned. | |
488 | */ | |
489 | ||
490 | int ide_dma_setup(ide_drive_t *drive) | |
491 | { | |
492 | ide_hwif_t *hwif = drive->hwif; | |
493 | struct request *rq = HWGROUP(drive)->rq; | |
494 | unsigned int reading; | |
495 | u8 dma_stat; | |
496 | ||
497 | if (rq_data_dir(rq)) | |
498 | reading = 0; | |
499 | else | |
500 | reading = 1 << 3; | |
501 | ||
502 | /* fall back to pio! */ | |
503 | if (!ide_build_dmatable(drive, rq)) { | |
504 | ide_map_sg(drive, rq); | |
505 | return 1; | |
506 | } | |
507 | ||
508 | /* PRD table */ | |
2ad1e558 | 509 | if (hwif->mmio) |
0ecdca26 BZ |
510 | writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); |
511 | else | |
512 | outl(hwif->dmatable_dma, hwif->dma_prdtable); | |
1da177e4 LT |
513 | |
514 | /* specify r/w */ | |
515 | hwif->OUTB(reading, hwif->dma_command); | |
516 | ||
517 | /* read dma_status for INTR & ERROR flags */ | |
518 | dma_stat = hwif->INB(hwif->dma_status); | |
519 | ||
520 | /* clear INTR & ERROR flags */ | |
521 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
522 | drive->waiting_for_dma = 1; | |
523 | return 0; | |
524 | } | |
525 | ||
526 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
527 | ||
528 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
529 | { | |
530 | /* issue cmd to drive */ | |
531 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
532 | } | |
533 | ||
534 | void ide_dma_start(ide_drive_t *drive) | |
535 | { | |
536 | ide_hwif_t *hwif = HWIF(drive); | |
537 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
538 | ||
539 | /* Note that this is done *after* the cmd has | |
540 | * been issued to the drive, as per the BM-IDE spec. | |
541 | * The Promise Ultra33 doesn't work correctly when | |
542 | * we do this part before issuing the drive cmd. | |
543 | */ | |
544 | /* start DMA */ | |
545 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
546 | hwif->dma = 1; | |
547 | wmb(); | |
548 | } | |
549 | ||
550 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
551 | ||
552 | /* returns 1 on error, 0 otherwise */ | |
553 | int __ide_dma_end (ide_drive_t *drive) | |
554 | { | |
555 | ide_hwif_t *hwif = HWIF(drive); | |
556 | u8 dma_stat = 0, dma_cmd = 0; | |
557 | ||
558 | drive->waiting_for_dma = 0; | |
559 | /* get dma_command mode */ | |
560 | dma_cmd = hwif->INB(hwif->dma_command); | |
561 | /* stop DMA */ | |
562 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
563 | /* get DMA status */ | |
564 | dma_stat = hwif->INB(hwif->dma_status); | |
565 | /* clear the INTR & ERROR bits */ | |
566 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
567 | /* purge DMA mappings */ | |
568 | ide_destroy_dmatable(drive); | |
569 | /* verify good DMA status */ | |
570 | hwif->dma = 0; | |
571 | wmb(); | |
572 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
573 | } | |
574 | ||
575 | EXPORT_SYMBOL(__ide_dma_end); | |
576 | ||
577 | /* returns 1 if dma irq issued, 0 otherwise */ | |
578 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
579 | { | |
580 | ide_hwif_t *hwif = HWIF(drive); | |
581 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
582 | ||
1da177e4 LT |
583 | /* return 1 if INTR asserted */ |
584 | if ((dma_stat & 4) == 4) | |
585 | return 1; | |
586 | if (!drive->waiting_for_dma) | |
587 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
588 | drive->name, __FUNCTION__); | |
589 | return 0; | |
590 | } | |
0ae2e178 BZ |
591 | #else |
592 | static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } | |
1da177e4 LT |
593 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
594 | ||
595 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
596 | { | |
597 | struct hd_driveid *id = drive->id; | |
598 | ||
65e5f2e3 | 599 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
600 | if (blacklist) { |
601 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
602 | drive->name, id->model); | |
603 | return blacklist; | |
604 | } | |
605 | return 0; | |
606 | } | |
607 | ||
608 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
609 | ||
2d5eaa6d BZ |
610 | static const u8 xfer_mode_bases[] = { |
611 | XFER_UDMA_0, | |
612 | XFER_MW_DMA_0, | |
613 | XFER_SW_DMA_0, | |
614 | }; | |
615 | ||
7670df73 | 616 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) |
2d5eaa6d BZ |
617 | { |
618 | struct hd_driveid *id = drive->id; | |
619 | ide_hwif_t *hwif = drive->hwif; | |
620 | unsigned int mask = 0; | |
621 | ||
622 | switch(base) { | |
623 | case XFER_UDMA_0: | |
624 | if ((id->field_valid & 4) == 0) | |
625 | break; | |
626 | ||
2d5eaa6d | 627 | if (hwif->udma_filter) |
851dd33b SS |
628 | mask = hwif->udma_filter(drive); |
629 | else | |
630 | mask = hwif->ultra_mask; | |
631 | mask &= id->dma_ultra; | |
2d5eaa6d | 632 | |
7670df73 BZ |
633 | /* |
634 | * avoid false cable warning from eighty_ninty_three() | |
635 | */ | |
636 | if (req_mode > XFER_UDMA_2) { | |
637 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
638 | mask &= 0x07; | |
639 | } | |
2d5eaa6d BZ |
640 | break; |
641 | case XFER_MW_DMA_0: | |
b4e44369 SS |
642 | if ((id->field_valid & 2) == 0) |
643 | break; | |
644 | if (hwif->mdma_filter) | |
645 | mask = hwif->mdma_filter(drive); | |
646 | else | |
647 | mask = hwif->mwdma_mask; | |
648 | mask &= id->dma_mword; | |
2d5eaa6d BZ |
649 | break; |
650 | case XFER_SW_DMA_0: | |
15a4f943 | 651 | if (id->field_valid & 2) { |
3649c06e | 652 | mask = id->dma_1word & hwif->swdma_mask; |
15a4f943 BZ |
653 | } else if (id->tDMA) { |
654 | /* | |
655 | * ide_fix_driveid() doesn't convert ->tDMA to the | |
656 | * CPU endianness so we need to do it here | |
657 | */ | |
658 | u8 mode = le16_to_cpu(id->tDMA); | |
659 | ||
660 | /* | |
661 | * if the mode is valid convert it to the mask | |
662 | * (the maximum allowed mode is XFER_SW_DMA_2) | |
663 | */ | |
664 | if (mode <= 2) | |
665 | mask = ((2 << mode) - 1) & hwif->swdma_mask; | |
666 | } | |
2d5eaa6d BZ |
667 | break; |
668 | default: | |
669 | BUG(); | |
670 | break; | |
671 | } | |
672 | ||
673 | return mask; | |
674 | } | |
675 | ||
676 | /** | |
7670df73 | 677 | * ide_find_dma_mode - compute DMA speed |
2d5eaa6d | 678 | * @drive: IDE device |
7670df73 BZ |
679 | * @req_mode: requested mode |
680 | * | |
681 | * Checks the drive/host capabilities and finds the speed to use for | |
682 | * the DMA transfer. The speed is then limited by the requested mode. | |
2d5eaa6d | 683 | * |
7670df73 BZ |
684 | * Returns 0 if the drive/host combination is incapable of DMA transfers |
685 | * or if the requested mode is not a DMA mode. | |
2d5eaa6d BZ |
686 | */ |
687 | ||
7670df73 | 688 | u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) |
2d5eaa6d BZ |
689 | { |
690 | ide_hwif_t *hwif = drive->hwif; | |
691 | unsigned int mask; | |
692 | int x, i; | |
693 | u8 mode = 0; | |
694 | ||
33c1002e BZ |
695 | if (drive->media != ide_disk) { |
696 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
697 | return 0; | |
698 | } | |
2d5eaa6d BZ |
699 | |
700 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
7670df73 BZ |
701 | if (req_mode < xfer_mode_bases[i]) |
702 | continue; | |
703 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); | |
2d5eaa6d BZ |
704 | x = fls(mask) - 1; |
705 | if (x >= 0) { | |
706 | mode = xfer_mode_bases[i] + x; | |
707 | break; | |
708 | } | |
709 | } | |
710 | ||
75d7d963 BZ |
711 | if (hwif->chipset == ide_acorn && mode == 0) { |
712 | /* | |
713 | * is this correct? | |
714 | */ | |
715 | if (ide_dma_good_drive(drive) && drive->id->eide_dma_time < 150) | |
716 | mode = XFER_MW_DMA_1; | |
717 | } | |
718 | ||
3ab7efe8 BZ |
719 | mode = min(mode, req_mode); |
720 | ||
721 | printk(KERN_INFO "%s: %s mode selected\n", drive->name, | |
d34887da | 722 | mode ? ide_xfer_verbose(mode) : "no DMA"); |
2d5eaa6d | 723 | |
3ab7efe8 | 724 | return mode; |
2d5eaa6d BZ |
725 | } |
726 | ||
7670df73 | 727 | EXPORT_SYMBOL_GPL(ide_find_dma_mode); |
2d5eaa6d | 728 | |
0ae2e178 | 729 | static int ide_tune_dma(ide_drive_t *drive) |
29e744d0 | 730 | { |
8704de8f | 731 | ide_hwif_t *hwif = drive->hwif; |
29e744d0 BZ |
732 | u8 speed; |
733 | ||
c223701c | 734 | if (noautodma || drive->nodma || (drive->id->capability & 1) == 0) |
122ab088 BZ |
735 | return 0; |
736 | ||
737 | /* consult the list of known "bad" drives */ | |
738 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
739 | return 0; |
740 | ||
3ab7efe8 BZ |
741 | if (ide_id_dma_bug(drive)) |
742 | return 0; | |
743 | ||
8704de8f | 744 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) |
0ae2e178 BZ |
745 | return config_drive_for_dma(drive); |
746 | ||
29e744d0 BZ |
747 | speed = ide_max_dma_mode(drive); |
748 | ||
8704de8f BZ |
749 | if (!speed) { |
750 | /* is this really correct/needed? */ | |
751 | if ((hwif->host_flags & IDE_HFLAG_CY82C693) && | |
752 | ide_dma_good_drive(drive)) | |
753 | return 1; | |
754 | else | |
755 | return 0; | |
756 | } | |
29e744d0 | 757 | |
8704de8f | 758 | if (hwif->host_flags & IDE_HFLAG_NO_SET_MODE) |
88b2b32b BZ |
759 | return 0; |
760 | ||
761 | if (ide_set_dma_mode(drive, speed)) | |
4728d546 | 762 | return 0; |
29e744d0 | 763 | |
4728d546 | 764 | return 1; |
29e744d0 BZ |
765 | } |
766 | ||
0ae2e178 BZ |
767 | static int ide_dma_check(ide_drive_t *drive) |
768 | { | |
769 | ide_hwif_t *hwif = drive->hwif; | |
770 | int vdma = (hwif->host_flags & IDE_HFLAG_VDMA)? 1 : 0; | |
771 | ||
772 | if (!vdma && ide_tune_dma(drive)) | |
773 | return 0; | |
774 | ||
775 | /* TODO: always do PIO fallback */ | |
776 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) | |
777 | return -1; | |
778 | ||
779 | ide_set_max_pio(drive); | |
780 | ||
781 | return vdma ? 0 : -1; | |
782 | } | |
783 | ||
3ab7efe8 | 784 | int ide_id_dma_bug(ide_drive_t *drive) |
1da177e4 | 785 | { |
3ab7efe8 | 786 | struct hd_driveid *id = drive->id; |
1da177e4 LT |
787 | |
788 | if (id->field_valid & 4) { | |
789 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
3ab7efe8 | 790 | goto err_out; |
1da177e4 LT |
791 | } else if (id->field_valid & 2) { |
792 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
3ab7efe8 | 793 | goto err_out; |
1da177e4 | 794 | } |
3ab7efe8 BZ |
795 | return 0; |
796 | err_out: | |
797 | printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); | |
798 | return 1; | |
1da177e4 LT |
799 | } |
800 | ||
3608b5d7 BZ |
801 | int ide_set_dma(ide_drive_t *drive) |
802 | { | |
3608b5d7 BZ |
803 | int rc; |
804 | ||
7b905994 BZ |
805 | /* |
806 | * Force DMAing for the beginning of the check. | |
807 | * Some chipsets appear to do interesting | |
808 | * things, if not checked and cleared. | |
809 | * PARANOIA!!! | |
810 | */ | |
4a546e04 | 811 | ide_dma_off_quietly(drive); |
3608b5d7 | 812 | |
7b905994 BZ |
813 | rc = ide_dma_check(drive); |
814 | if (rc) | |
815 | return rc; | |
3608b5d7 | 816 | |
4a546e04 BZ |
817 | ide_dma_on(drive); |
818 | ||
819 | return 0; | |
3608b5d7 BZ |
820 | } |
821 | ||
1da177e4 | 822 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
841d2a9b | 823 | void ide_dma_lost_irq (ide_drive_t *drive) |
1da177e4 LT |
824 | { |
825 | printk("%s: DMA interrupt recovery\n", drive->name); | |
1da177e4 LT |
826 | } |
827 | ||
841d2a9b | 828 | EXPORT_SYMBOL(ide_dma_lost_irq); |
1da177e4 | 829 | |
c283f5db | 830 | void ide_dma_timeout (ide_drive_t *drive) |
1da177e4 | 831 | { |
c283f5db SS |
832 | ide_hwif_t *hwif = HWIF(drive); |
833 | ||
1da177e4 | 834 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
1da177e4 | 835 | |
c283f5db SS |
836 | if (hwif->ide_dma_test_irq(drive)) |
837 | return; | |
838 | ||
839 | hwif->ide_dma_end(drive); | |
1da177e4 LT |
840 | } |
841 | ||
c283f5db | 842 | EXPORT_SYMBOL(ide_dma_timeout); |
1da177e4 | 843 | |
a02bfd3c | 844 | static void ide_release_dma_engine(ide_hwif_t *hwif) |
1da177e4 LT |
845 | { |
846 | if (hwif->dmatable_cpu) { | |
36501650 BZ |
847 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
848 | ||
849 | pci_free_consistent(pdev, PRD_ENTRIES * PRD_BYTES, | |
850 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
1da177e4 LT |
851 | hwif->dmatable_cpu = NULL; |
852 | } | |
1da177e4 LT |
853 | } |
854 | ||
855 | static int ide_release_iomio_dma(ide_hwif_t *hwif) | |
856 | { | |
1da177e4 | 857 | release_region(hwif->dma_base, 8); |
020e322d SS |
858 | if (hwif->extra_ports) |
859 | release_region(hwif->extra_base, hwif->extra_ports); | |
1da177e4 LT |
860 | return 1; |
861 | } | |
862 | ||
863 | /* | |
864 | * Needed for allowing full modular support of ide-driver | |
865 | */ | |
dc844e05 | 866 | int ide_release_dma(ide_hwif_t *hwif) |
1da177e4 | 867 | { |
dc844e05 SS |
868 | ide_release_dma_engine(hwif); |
869 | ||
2ad1e558 | 870 | if (hwif->mmio) |
1da177e4 | 871 | return 1; |
dc844e05 SS |
872 | else |
873 | return ide_release_iomio_dma(hwif); | |
1da177e4 LT |
874 | } |
875 | ||
876 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) | |
877 | { | |
36501650 BZ |
878 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
879 | ||
880 | hwif->dmatable_cpu = pci_alloc_consistent(pdev, | |
1da177e4 LT |
881 | PRD_ENTRIES * PRD_BYTES, |
882 | &hwif->dmatable_dma); | |
883 | ||
884 | if (hwif->dmatable_cpu) | |
885 | return 0; | |
886 | ||
dc844e05 SS |
887 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
888 | hwif->cds->name); | |
1da177e4 | 889 | |
1da177e4 LT |
890 | return 1; |
891 | } | |
892 | ||
ecf32796 | 893 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base) |
1da177e4 LT |
894 | { |
895 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
896 | ||
1da177e4 LT |
897 | return 0; |
898 | } | |
899 | ||
ecf32796 | 900 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base) |
1da177e4 LT |
901 | { |
902 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
ecf32796 | 903 | hwif->name, base, base + 7); |
020e322d | 904 | |
ecf32796 | 905 | if (!request_region(base, 8, hwif->name)) { |
1da177e4 LT |
906 | printk(" -- Error, ports in use.\n"); |
907 | return 1; | |
908 | } | |
020e322d | 909 | |
020e322d SS |
910 | if (hwif->cds->extra) { |
911 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
912 | ||
913 | if (!hwif->mate || !hwif->mate->extra_ports) { | |
914 | if (!request_region(hwif->extra_base, | |
915 | hwif->cds->extra, hwif->cds->name)) { | |
916 | printk(" -- Error, extra ports in use.\n"); | |
ecf32796 | 917 | release_region(base, 8); |
020e322d SS |
918 | return 1; |
919 | } | |
920 | hwif->extra_ports = hwif->cds->extra; | |
921 | } | |
1da177e4 | 922 | } |
020e322d | 923 | |
1da177e4 LT |
924 | return 0; |
925 | } | |
926 | ||
ecf32796 | 927 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base) |
1da177e4 | 928 | { |
2ad1e558 | 929 | if (hwif->mmio) |
ecf32796 | 930 | return ide_mapped_mmio_dma(hwif, base); |
2ad1e558 | 931 | |
ecf32796 | 932 | return ide_iomio_dma(hwif, base); |
1da177e4 LT |
933 | } |
934 | ||
ecf32796 | 935 | void ide_setup_dma(ide_hwif_t *hwif, unsigned long base) |
1da177e4 | 936 | { |
4e5a68ae SS |
937 | u8 dma_stat; |
938 | ||
ecf32796 | 939 | if (ide_dma_iobase(hwif, base)) |
1da177e4 LT |
940 | return; |
941 | ||
942 | if (ide_allocate_dma_engine(hwif)) { | |
943 | ide_release_dma(hwif); | |
944 | return; | |
945 | } | |
946 | ||
a02bfd3c BZ |
947 | hwif->dma_base = base; |
948 | ||
ecf32796 SS |
949 | if (!hwif->dma_command) |
950 | hwif->dma_command = hwif->dma_base + 0; | |
951 | if (!hwif->dma_vendor1) | |
952 | hwif->dma_vendor1 = hwif->dma_base + 1; | |
953 | if (!hwif->dma_status) | |
954 | hwif->dma_status = hwif->dma_base + 2; | |
955 | if (!hwif->dma_vendor3) | |
956 | hwif->dma_vendor3 = hwif->dma_base + 3; | |
957 | if (!hwif->dma_prdtable) | |
958 | hwif->dma_prdtable = hwif->dma_base + 4; | |
1da177e4 | 959 | |
15ce926a BZ |
960 | if (!hwif->dma_host_set) |
961 | hwif->dma_host_set = &ide_dma_host_set; | |
1da177e4 LT |
962 | if (!hwif->dma_setup) |
963 | hwif->dma_setup = &ide_dma_setup; | |
964 | if (!hwif->dma_exec_cmd) | |
965 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
966 | if (!hwif->dma_start) | |
967 | hwif->dma_start = &ide_dma_start; | |
968 | if (!hwif->ide_dma_end) | |
969 | hwif->ide_dma_end = &__ide_dma_end; | |
970 | if (!hwif->ide_dma_test_irq) | |
971 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
c283f5db SS |
972 | if (!hwif->dma_timeout) |
973 | hwif->dma_timeout = &ide_dma_timeout; | |
841d2a9b SS |
974 | if (!hwif->dma_lost_irq) |
975 | hwif->dma_lost_irq = &ide_dma_lost_irq; | |
1da177e4 | 976 | |
4e5a68ae SS |
977 | dma_stat = hwif->INB(hwif->dma_status); |
978 | printk(KERN_CONT ", BIOS settings: %s:%s, %s:%s\n", | |
979 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "PIO", | |
980 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "PIO"); | |
1da177e4 LT |
981 | } |
982 | ||
983 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
984 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |